CN203338430U - Four-door double-control access controller - Google Patents
Four-door double-control access controller Download PDFInfo
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- CN203338430U CN203338430U CN201320077990XU CN201320077990U CN203338430U CN 203338430 U CN203338430 U CN 203338430U CN 201320077990X U CN201320077990X U CN 201320077990XU CN 201320077990 U CN201320077990 U CN 201320077990U CN 203338430 U CN203338430 U CN 203338430U
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Abstract
The utility model discloses a four-door double-control access controller, comprising a power supply unit (1), a core unit (2), a communication unit (3), a CPLD/FPGA (complex programmable logic device/field programmable gata array) logic unit (4), an I/O (input/output) interface unit (5) and a WG26 interface/RS485 interface unit (6). The four-door double-control access controller has the advantages that the four-door double-control access controller can meet the application environment, which has high demands on safety control level, and requires a plurality of identification card reading devices to be arranged, and a plurality of managers; a wiegand interface and an RS485 interface can be multiplexed; software configuration and hardware gating can be achieved; the four-door double-control access controller has the characteristics of high identity recognition efficiency, high information retrieval and feedback efficiency, large information memory capacity, high reliability, reasonable comprehensive wiring, low cost and the like.
Description
Technical field
The utility model relates to gate inhibition's management and control technical field, particularly a kind of four dual control access controllers.
Background technology
Access control system in intelligent residential district, the field such as parking management system, building automation is widely applied.Access controller is the key equipment of access control system.Simple gate and two everys are prohibited controller and are widely applied in access control system, but high for the security management and control class requirement, need a large amount of identification reader devices of arranging, need a fairly large number of enterprises and institutions of managerial personnel, government bodies, the applied environments such as army, no matter be from the identity information recognition efficiency, information retrieval and feedback efficiency, information storage capacity, the reliability of product, the technical factors such as the rationality of comprehensive wiring, or consider from factors such as the overall costs of access control system, adopting simple gate and two access controllers is not solution preferably.
On the other hand, in access control system, card reader commonly used is mainly Wei root interface card reader at present, along with low frequency card reader and ISO-1443A/B high frequency card reader are substituted by the CPU card reader gradually, requirement to the transmission range of gate inhibition's control unit interface and data volume is also more and more higher, supports the access controller of RS485 interface card reader progressively to become main flow.
Summary of the invention
The purpose of this utility model is to provide a kind of four dual control access controllers, the gateway of every controller energy 4 doors of two-way control (or passage), its Peripheral Interface comprises 8 Lu Weigen input interfaces and 8 road RS485 interfaces, 4 road door lock output control interfaces, 4 road door magnetic feed back input interfaces, 4 road door open button input interfaces, 2 tunnel warning input interfaces, 2 tunnel warning output interfaces, 1 road dismantling-proof alarming input interface, 1 road RS232 debugging interface and 1 road 10M/100M self-adaptation Ethernet interface etc., wherein 8 Lu Weigen input interfaces and RS485 interface duplex, but software configuration, the hardware gating.
A kind of four dual control access controllers of the utility model comprise: power supply unit, core cell, communication unit, CPLD/FPGA logical block, I/O interface unit, WG26 interface/RS485 interface unit; Power supply unit is electrically connected to by the power lead formation of 3.3V with core cell, communication unit, CPLD/FPGA logical block respectively; Power supply unit forms and is electrically connected to by 5V and 12V power lead with I/O interface unit, WG26 interface/RS485 interface unit respectively; Core cell forms and is electrically connected to by serial bus with communication unit; Core cell forms and is electrically connected to by the parallel port bus with the CPLD/FPGA logical block; Core cell forms and is electrically connected to by serial bus with WG26 interface/RS485 interface unit; The CPLD/FPGA logical block forms and is electrically connected to by the IO signal wire with I/O interface unit and WG26 interface/RS485 interface unit respectively.
Described power supply unit turns 12V/3A technical grade power module by external AC 220V provides input power, after anti-reverse protection module, level switch module with between core cell, communication unit, CPLD/FPGA logical block, I/O interface unit, WG26 interface/RS485 interface unit, forms and is electrically connected to by 5V/12V or 3.3V power lead respectively.
Described core cell is comprised of level switch module, ARM main control module and peripheral circuit module; Level switch module turns the 1.8V level shifting circuit by 3.3V and forms, and with the ARM main control module, by the 1.8V power lead, forms and is electrically connected to; The ARM main control module is by the electric circuit constitutes such as arm processor, crystal oscillating circuit, SDRAM memory circuit, NANDFLASH memory circuits; The peripheral circuit module is by the electric circuit constitutes such as clock circuit, jtag interface circuit, reset circuits, and the peripheral circuit module forms and is electrically connected to by signal wire with the ARM main control module.Described ARM main control module main control chip adopts the ARM9 of atmel corp processor A T91SAM9260.
Described communication unit is comprised of RS232 AccessPort module and 10M/100M self-adaptation ethernet module; Described 10M/100M self-adaptation ethernet module adopts physical layer protocol transmitting-receiving control chip DM9161A.
Described CPLD/FPGA logical block is comprised of CPLD/FPAG application of logic circuit module and peripheral circuit module; The peripheral circuit module is by crystal oscillating circuit and jtag interface the electric circuit constitute, and peripheral circuit forms and is electrically connected to by signal wire with the CPLD/FPGA application of logic circuit module.Described CPLD/FPGA application of logic circuit module main control chip adopts the EMP1270 of ALTERA company or EP2C5 logic chip.
Described I/O interface unit is comprised of 6 road relay output modules, 11 road optocoupler load modules, 4 tunnel card reading status LED light signal output module; The outputting circuit for relay module turns 5V signal level shift circuit, relay drive circuit, relay and interface circuit by 3.3V and forms; The optocoupler load module is comprised of optocoupler and interface circuit; Card reading status LED light signal output module is comprised of inverter circuit.
Described WG26 interface/RS485 interface unit is by 8 Lu Weigen load modules, 8 road RS485 interface module and multi-channel gating switch modules; Wei root load module turns 3.3V signal level shift circuit and Wei root interface the electric circuit constitute by 5V, the RS485 interface module turns 3.3V signal level shift circuit and RS485 serial communication device SN65LBC184 and the electric circuit constitute thereof by 5V, the multi-channel gating switch circuit is comprised of multi-channel gating switch (SPDT) circuit and interface protection circuit thereof, for realizing software configuration, hardware gating WG26 interface or RS485 interface.
The advantage of a kind of four dual control access controllers of the utility model is: can meet, needs a large amount of arrange identification reader devices high for the security management and control class requirement, need a fairly large number of applied environment of managerial personnel.Take into account Wei root interface and RS485 interface duplex, but software configures, the hardware gating; The identity information recognition efficiency is high, and information retrieval and feedback efficiency are high, and information storage capacity is large, the characteristics such as reliability is high, comprehensive wiring is reasonable and cost is low.
The accompanying drawing explanation
Tetra-dual control access controller structured flowcharts of Fig. 1.
Tetra-dual control access controller theory diagrams of Fig. 2.
Fig. 3 Wei root interface and RS485 interface hardware principle of multiplexing block diagram.
Embodiment
Shown in Fig. 1, four dual control access controllers described in the utility model comprise: power supply unit 1, core cell 2, communication unit 3, CPLD/FPGA logical block 4, I/O interface unit 5, WG26 interface/RS485 interface unit 6; Power supply unit 1 is electrically connected to by the power lead formation of 3.3V with core cell 2, communication unit 3, CPLD/FPGA logical block 4 respectively; Power supply unit 1 forms and is electrically connected to by 5V and 12V power lead with I/O interface unit 5, WG26 interface/RS485 interface unit 6 respectively; Core cell 2 forms and is electrically connected to by serial bus with communication unit 3; Core cell 2 forms and is electrically connected to by the parallel port bus with CPLD/FPGA logical block 4; Core cell 2 forms and is electrically connected to by serial bus with WG26 interface/RS485 interface unit 6; CPLD/FPGA logical block 4 forms and is electrically connected to by the IO signal wire with I/O interface unit 5 and WG26 interface/RS485 interface unit 6 respectively.
Described power supply unit 1 as shown in Figure 2; turning 12V/3A technical grade power module by external AC 220V provides input power, after anti-reverse protection module A, level switch module B with between core cell, communication unit, CPLD/FPGA logical block, I/O interface unit, WG26 interface/RS485 interface unit, forms and is electrically connected to by 5V/12V or 3.3V power lead respectively.Described anti-reverse protection module adopts control rectifier IRF3205; form and be electrically connected to the positive level of 12V input power after current-limiting resistance of its grid series connection; source class forms and is electrically connected to the ground (GND) of circuit board; leak level and form and be electrically connected to the negative level of 12V input power, the positive level of 12V input power forms and is electrically connected to the positive level of the 12V of circuit board.Described level switch module comprises that respectively 12V turns the 5V level shifting circuit; 5V turns the 3.3V level shifting circuit and 12V turns 5V insulating power supply change-over circuit.Wherein 12V turns the 5V insulating power supply for the I/O interface unit.
Described core cell 2 as shown in Figure 2, is comprised of level switch module C, ARM main control module D and peripheral circuit module E; Level switch module turns the 1.8V level shifting circuit by 3.3V and forms, and with the ARM main control module, by the 1.8V power lead, forms and is electrically connected to; The ARM main control module is by the electric circuit constitutes such as arm processor, crystal oscillating circuit, SDRAM memory circuit, NANDFLASH memory circuits; Described arm processor adopts the ARM9 of atmel corp technical grade processor A T91SAM9260; The SDRAM storer adopts two 64M to add up to the SDRAM of 128M; The NANDFLASH storer adopts the NANDFLASH of 128M, and SDRAM and NANDFLASH form and are electrically connected to by address bus, data bus and control bus respectively with between arm processor.The peripheral circuit module is by the electric circuit constitutes such as clock circuit, jtag interface circuit, reset circuits, and the peripheral circuit module forms and is electrically connected to by signal wire with the ARM main control module.
Described communication unit 3 as shown in Figure 2, is comprised of RS232 AccessPort module F and 10M/100M self-adaptation ethernet module G; RS232 AccessPort module is printed for debugging and the Debugging message of access controller, 10M/100M self-adaptation ethernet module is for the data interaction with host computer (server), and described 10M/100M self-adaptation ethernet module adopts physical layer protocol transmitting-receiving control chip DM9161A.
Described CPLD/FPGA logical block 4 as shown in Figure 2, is comprised of CPLD/FPAG application of logic circuit module H and peripheral circuit module I; The CPLD/FPAG application of logic circuit module is for parsing and the logical process of Wiegand signal and IO signal, for the passage gating of the control of RS485 chip input and output direction and multi-channel gating switch, described CPLD/FPGA application of logic circuit module main control chip adopts the EMP1270 of ALTERA company or EP2C5 logic chip simultaneously; The peripheral circuit module is by crystal oscillating circuit and jtag interface the electric circuit constitute, and peripheral circuit forms and is electrically connected to by signal wire with the CPLD/FPGA application of logic circuit module.Access controller Wiegand signal treatment scheme as shown in Figure 3, the CPLD/FPGA logic circuit unit converts the serial Wiegand signal to parallel signal the zone bit set of enable pass track data status register and produces look-at-me after the processing such as interrupt acquisition, displacement, verification, overtime control, storage, is interrupted and read the data of the data register storage of interrupt flag bit respective channel by the arm processor response.
Described I/O interface unit 5 as shown in Figure 2, is comprised of 6 road relay output module J, 11 road optocoupler load module K, 4 tunnel card reading status LED light signal output module L; The outputting circuit for relay module turns 5V signal level shift circuit, relay drive circuit, relay and interface circuit by 3.3V and forms; The optocoupler load module is comprised of optocoupler and interface circuit; Card reading status LED light signal output module is comprised of inverter circuit.6 road relay output modules comprise that 4 road door lock outputs are controlled, reporting to the police in 2 tunnels, output is controlled; 11 road optocoupler load modules comprise 4 road door magnetic feed back inputs, 4 road door open button inputs, 2 tunnels warning inputs and 1 road dismantling-proof alarming input; 4 tunnel card reading status output modules collect the rear indicative function of competent person's identity information (ID) for the card reader articulated on WG26 interface/RS485 interface.
Described WG26 interface/RS485 interface unit 6 as shown in Figure 2, by 8 Lu Weigen load module M and 8 road RS485 interface module N, the compositions such as multi-channel gating switch module O; Wei root load module turns 3.3V signal level shift circuit and Wei root interface the electric circuit constitute by 5V.Described Wei root load module turns 3.3V signal level shift circuit and Wei root interface the electric circuit constitute by 5V, and the WG26 data-signal of 5V is changed into after 3.3V and forms and be electrically connected to the application of logic circuit module main control chip of CPLD/FPGA logical block (4); The RS485 interface module turns the 3.3V signal level shift circuit by 5V and the RS485 interface circuit forms, and wherein the RS485 interface circuit adopts technical grade SN65LBC184 serial port chip.Described 5V turns the 3.3V signal level shift circuit and adopts the MC74LVX3245 chip; Described multi-channel gating switch module is comprised of SPDT chip ADG333A and protection circuit thereof, and wherein protection circuit is on the gating interface and connects the 6.8V Transient Suppression Diode.
The gating principle of described multi-channel gating switch module O as shown in Figure 3, the IO of CPLD/FPGA logical block 4 meets the direction control end EN of multi-channel gating switch chip, control and make the access data interface select one between WG26 interface and RS485 interface by the low and high level of EN, configurable by software, the hardware gating.
Claims (4)
1. four dual control access controllers, comprise: power supply unit (1), core cell (2), communication unit (3), CPLD/FPGA logical block (4), I/O interface unit (5), WG26 interface/RS485 interface unit (6) is characterized in that: power supply unit (1) is electrically connected to by the power lead formation of 3.3V with core cell (2), communication unit (3), CPLD/FPGA logical block (4) respectively; Power supply unit (1) forms and is electrically connected to by 5V and 12V power lead with I/O interface unit (5), WG26 interface unit (6) respectively; Core cell (2) forms and is electrically connected to by serial bus with communication unit (3); Core cell (2) forms and is electrically connected to by the parallel port bus with CPLD/FPGA logical block (4); Core cell (2) forms and is electrically connected to by serial bus with WG26 interface/RS485 interface unit (6); CPLD/FPGA logical block (4) forms and is electrically connected to by the IO signal wire with I/O interface unit (5) and WG26 interface/RS485 interface unit (6) respectively.
2. a kind of four dual control access controllers according to claim 1, it is characterized in that: described power supply unit (1) turns 12V/5A technical grade power module by external AC 220V provides input power, after anti-reverse protection module A, level switch module B with between core cell (2), communication unit (3), CPLD/FPGA logical block (4), I/O interface unit (5), WG26 interface/RS485 interface unit (6), forms and is electrically connected to by 5V/12V or 3.3V power lead respectively; Described reverse connection prevention protection circuit grid adopt control rectifier IRF3205; form and be electrically connected to the positive level of 12V input power after current-limiting resistance of its grid series connection; source class forms and is electrically connected to the ground of circuit board; leak level and form and be electrically connected to the negative level of 12V input power, the positive level of 12V input power forms and is electrically connected to the positive level of the 12V of circuit board.
3. a kind of four dual control access controllers according to claim 1, it is characterized in that: described CPLD/FPGA logical block (4), CPLD/FPAG application of logic circuit module H and peripheral circuit module I, consist of, the CPLD/FPAG application of logic circuit module is for parsing and the logical process of Wiegand signal and IO signal.
4. a kind of four dual control access controllers according to claim 1, it is characterized in that: described core cell (2), formed the described ARM main control module D processor adopting ARM9 of atmel corp technical grade processor A T91SAM9260 by level switch module C, ARM main control module D and peripheral circuit module E.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320077990XU CN203338430U (en) | 2013-02-20 | 2013-02-20 | Four-door double-control access controller |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320077990XU CN203338430U (en) | 2013-02-20 | 2013-02-20 | Four-door double-control access controller |
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| CN203338430U true CN203338430U (en) | 2013-12-11 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104123772A (en) * | 2014-06-25 | 2014-10-29 | 北京燕山电子设备厂 | Access controller based on Loongson chip |
| CN106059285A (en) * | 2016-08-03 | 2016-10-26 | 宝晟科技（北京）有限公司 | Anti-interference circuit of power supply of ETC main control board |
| CN106355705A (en) * | 2016-08-31 | 2017-01-25 | 杭州易和网络有限公司 | IP door control system |
| CN106898066A (en) * | 2017-01-25 | 2017-06-27 | 浙江大学 | A kind of non-motor vehicle dynamic puzzle-lock based on clock |
| CN108241397A (en) * | 2016-12-27 | 2018-07-03 | 华大半导体有限公司 | Multiplex circuit compensator circuit of electric leakage and method |
| CN109215177A (en) * | 2017-07-03 | 2019-01-15 | 深圳市通达智科技有限公司 | access control system and access control method |
-
2013
- 2013-02-20 CN CN201320077990XU patent/CN203338430U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104123772A (en) * | 2014-06-25 | 2014-10-29 | 北京燕山电子设备厂 | Access controller based on Loongson chip |
| CN106059285A (en) * | 2016-08-03 | 2016-10-26 | 宝晟科技（北京）有限公司 | Anti-interference circuit of power supply of ETC main control board |
| CN106355705A (en) * | 2016-08-31 | 2017-01-25 | 杭州易和网络有限公司 | IP door control system |
| CN108241397A (en) * | 2016-12-27 | 2018-07-03 | 华大半导体有限公司 | Multiplex circuit compensator circuit of electric leakage and method |
| CN106898066A (en) * | 2017-01-25 | 2017-06-27 | 浙江大学 | A kind of non-motor vehicle dynamic puzzle-lock based on clock |
| CN109215177A (en) * | 2017-07-03 | 2019-01-15 | 深圳市通达智科技有限公司 | access control system and access control method |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131211 Termination date: 20170220 |