CN203325459U - Power management module capable of effectively avoiding electric leakage of LPDDR2 - Google Patents
Power management module capable of effectively avoiding electric leakage of LPDDR2 Download PDFInfo
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- CN203325459U CN203325459U CN2013204125454U CN201320412545U CN203325459U CN 203325459 U CN203325459 U CN 203325459U CN 2013204125454 U CN2013204125454 U CN 2013204125454U CN 201320412545 U CN201320412545 U CN 201320412545U CN 203325459 U CN203325459 U CN 203325459U
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- lpddr2
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Abstract
The utility model relates to a power management module capable of effectively avoiding electric leakage of an LPDDR2. The power management module comprises a power management chip, a DC/DC voltage reduction circuit, load switches and the LPDDR2. A power output port of the power management chip is connected with the power end of the LPDDR2 through the DC/DC voltage reduction circuit and one load switch in sequence. The output end of the DC/DC voltage reduction circuit comprises a VREG_S1 output end and a VREG_S2 output end. The VREG_S1 output end of the DC/DC voltage reduction circuit is connected with the VDD_1V2 power end of the LPDDR2 through one load switch. The VREG_S2 output end of the DC/DC voltage reduction circuit is connected with the VDD_1V8 power end of the LPDDR2 through one load switch. The power management module has the advantages that the DC/DC voltage reduction circuit is arranged at the output end of the power management chip, output voltage can be converted, controlled and adjusted effectively, stable voltage can be provided for a follow-up circuit, and the stability of operation of the circuit is improved; the load switches are arranged, and outage of the LPDDR2 can be effectively controlled, damage to electronic components by the electric leakage of the LPDDR2 is avoided, and the service life of the components is prolonged.
Description
Technical field
The utility model relates to a kind of electric power management circuit, particularly relates to the power management module that can effectively avoid the LPDDR2 electric leakage.
Background technology
Owing in nearly all application that requires the fast processing mass data, all having required the RAM(random access memory), thereby the DDR storer also becomes and becomes more and more important, its application is also more extensive.The DDR internal memory adopts TSOP chip package form usually, it is upper that this packing forms can well be operated in 200MHz, yet, when frequency is higher, its long pin will produce very high impedance and stray capacitance, and this can affect its stability and the difficulty of frequency upgrading.
The DDR2 internal memory adopts the FBGA packing forms, is different from the TSOP packing forms of widespread use, and the FBGA encapsulation provides better electric property and thermal diffusivity, for the development of the steady operation of DDR2 internal memory and following frequency provides good guarantee.The DDR2 internal memory adopts 1.8V voltage, with respect to the 2.5V of DDR standard, has reduced much, thereby obvious less power consumption and less thermal value are provided.DDR2 not only has the transmittability of DDR twice, and in the situation that adopt more lower calorific value, more low-power consumption, DDR2 can obtain frequency upgrading faster.
Along with the development of the up-to-date processor technology of Intel, Front Side Bus is more and more higher to the requirement of memory bandwidth, and the DDR2 internal memory that has higher more stable operation frequency will be trend of the times.Electric power management circuit is the basis of mobile phone normal operation.The VDD output terminal of existing power management chip directly connects the VDD power end of DDR2 usually, though can realize the power supply of DDR2, the outage of LPDDR2 can't effectively be controlled, the phenomenon that can't avoid the LPDDR2 electric leakage to cause electronic devices and components to damage.
The utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, provide a kind of simple in structure, circuit is stable can effectively avoid the power management module of LPDDR2 electric leakage, it can effectively be changed, the voltage of control and regulation output, for subsequent conditioning circuit provides stable voltage, can effectively control the outage of LPDDR2, avoid electronic devices and components to damage, improve the serviceable life of components and parts.
The purpose of this utility model is achieved through the following technical solutions: the power management module that can effectively avoid the LPDDR2 electric leakage, it comprises power management chip, DC/DC reduction voltage circuit, load switch and LPDDR2, and the output port of power source of power management chip is connected with the power end of LPDDR2 with load switch by the DC/DC reduction voltage circuit successively.
Further, the output terminal of described DC/DC reduction voltage circuit comprises VREG_S1 output terminal and VREG_S2 output terminal, the VREG_S1 output terminal of DC/DC reduction voltage circuit is connected with the VDD_1V2 power end of LPDDR2 by load switch, and the VREG_S2 output terminal of DC/DC reduction voltage circuit is connected with the VDD_1V8 power end of LPDDR2 by load switch.
The beneficial effects of the utility model are:
(1) output terminal at power management chip is provided with the DC/DC reduction voltage circuit, can effectively change, the voltage of control and regulation output, for subsequent conditioning circuit provides stable voltage, guarantees the working stability of circuit;
(2) be provided with load switch, can effectively control the break-make of LPDDR2 power supply, avoid LPDDR2 that larger leakage current is arranged before dormancy or initialization, thereby avoided the electronic devices and components that cause because of leakage current to damage, improve the serviceable life of components and parts.
The accompanying drawing explanation
Fig. 1 is electrical block diagram of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail, but protection domain of the present utility model is not limited to the following stated.
As shown in Figure 1, can effectively avoid the power management module of LPDDR2 electric leakage, it comprises power management chip (PM8029), DC/DC reduction voltage circuit, load switch (LOAD SWITCH) and LPDDR2, and the output port of power source of power management chip (PM8029) is connected with the power end of LPDDR2 with load switch (LOAD SWITCH) by the DC/DC reduction voltage circuit successively.
Further, the output terminal of described DC/DC reduction voltage circuit comprises VREG_S1 output terminal and VREG_S2 output terminal, the VREG_S1 output terminal of DC/DC reduction voltage circuit is connected with the VDD_1V2 power end of LPDDR2 by load switch, and the VREG_S2 output terminal of DC/DC reduction voltage circuit is connected with the VDD_1V8 power end of LPDDR2 by load switch.
Claims (2)
1. can effectively avoid the power management module of LPDDR2 electric leakage, it is characterized in that: it comprises power management chip, DC/DC reduction voltage circuit, load switch and LPDDR2, and the output port of power source of power management chip is connected with the power end of LPDDR2 with load switch by the DC/DC reduction voltage circuit successively.
2. the power management module that can effectively avoid LPDDR2 electric leakage according to claim 1, it is characterized in that: the output terminal of described DC/DC reduction voltage circuit comprises VREG_S1 output terminal and VREG_S2 output terminal, the VREG_S1 output terminal of DC/DC reduction voltage circuit is connected with the VDD_1V2 power end of LPDDR2 by load switch, and the VREG_S2 output terminal of DC/DC reduction voltage circuit is connected with the VDD_1V8 power end of LPDDR2 by load switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013204125454U CN203325459U (en) | 2013-07-12 | 2013-07-12 | Power management module capable of effectively avoiding electric leakage of LPDDR2 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013204125454U CN203325459U (en) | 2013-07-12 | 2013-07-12 | Power management module capable of effectively avoiding electric leakage of LPDDR2 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203325459U true CN203325459U (en) | 2013-12-04 |
Family
ID=49664775
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2013204125454U Expired - Fee Related CN203325459U (en) | 2013-07-12 | 2013-07-12 | Power management module capable of effectively avoiding electric leakage of LPDDR2 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203325459U (en) |
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2013
- 2013-07-12 CN CN2013204125454U patent/CN203325459U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131204 Termination date: 20150712 |
|
| EXPY | Termination of patent right or utility model |