CN203312289U - #-shaped artificial magnetic conductor for 60 GHz on-chip antenna - Google Patents
#-shaped artificial magnetic conductor for 60 GHz on-chip antenna Download PDFInfo
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- CN203312289U CN203312289U CN2013203988235U CN201320398823U CN203312289U CN 203312289 U CN203312289 U CN 203312289U CN 2013203988235 U CN2013203988235 U CN 2013203988235U CN 201320398823 U CN201320398823 U CN 201320398823U CN 203312289 U CN203312289 U CN 203312289U
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Abstract
A #-shaped artificial magnetic conductor for a 60 GHz on-chip antenna can be used for a millimeter wave integrated circuit, waveguide transmission, an on-chip antenna, and the like. The artificial magnetic conductor is produced with use of a CMOS integrated circuit technology, and comprises a silicon substrate, a silicon oxide buffer layer, a metal layer, a silicon oxide insulating layer, and a functional circuit layer which is arranged at the top; and the metal layer is made into a distributed #-shaped structure. The artificial magnetic conductor is applied to the millimeter wave integrated circuit design, and particularly to an integrated on-chip antenna, so that the antenna and the silicon substrate are isolated effectively and a wireless incident electromagnetic wave of the antenna is prevented from entering the silicon substrate. According to the utility model, the #-shaped artificial magnetic conductor for the antenna on the 60 GHz piece serves as the isolation layer between the millimeter wave on-chip radiating antenna and the silicon substrate; the simple structure is realized; the artificial magnetic conductor is compatible with the CMOS technology; and when the artificial magnetic conductor is applied to the 60 GHz integrated on-chip antenna, the wireless incident electromagnetic wave signal loss by the silicon substrate is reduced.
Description
Technical field
The utility model relates to millimetre integrated circuit and on-chip antenna technical field, particularly a kind of 60 GHz on-chip antenna artificial magnetic conductor structures.
Background technology
60 GHz frequency band short-distance wireless communications make wireless personal local area network network (WPANs) produce revolutionary breakthrough, at wireless consumption electronic product, the large capacity media file transmission of high-resolution, moving distributing calculates, and the fields such as wireless game and fast transport super large file have the great market prospect.The free space wavelength of 60 GHz frequencies only has 5 millimeters, therefore adopts the very antenna of small size just can realize the transmitting-receiving of wireless data.Therefore, integrated low-noise amplifier on monolithic integrated circuit chip, frequency mixer, frequency converter, wave detector, modulator, transceiver and antenna, realize the radio communication of 60 gigahertz band, can effectively reduce the volume of Wireless communication transceiver system, make its compact conformation, machining reproducibility is good, and reliability is high.
Current 60 GHzs and millimetre integrated circuit mainly adopt the GaAs manufacturing process, complex process not only, and cost is high, price, and also arsenic (As) is a kind of poisonous material, need to protect.Adopt the CMOS integrated circuit technology to realize 60 GHzs and millimetre integrated circuit, can greatly reduce costs, improve output.But CMOS technique is done substrate with silicon materials, silicon substrate is not the material insulated fully, has certain conductivity, can not reach desirable isolation effect while particularly being operated in high frequency, can produce leakage current, obviously reduces radiation efficiency and the gain of on-chip antenna.Therefore the electromagnetic wave loss that solves silicon substrate is the key issue of CMOS millimetre integrated circuit and on-chip antenna development.
Over nearly 10 years, industry is devoted to solve silicon substrate loss problem always, has proposed once proton injection method, methods of micro-mechanics, resin bed insulation method and artificial magnetic conductor method etc.
The artificial magnetic conductor structure adds a separator exactly between silicon substrate and functional circuit layer, reduce the loss of silicon substrate to frequency electromagnetic waves.Its buffer action is the reflected phase will band gap properties due to artificial magnetic conductor, when the incident wave frequency during near the resonance frequency of artificial magnetic conductor structure, the surface impedance of artificial magnetic conductor structure is very high, when therefore plane wave incided the artificial magnetic conductor surface, its reflected wave and incident wave phase difference were 0, when the wave frequency of incident makes the artificial magnetic conductor surface impedance equal free space impedance, the phase difference of incident wave and reflected wave is ± 90 °, design artificial magnetic conductor structure, make the phase difference of its incident wave and reflected wave just can realize the isolation to incident electromagnetic wave between ± 90 °.
Artificial magnetic conductor CMOS technique compatible, cost are low, simple in structure, are a kind of very promising technology.
Summary of the invention
The purpose of this utility model is for 60 GHz millimetre integrated circuits and on-chip antenna design, solve silicon substrate electromagnetic wave loss problem, a kind of groined type artificial magnetic conductor for 60 GHz on-chip antennas is provided, realize the insulation of on-chip circuit and silicon substrate, improve the job stability of on-chip circuit and efficiency and the gain of on-chip antenna.
The groined type artificial magnetic conductor for 60 GHz on-chip antennas that the utility model provides comprises:
Silicon substrate, silica resilient coating, metal level, insulating layer of silicon oxide and functional circuit layer, stack gradually making from top to bottom.Below silicon substrate is positioned at, above it, cover one deck silica resilient coating, on the silica resilient coating, have the metal level of distributed groined type array of structures for one deck, on metal level, cover one deck insulating layer of silicon oxide, the top of insulating layer of silicon oxide is the functional circuit layer.
Described artificial magnetic conductor adopts traditional CMOS technique to realize.
Described metal level is made by the first metal layer of CMOS technique.
Described metal level is divided into N * N unit, the span of N is 6 to 11, each unit is to take 200 microns squares as the length of side, foursquare middle part has a groined type fluting, each groined type fluting is intersected to form mutually by four strip line of rabbet joint, 80 microns of each strip slot line lengths, wide 5 microns, the distance between every two parallel line of rabbet joint is 30 microns.
Described Si-Substrate Thickness during to 320 micrometer range, meets described artificial magnetic conductor centre frequency 60 GHzs, the parameter request of bandwidth 20 GHzs at 280 microns.
Its thickness of described insulating layer of silicon oxide is 1.3 microns.
The utility model is based on the CMOS integrated circuit technology, in special-purpose EDA design software, determine size and the position of silica resilient coating 4, lamellule 7, via hole 6, insulating layer of silicon oxide 2 and cyclic array structure 9, adopt full method for customizing design, based semiconductor technique realizes.
Advantage of the present utility model and good effect:
The 60 GHz on-chip antenna intersecting parallels artificial magnetic conductors that the utility model provides, have the reflected phase will band gap properties, the central task frequency is 60 GHzs, and bandwidth has reached 20.2 GHzs, relative bandwidth is large, and antenna integrated application has obvious competitive advantage on 60 GHz sheets.The artificial magnetic conductor that the utility model provides is simple in structure, and area is little, and each cellar area is only for take 200 microns little squares as the length of side, fully compatible existing CMOS technique.
The accompanying drawing explanation
Fig. 1 is a kind of structure chart of groined type artificial magnetic conductor for 60 GHz on-chip antennas;
Fig. 2 is artificial magnetic conductor metal level lamellule 7 cellular construction figure;
Fig. 3 is the N * N intersecting parallels artificial magnetic conductor array 9 structure charts of periodic arrangement.
Fig. 4 has prepared the artificial magnetic conductor structure chart of on-chip antenna at the functional circuit layer.
Embodiment
Embodiment 1:
As shown in Figure 1, the groined type artificial magnetic conductor for 60 GHz on-chip antennas that the utility model provides, concrete structure comprises:
Silicon substrate, silica resilient coating, metal level, insulating layer of silicon oxide and functional circuit layer, stack gradually making from top to bottom.Below silicon substrate is positioned at, above it, cover one deck silica resilient coating, on the silica resilient coating, have the metal level of distributed groined type array of structures for one deck, on metal level, cover one deck insulating layer of silicon oxide, the top of insulating layer of silicon oxide is the functional circuit layer.
Si-Substrate Thickness during to 320 micrometer range, meets described artificial magnetic conductor centre frequency 60 GHzs, the parameter request of bandwidth 20 GHzs at 280 microns.
The intersecting parallels artificial magnetic conductor adopts traditional CMOS technique to realize.
Intersecting parallels artificial magnetic conductor metal level is made by the first metal layer of CMOS technique, and this metal level is made into distributed groined type structure.
Whole metal level is divided into N * N unit, each unit is to take 200 microns squares as the length of side, foursquare middle part has a groined type fluting, each groined type fluting is intersected to form mutually by four strip line of rabbet joint, 80 microns of each strip slot line lengths, wide 5 microns, the distance between every two parallel line of rabbet joint is 30 microns.
Its thickness of insulating layer of silicon oxide is 1.3 microns.
Embodiment 2:
As shown in Figures 2 and 3, N * N periodic structure arrange for 60 GHz on-chip antenna intersecting parallels artificial magnetic conductors, concrete structure is as follows:
Get N=7, realize that 7 * 7 periodic structures arrange for 60 GHz on-chip antenna intersecting parallels artificial magnetic conductors.
Employing has the silicon substrate 5 of the silicon chip of epitaxial loayer as the intersecting parallels artificial magnetic conductor, and the thickness of silicon substrate 5 is 300 microns.
Above silicon substrate 5, with the field oxidation technology growing silicon oxide resilient coating 4 of CMOS, determine that by the method for photoetching the size of silica resilient coating 4 is for take 1.84 millimeters squares as the length of side, as the lower dielectric layer of intersecting parallels artificial magnetic conductor.
Silicon chip is carried out to annealing in process, on silica resilient coating 4, carry out the chemical vapour deposition (CVD) oxidation, then utilize the first metal layer evaporated metal layer 3 of CMOS technique, utilize the method for photoetching to form 7 * 7 and take 200 microns square lamellules 7 as the length of side, gap between each lamellule is 55 microns, 7 * 7 lamellules 7 are pressed the ranks periodic and are arranged, and as Fig. 3, form the square formation of 7 * 7 lamellules.
Described lamellule 7, the above etches intersecting parallels fluting 8, each intersecting parallels fluting is intersected to form mutually by four strip line of rabbet joint, 80 microns of each strip slot line lengths, wide 5 microns, centre distance between every two parallel line of rabbet joint is 30 microns, and the lamellule 7 of each fluting is connected with silicon substrate 5 and ground connection by via hole 6.
On metal level 3, carry out the chemical vapour deposition (CVD) oxidation, form insulating layer of silicon oxide 2, insulating layer of silicon oxide 2 is as the upper dielectric layer of artificial magnetic conductor, and thickness is 1.3 microns.
The central task frequency of 7 * 7 matrix structure intersecting parallels artificial magnetic conductors of realizing is 60 GHzs, bandwidth 20.5 GHzs, relative bandwidth 34%.
Embodiment 3:
Described a kind of 60 GHz on-chip antennas are as follows with the application example of intersecting parallels artificial magnetic conductor:
As shown in Figure 4, a kind of 60 GHz on-chip antennas of 6 * 6 periodic structures arrangements are implemented as follows with intersecting parallels artificial magnetic conductor array:
Employing has the silicon substrate 5 of the silicon chip of epitaxial loayer as the intersecting parallels artificial magnetic conductor, and the thickness of silicon substrate 5 is 300 microns.Above silicon substrate 5, with the field oxidation technology growing silicon oxide resilient coating 4 of CMOS, determine that by the method for photoetching the size of silica resilient coating 4 is for take 1.585 millimeters squares as the length of side, as the lower dielectric layer of intersecting parallels artificial magnetic conductor.
Silicon chip is carried out to annealing in process, on silica resilient coating 4, carry out the chemical vapour deposition (CVD) oxidation, then utilize the first metal layer evaporated metal layer 3 of CMOS technique, utilize the method for photoetching to form 6 * 6 and take 200 microns square lamellules 7 as the length of side, gap between each lamellule is 55 microns, 6 * 6 lamellules 7 are pressed the ranks periodic and are arranged, and as Fig. 4, form the square formation of 6 * 6 lamellules 7.
Described lamellule 7, the above etches intersecting parallels fluting 8, each intersecting parallels fluting is intersected to form mutually by four strip line of rabbet joint, 80 microns of each strip slot line lengths, wide 5 microns, centre distance between every two parallel line of rabbet joint is 30 microns, and the lamellule 7 of each fluting is connected with silicon substrate 5 and ground connection by via hole 6.
On metal level 3, carry out the chemical vapour deposition (CVD) oxidation, form insulating layer of silicon oxide 2, insulating layer of silicon oxide 2 is as the upper dielectric layer of artificial magnetic conductor, and thickness is 1.3 microns, forms the artificial magnetic conductor 10 of 6 * 6 matrix structures.
Utilize the top layer metallic layer evaporation metal of CMOS technique, utilize the method for photoetching to form monopole antenna 11, then prepare antenna welding node 13, and ground nodes 12, ground nodes 14.
Claims (4)
1. groined type artificial magnetic conductor for 60 GHz on-chip antennas is characterized in that this artificial magnetic conductor comprises:
Silicon substrate, silica resilient coating, metal level, insulating layer of silicon oxide and functional circuit layer, stack gradually and make from top to bottom; Below silicon substrate is positioned at, above it, cover one deck silica resilient coating, on the silica resilient coating, have the metal level of distributed groined type array of structures for one deck, on metal level, cover one deck insulating layer of silicon oxide, the top of insulating layer of silicon oxide is the functional circuit layer.
2. artificial magnetic conductor according to claim 1, it is characterized in that, described metal level is divided into N * N unit, between each unit, interval is 55 microns, and each unit is to take 200 microns squares as the length of side, and foursquare middle part has a groined type fluting, each groined type fluting is intersected to form mutually by four strip line of rabbet joint, 80 microns of each strip slot line lengths, wide 5 microns, the distance between every two parallel line of rabbet joint is 30 microns.
3. artificial magnetic conductor according to claim 1 and 2, is characterized in that, described Si-Substrate Thickness during to 320 micrometer range, meets described artificial magnetic conductor centre frequency 60 GHzs, the parameter request of bandwidth 20 GHzs at 280 microns.
4. artificial magnetic conductor according to claim 1 and 2, is characterized in that, described silicon oxide insulation layer thickness is 1.3 microns.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2013203988235U CN203312289U (en) | 2013-07-05 | 2013-07-05 | #-shaped artificial magnetic conductor for 60 GHz on-chip antenna |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2013203988235U CN203312289U (en) | 2013-07-05 | 2013-07-05 | #-shaped artificial magnetic conductor for 60 GHz on-chip antenna |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112909531A (en) * | 2021-02-24 | 2021-06-04 | 电子科技大学 | L-shaped wide-bandwidth wave beam circularly polarized on-chip antenna applied to millimeter wave frequency band |
| CN113612021A (en) * | 2021-08-05 | 2021-11-05 | 东南大学 | Miniaturized 45-degree dual-polarized crossed dipole antenna |
-
2013
- 2013-07-05 CN CN2013203988235U patent/CN203312289U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112909531A (en) * | 2021-02-24 | 2021-06-04 | 电子科技大学 | L-shaped wide-bandwidth wave beam circularly polarized on-chip antenna applied to millimeter wave frequency band |
| CN113612021A (en) * | 2021-08-05 | 2021-11-05 | 东南大学 | Miniaturized 45-degree dual-polarized crossed dipole antenna |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131127 Termination date: 20160705 |
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| CF01 | Termination of patent right due to non-payment of annual fee |