CN203301371U - Power supply management circuit and set top box - Google Patents
Power supply management circuit and set top box Download PDFInfo
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- CN203301371U CN203301371U CN2013203794579U CN201320379457U CN203301371U CN 203301371 U CN203301371 U CN 203301371U CN 2013203794579 U CN2013203794579 U CN 2013203794579U CN 201320379457 U CN201320379457 U CN 201320379457U CN 203301371 U CN203301371 U CN 203301371U
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Abstract
The utility model discloses a power supply management circuit and a set top box. Multistage direct current converting chips are disposed, and an input terminal of a first stage direct current converting chip is connected with an input power supply, to convert the input power supply into work voltage output when a first power on sequence is requested; the work voltage output of the first power on sequence is transmitted to an enabled terminal of a second direct current converting chip, an input terminal of the second direct current converting chip is connected with the input power supply, to convert the input power supply into work voltage output when a second power on sequence is requested after a work voltage of the first power on sequence is established. According to the power supply management circuit and the set top box, the power supply management circuit is established by adopting low cost and commonly used direct current converting chips and cooperating with simple discrete components, an input power supply of a system is converted to work voltages of multipath different power on sequences and transmitted to processing chips of the system, so as to raise the universality of circuit design and reduce product cost, meanwhile, requirements of the processing chips for processing multipath work power supplies and different power on sequences of the multipath work power supplies are satisfied.
Description
Technical field
The utility model belongs to the power circuit technical field, specifically, relates to a kind of for the electric power management circuit of the orderly control of the realization of the electrifying timing sequence to different electrical power and the set-top box product that adopts described electric power management circuit design.
Background technology
Along with the fast development of digital television techniques, present top box of digital machine product, except possessing traditional radio TV signals receiving and processing capacity, also has been endowed the additional functions such as online, digital program request, urban information.Be accompanied by the increasing of top box of digital machine product additional function and reinforcement day by day that system operation reliability requires, process chip that need to the configuration process ability is more powerful on the signal plate of set-top box meets the software and hardware demand for control of whole system.This just require the production firm of process chip must be in process chip integrated more functional module, more interface resource is provided, reach thus when supporting every additional function, by peripheral circuits design, improve the purpose of system reliability.
Due to integrated many functional modules in process chip, different functional modules may need different operating voltages, and different functional modules often also has different requirements for the electrifying timing sequence of operating voltage, therefore, not only need the electric power system on power panel that the power supply of multiple amplitude is provided to process chip, and for the electrifying timing sequence of each road power supply, also must meet the requirement that powers on of each functional module in process chip.For present top box of digital machine product, the required supply power voltage of its inner process chip generally has 5V, 3.3V, 2.5V, 1.1V, 1.5V or 1.8V etc. multiple, and be accompanied by the more and more higher of process chip dominant frequency, single clock cycle is shorter and shorter, and this will certainly propose higher requirement to the power supply sequential.
Aspect the power supply timing management, traditional method for designing is to adopt special power management chip at present, sequential requirement according to different operating voltage, by the configuration power management chip software or design different peripheral feedback circuits, realize the orderly control of Dui Ge road operating voltage electrifying timing sequence.But this design, because needs use special power management chip, causes product cost to raise, and because the chip that different manufacturers is produced can not be general, therefore when the batch production supply of material, can there be a lot of problems, had a strong impact on the delivery cycle of product, and debugging difficulty be larger.
Summary of the invention
The utility model adopts the electrifying timing sequence of special power management chip Dui Ge road power supply to control the problem that the cost that brings is high, debugging difficulty is large in order to solve the existing power supply management circuit, a kind of electric power management circuit that adopts the direct current conversion chip to coordinate discrete component to build has been proposed, when the electrifying timing sequence of Zai Duige road power supply is realized accurately controlling, reduce circuit cost, simplified debugging difficulty.
For solving the problems of the technologies described above, the utility model is achieved by the following technical solutions:
A kind of electric power management circuit, be provided with multistage direct current conversion chip; The input of first order direct current conversion chip connects input power, input power is converted to the operating voltage that requires the first electrifying timing sequence, by the output output of first order direct current conversion chip; The operating voltage of the first electrifying timing sequence is transferred to the Enable Pin of second level direct current conversion chip, the input of second level direct current conversion chip connects described input power, after the operating voltage of the first electrifying timing sequence is set up, described input power is converted to the operating voltage that requires the second electrifying timing sequence, by the output output of second level direct current conversion chip.
Further, the Enable Pin of described second level direct current conversion chip connects input power by the first resistance, and by the second resistance, receives the operating voltage of described the first electrifying timing sequence.
For the operating voltage to the second electrifying timing sequence, realize the accurate control of electrifying timing sequence, the Enable Pin of described second level direct current conversion chip, by charging capacitor ground connection, is discharged and recharged to the electrifying timing sequence of time adjustment operating voltage by adjusting.
Operating voltage for the second electrifying timing sequence of generating the different amplitudes of multichannel, in described multistage direct current conversion chip, also be provided with an other second level direct current conversion chip, the input of a described other second level direct current conversion chip receives the operating voltage of the first electrifying timing sequence, and conversion generates the operating voltage output that requires the second electrifying timing sequence of different amplitudes.
Further, the operating voltage of described the first electrifying timing sequence is the operating voltage of 3.3V, by diode, exports the operating voltage of the 2.5V that requires the second electrifying timing sequence.
Further again, the operating voltage of described 3.3V connects the anode of another diode by the switch ways of a switching circuit, by the negative electrode output of described another diode, require the operating voltage of the 2.5V of the 3rd electrifying timing sequence, the control end of described switching circuit receives the operating voltage of the second electrifying timing sequence.Utilize the operating voltage of the second electrifying timing sequence to control the foundation of the operating voltage of the 3rd electrifying timing sequence.
Preferably, in described switching circuit, be provided with a NPN type triode and a positive-negative-positive triode, the base stage of described NPN type triode receives the operating voltage of the second electrifying timing sequence, grounded emitter, collector electrode connects the base stage of positive-negative-positive triode, and by current-limiting resistance, connects the operating voltage of described 3.3V; The emitter of described positive-negative-positive triode connects the operating voltage of described 3.3V, and collector electrode connects the anode of described another diode.
For the operating voltage to the 3rd electrifying timing sequence, realize the accurate control of settling time, preferably by the base stage of described NPN type triode by capacity earth, the time that discharges and recharges by regulating described electric capacity can be adjusted the settling time of the operating voltage of the 3rd electrifying timing sequence.
Preferably, described first order direct current conversion chip comprises two, respectively the operating voltage of conversion output 5V and the operating voltage of 3.3V.
Based on above-mentioned electric power management circuit, the utility model has also proposed a kind of set-top box that adopts described electric power management circuit design, comprises process chip and electric power management circuit, in described electric power management circuit, is provided with multistage direct current conversion chip; The input of first order direct current conversion chip connects input power, input power is converted to the operating voltage that requires the first electrifying timing sequence, by the output output of first order direct current conversion chip; The operating voltage of the first electrifying timing sequence is transferred to the Enable Pin of second level direct current conversion chip, the input of second level direct current conversion chip connects described input power, after the operating voltage of the first electrifying timing sequence is set up, described input power is converted to the operating voltage that requires the second electrifying timing sequence, by the output output of second level direct current conversion chip; The operating voltage of the different sequential by the output of described electric power management circuit transfers to respectively the different power pin of process chip, to meet the power reguirements of process chip.
compared with prior art, advantage of the present utility model and good effect are: the utility model adopts low-cost general direct current conversion chip to coordinate simple discrete component to set up electric power management circuit, the operating voltage that converts the input power of system to multichannel different electrifying timing sequences transfers to the process chip of system, and then meet process chip to multiplex operation power supply and the different electrifying timing sequence requirements of each road working power in, improved the versatility of circuit design, shortened the time of delivery of product, avoided adopting the product cost that special power management chip design system circuit causes to raise, the problems such as circuit design is not general.It is applied in the design of the electronic products such as set-top box, helps the global advantage of improving product.
The accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the utility model embodiment, below will the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described.Apparently, the accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 generates the circuit theory diagrams of 5V operating voltage in the electric power management circuit that proposes of the utility model;
Fig. 2 is the circuit theory diagrams that generate the 3.3V operating voltage;
Fig. 3 is the circuit theory diagrams that generate the 1.1V operating voltage;
Fig. 4 is the circuit theory diagrams that generate the 1.5V operating voltage;
Fig. 5 is the circuit theory diagrams that generate the 2.5V operating voltage of the second electrifying timing sequence;
Fig. 6 is the circuit theory diagrams that generate the 2.5V operating voltage of the 3rd electrifying timing sequence.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described.Obviously, described embodiment is only a part of embodiment in the utility model, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making all other embodiment that obtain under the creative work prerequisite, all belong to the scope of the utility model protection.
For the advantage that makes technical solutions of the utility model is clearer, below in conjunction with drawings and Examples, the utility model is explained.
The present embodiment is in order to obtain the operating voltage of different sequential, at first adopt direct current conversion chip (DC-DC chip) directly to carry out conversion process to the input power of system, generate and require electrifying timing sequence operating voltage (hereinafter referred to as the operating voltage of the first electrifying timing sequence) the earliest; Then, utilize the operating voltage conversion of the first electrifying timing sequence to generate or control operating voltage (hereinafter referred to as the operating voltage of the second electrifying timing sequence) output that requires electrifying timing sequence slightly late.Due to electrifying timing sequence after the generation of operating voltage depend on the electrifying timing sequence foundation of operating voltage the preceding, therefore can conscientiously guarantee the accuracy of different operating voltage electrifying timing sequence.
For multichannel DC-DC chip is distinguished, below will be referred to as first order DC-DC chip be used to the DC-DC chip of changing the operating voltage that generates the first electrifying timing sequence, will be referred to as second level DC-DC chip be used to the DC-DC chip of changing the operating voltage that generates the second electrifying timing sequence.Utilize first order DC-DC chip to change the input power of system, to generate the operating voltage of the first required electrifying timing sequence of process chip; Then, the operating voltage of the first electrifying timing sequence is transferred to Enable Pin or the input of second level DC-DC chip, by controlling second level DC-DC chip, after the operating voltage of the first electrifying timing sequence is set up, enable or have input power to access, thereby the electrifying timing sequence that can guarantee the operating voltage of exporting by the conversion of second level DC-DC chip is later than the operating voltage of the first electrifying timing sequence, just can generate thus the operating voltage of the second required electrifying timing sequence of process chip, meet the power demands of process chip to the operating voltage of two kinds of different electrifying timing sequences.
Certainly, also can carry out multi-tier to this circuit design scheme, namely, use multistage DC-DC chip, one-level DC-DC chip enable or as the input power of rear one-level DC-DC chip after utilizing the operating voltage of previous stage DC-DC chip output to control, just can realize the generation successively of the operating voltage of various different electrifying timing sequences thus.
Below take the set-top box product as example, the generative process of the required De Ge of the process chip on its signal plate road operating voltage is at length set forth.
Take the required multiplex operation voltage of process chip, being respectively 5V, 3.3V, 2.5V, 1.1V, 1.5V describes as example.Wherein, process chip requires 3.3V and 5V operating voltage first to power on; 2.5V, 2.5_2,1.1V and 1.5V operating voltage power on after 3.3V; 2.5V_3 power on after 1.1V.
In order to meet the electrifying timing sequence requirement of process chip Dui Ge road operating voltage, on the power panel of set-top box, be provided with two first order DC-DC chip N15, N14, referring to Fig. 1, shown in Figure 2, be respectively used to conversion and generate 5V and 3.3V operating voltage.Input power (describing as an example of+12V example) is transferred to the input IN of first order DC-DC chip N15 by the filter circuit that consists of inductance FB35 and capacitor C 141, C142, by adjusting, be connected to divider resistance R125, the R126 of the feedback end FB of first order DC-DC chip N15, the resistance of R127, realize the adjusting to first order DC-DC chip N15 output voltage.The present embodiment is regulated the operating voltage of first order DC-DC chip N15 conversion generation+5V, by its output SW output, as shown in Figure 1.In like manner, + 12V input power is transferred to the input IN of first order DC-DC chip N14 by the filter circuit that consists of inductance FB30 and capacitor C 133, C134, by adjusting, be connected to divider resistance R115, the R116 of the feedback end FB of first order DC-DC chip N14, the resistance of R118, make by the operating voltage 3V3_CON of first order DC-DC chip N14 conversion generation+3.3V, by its output SW output, as shown in Figure 2.
For the required 1.1V operating voltage of process chip, because its electrifying timing sequence requires to be later than+the operating voltage 3V3_CON of 3.3V, therefore, the present embodiment is taked to utilize the operating voltage 3V3_CON of first order DC-DC chip N14 output+3.3V to control the method that second level DC-DC chip N13 enables and generated, and is shown in Figure 3.By first order DC-DC chip N14 conversion output+the operating voltage 3V3_CON of 3.3V transfers to the Enable Pin EN of second level DC-DC chip N13 by the second resistance R 140, described Enable Pin EN high level is effective, and described Enable Pin EN is passed through to the first resistance R 103 connection+12V input powers.described+12V input power is passed through simultaneously by inductance FB27 and capacitor C 125, the filter circuit that C126 forms transfers to the input IN of second level DC-DC chip N13, before the operating voltage 3V3_CON of+3.3V does not set up, voltage U=12V*R140/ (R103+R140) due to chip N13 Enable Pin EN, as long as adjusting resistance R103, the resistance of R140, make voltage U before the operating voltage 3V3_CON of+3.3V does not set up, effective voltage amplitude less than Enable Pin EN, and after the operating voltage 3V3_CON of+3.3V sets up just greater than the effective voltage amplitude of Enable Pin EN, can guarantee that second level DC-DC chip N13 is not in off position before the operating voltage 3V3_CON of+3.3V sets up, and then the electrifying timing sequence of guaranteeing the 1.1V operating voltage is later than+the operating voltage 3V3_CON of 3.3V.
In like manner, adjustment is connected to divider resistance R107, the R109 of the feedback end FB of second level DC-DC chip N13, the resistance of R110, utilize the input power of second level DC-DC chip N13 general+12V to convert the operating voltage 1V1_CORE of 1.1V to, by its output SW, export.
The Enable Pin EN that certainly, also can design second level DC-DC chip N13 only receive from first order DC-DC chip N14 conversion output+the operating voltage 3V3_CON of 3.3V.Before the operating voltage 3V3_CON of+3.3V did not generate, second level DC-DC chip N13, because its Enable Pin EN current potential is low, was in disarmed state, thereby second level DC-DC chip N13 do not work, and can not export the operating voltage 1V1_CORE of 1.1V; And after the operating voltage 3V3_CON of+3.3V generated, second level DC-DC chip N13 was the high operation that starts due to the current potential of its Enable Pin EN, changed the operating voltage 1V1_CORE that exports 1.1V.
In addition, the present embodiment can also further pass through charging capacitor C124 ground connection by the Enable Pin EN of second level DC-DC chip N13, and is shown in Figure 3.By the parameter value of adjusting capacitor C 124, adjust the time that discharges and recharges of capacitor C 124, and then realize the fine setting to the electrifying timing sequence of operating voltage 1V1_CORE.
For the required 1.5V operating voltage of process chip, because its electrifying timing sequence requires to be later than+the operating voltage 3V3_CON of 3.3V, therefore, the present embodiment adopt using first order DC-DC chip N14 output+the operating voltage 3V3_CON of 3.3V changes generation as the mode of the input power of second level DC-DC chip UU6, and is shown in Figure 4.By first order DC-DC chip N14 conversion output+the operating voltage 3V3_CON of 3.3V transfers to input IN and the Enable Pin EN of second level DC-DC chip UU6 by the filter circuit that consists of inductance FB36 and capacitor C 245, described Enable Pin EN high level is effective, make second level DC-DC chip UU6 after the operating voltage 3V3_CON of+3.3V sets up, enable immediately operation, the operating voltage 3V3_CON of+3.3V is converted to+the operating voltage 1V5 of 1.5V, by its output LX, export.
For process chip required two-way 2.5V operating voltage 2V5,2V5_2, can adopt the operating voltage 3V3_CON of+3.3V is generated by two diode DO2, DO4 decompression transformation respectively, shown in Figure 5.Because the PN junction pressure drop of diode DO2, DO4 is 0.7V, therefore, utilize the PN junction 0.7V drooping characteristic of diode DO2, DO4, can generate electrifying timing sequence to be later than+2.5V operating voltage 2V5, the 2V5_2 of 3.3V operating voltage 3V3_CON.
The electrifying timing sequence required for process chip be later than+the operating voltage 2V5_3 of the 3rd electrifying timing sequence of 1.1V operating voltage 1V1_CORE, and the present embodiment adopts switching circuit to coordinate the mode of diode DO3 step-down to change generation, and is shown in Figure 6.By first order DC-DC chip N14 output+the operating voltage 3V3_CON of 3.3V transfers to the switch ways of a switching circuit, the control end that described switching circuit is set receives the 1.1V operating voltage 1V1_CORE of second level DC-DC chip N13 output.After the operating voltage 1V1_CORE of 1.1V generates, utilize described its switch ways of 1.1V operating voltage 1V1_CORE control switch circuit turn-on, make+the operating voltage 3V3_CON of 3.3V transfers to the anode of diode DO3, utilize the characteristic of the PN junction pressure drop of diode DO3 for 0.7V, the operating voltage 3V3_CON of+3.3V is converted to the operating voltage 2V5_3 output of 2.5V.Because the generation of operating voltage 2V5_3 is controlled by+foundation of 1.1V operating voltage 1V1_CORE, therefore, can guarantee that the electrifying timing sequence of operating voltage 2V5_3 is later than+the operating voltage 1V1_CORE of 1.1V.
As a kind of preferred design of the present embodiment, described switching circuit preferably adopts a NPN type triode QU1 and a positive-negative-positive triode Q2 to coordinate simple peripheral circuit to set up and realizes, and is shown in Figure 6.The 1.1V operating voltage 1V1_CORE of second level DC-DC chip N13 conversion output is transferred to the base stage of NPN type triode QU1 by resistance R 122, the grounded emitter of described NPN type triode QU1, collector electrode connects the base stage of positive-negative-positive triode Q2 on the one hand by resistance R 120, on the other hand by the operating voltage 3V3_CON of current-limiting resistance R117 connection+3.3V.The operating voltage 3V3_CON of the emitter connection+3.3V of described positive-negative-positive triode Q2, collector electrode connects the anode of diode DO3, by the 2.5V operating voltage 2V5_3 of the 3rd required electrifying timing sequence of the negative electrode output process chip of diode DO3.
Its operation principle is: before the operating voltage 1V1_CORE of 1.1V does not set up, NPN type triode QU1 is because its base voltage is the low cut-off state that is in, at this moment, the base voltage of positive-negative-positive triode Q2 equals its emitter voltage, therefore positive-negative-positive triode Q2 is in cut-off state equally, can't generate by diode DO3 conversion the operating voltage 2V5_3 of the 3rd electrifying timing sequence.
After the operating voltage 1V1_CORE of 1.1V sets up, NPN type triode QU1 is because its base voltage is the high saturation conduction state that enters, at this moment, the emitter voltage of positive-negative-positive triode Q2 is higher than its base voltage, and then makes positive-negative-positive triode Q2 change the saturation conduction state over to.Due to the emitter and collector connection of positive-negative-positive triode Q2, the operating voltage 3V3_CON of+3.3V transfers to diode DO3 by positive-negative-positive triode Q2, and then, under the hypotensive effect of diode DO3, converts the operating voltage 2V5_3 output of 2.5V to.Due to the electrifying timing sequence of operating voltage 2V5_3, be later than the operating voltage 1V1_CORE of 1.1V, therefore, form the operating voltage of the 3rd electrifying timing sequence.
For the electrifying timing sequence to operating voltage 2V5_3 is realized fine setting, the present embodiment also connects capacitor C 143 on the base stage of NPN type triode QU1, shown in Figure 6.By the minus earth of described capacitor C 143, by adjusting the parameter value of capacitor C 143, with the time that discharges and recharges of control capacittance C143, realize the accurate control to operating voltage 2V5_3 electrifying timing sequence.
Certainly, described switching circuit also can adopt other components and parts with on-off action to set up and realize, the present embodiment is not limited in above giving an example.
To transfer to the process chip on signal plate in set-top box by the electric power management circuit conversion output De Ge road operating voltage of the present embodiment, namely from the corresponding connection of the different power pin of process chip, thereby met the electrifying timing sequence requirement of process chip Dui Ge road operating voltage, guaranteed machine system stable operation.
The utility model takes full advantage of the ena-bung function of DC-DC chip and the PN junction dropping voltage characteristic of diode, complete the establishment design of electric power management circuit, not only the electrifying timing sequence of Dui Ge road operating voltage has been realized accurate control, and circuit cost is low, highly versatile, be adapted at applying on the electronic products such as set-top box, digital television.
Certainly; above-mentioned explanation is not to restriction of the present utility model; the utility model also is not limited in above-mentioned giving an example, and those skilled in the art make in essential scope of the present utility model variation, remodeling, interpolation or replacement, also should belong to protection range of the present utility model.
Claims (10)
1. an electric power management circuit, is characterized in that: be provided with multistage direct current conversion chip; The input of first order direct current conversion chip connects input power, input power is converted to the operating voltage that requires the first electrifying timing sequence, by the output output of first order direct current conversion chip; The operating voltage of the first electrifying timing sequence is transferred to the Enable Pin of second level direct current conversion chip, the input of second level direct current conversion chip connects described input power, after the operating voltage of the first electrifying timing sequence is set up, described input power is converted to the operating voltage that requires the second electrifying timing sequence, by the output output of second level direct current conversion chip.
2. electric power management circuit according to claim 1 is characterized in that: the Enable Pin of described second level direct current conversion chip connects input power by the first resistance, and by the second resistance, receives the operating voltage of described the first electrifying timing sequence.
3. electric power management circuit according to claim 2 is characterized in that: the Enable Pin of described second level direct current conversion chip is by charging capacitor ground connection.
4. electric power management circuit according to claim 1, it is characterized in that: in described multistage direct current conversion chip, also be provided with an other second level direct current conversion chip, the input of a described other second level direct current conversion chip receives the operating voltage of the first electrifying timing sequence, and conversion generates the operating voltage output that requires the second electrifying timing sequence of different amplitudes.
5. the described electric power management circuit of any one according to claim 1 to 4, it is characterized in that: the operating voltage of described the first electrifying timing sequence is the operating voltage of 3.3V, by diode, exports the operating voltage of the 2.5V that requires the second electrifying timing sequence.
6. electric power management circuit according to claim 5, it is characterized in that: the operating voltage of described 3.3V connects the anode of another diode by the switch ways of a switching circuit, by the negative electrode output of described another diode, require the operating voltage of the 2.5V of the 3rd electrifying timing sequence, the control end of described switching circuit receives the operating voltage of the second electrifying timing sequence.
7. electric power management circuit according to claim 6, it is characterized in that: in described switching circuit, be provided with a NPN type triode and a positive-negative-positive triode, the base stage of described NPN type triode receives the operating voltage of the second electrifying timing sequence, grounded emitter, collector electrode connects the base stage of positive-negative-positive triode, and by current-limiting resistance, connects the operating voltage of described 3.3V; The emitter of described positive-negative-positive triode connects the operating voltage of described 3.3V, and collector electrode connects the anode of described another diode.
8. electric power management circuit according to claim 7, it is characterized in that: the base stage of described NPN type triode is passed through capacity earth.
9. the described electric power management circuit of any one according to claim 1 to 4, it is characterized in that: described first order direct current conversion chip comprises two, respectively the operating voltage of conversion output 5V and the operating voltage of 3.3V.
10. set-top box, it is characterized in that: comprise process chip and as the described electric power management circuit of any one claim in claim 1 to 9, the operating voltage of the different sequential by described electric power management circuit output transfers to respectively the different power pin of process chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203794579U CN203301371U (en) | 2013-06-28 | 2013-06-28 | Power supply management circuit and set top box |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013203794579U CN203301371U (en) | 2013-06-28 | 2013-06-28 | Power supply management circuit and set top box |
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| CN203301371U true CN203301371U (en) | 2013-11-20 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154728A (en) * | 2017-05-19 | 2017-09-12 | 威创集团股份有限公司 | A kind of DC voltage electrifying timing sequence control device |
| CN110456696A (en) * | 2019-07-31 | 2019-11-15 | 浪潮金融信息技术有限公司 | A kind of intelligent self-service terminal control system |
-
2013
- 2013-06-28 CN CN2013203794579U patent/CN203301371U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107154728A (en) * | 2017-05-19 | 2017-09-12 | 威创集团股份有限公司 | A kind of DC voltage electrifying timing sequence control device |
| CN110456696A (en) * | 2019-07-31 | 2019-11-15 | 浪潮金融信息技术有限公司 | A kind of intelligent self-service terminal control system |
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Granted publication date: 20131120 Termination date: 20190628 |