CN203260588U - Groove terminal structure of power MOSFET - Google Patents
Groove terminal structure of power MOSFET Download PDFInfo
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- CN203260588U CN203260588U CN 201320254969 CN201320254969U CN203260588U CN 203260588 U CN203260588 U CN 203260588U CN 201320254969 CN201320254969 CN 201320254969 CN 201320254969 U CN201320254969 U CN 201320254969U CN 203260588 U CN203260588 U CN 203260588U
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Abstract
The utility model relates to a groove terminal structure of a power MOSFET. The groove terminal structure comprising a substrate and an epitaxial layer arranged on the substrate is characterized in that the epitaxial layer includes a first groove and a second groove; and gate oxide layers are arranged in the grooves. A gate electrode formed by polycrystalline silicon is arranged inside the first groove; and a suspension field plate formed by polycrystalline silicon is arranged inside the second groove. Body regions are arranged between the first groove and the second groove as well as at one side, approaching the boundary of the chip, of the first groove; and a source region is arranged on the body region of one side, approaching the boundary of the chip, of the first groove. An isolation oxidation layer is also arranged at the surface of the silicon wafer; and a source contact structure with good ohmic contact with the source region is arranged at the isolation oxidation layer. According to the structure provided by the utility model, a breakdown voltage of silicon wafer terminal portion is improved with a small occupied area; and the design difficulty of the silicon wafer terminal structure can be reduced.
Description
Technical field
The utility model belongs to technical field of semiconductors, relates to a kind of groove terminal structure of power MOSFET.
Background technology
At present, in the integrated circuit (IC) chip manufacture process, the junction termination technique measure of chip edge can be divided into two large classes:
1, the radius of curvature of tying for increasing curved surface reduces the concentrated of corner region electric field and the terminal protection structure of employing: such as tapered plane technology, depletion etching method, field plate (FP), floating empty field limiting ring (FFLR), knot termination extension (JTE), the horizontal doping of variation (VLD) etc.
2, for the impact that reduces device surface charge and interface charge adopt such as semi-insulating polysilicon film (SIPOS) passivating technique.
For large-size device, particularly only do in the situation of a device at a silicon chip, tapered plane technology, depletion etching method are methods preferably, because they almost can reach desirable puncture voltage, and the surface field reduction is a lot, so the requirement of surface passivation also can be relaxed.So most rectifiers and thyristor all are to make with the combination of positive and negative tapered plane.For power integrated circuit (PIC) and smart-power IC (SPIC), because integrated power device must be transversal device, comparatively commonly used is field plate and RESURF technology.And termination extension and variation are laterally mixed because principle and RESURF technology are similar, therefore also can use.And for vertical power device, such as VDMOS, IGBT etc., using many is field plate and field limiting ring technology.
Produce simply although the field limiting ring technology has, can reach the advantage of high breakdown voltage, it is very responsive to interface charge, and the effect of field limiting ring is had a greatly reduced quality.And the Metal field plate technology is not very sensitive to interface charge; and eliminate interface charge when being connected together with main junction electrode to the impact of device surface; but panel edges on the scene place electric field is concentrated, and the electric field that this high potential difference that can the additional guard ring in panel edges on the scene place weakens field plate and substrate causes is concentrated.Thereby the terminal structure that Metal field plate and field limiting ring combine proposed.This field plate and field limiting ring comprehensive combines both advantage.Adopt the device of this structure not only can realize the requirement of high breakdown voltage, and also have preferably reliability.
But in the design that many field limiting rings and offset field plate combine, the upper field plate length of each ring and ring spacing determines it is a difficult point.And in high tension apparatus; this structure will take larger chip area; as shown in Figure 2; a kind of terminal structure sectional arrangement drawing of prior art is shown near chip edge 17; the silicon chip boundary vicinity has 3 annular tagmas 25; it is withstand voltage to improve terminal to form two protection structures; the withstand voltage setting as required of spacing between the tagma 25; 25 the turning 16 in the tagma; electric field line distribution is concentrated; be the withstand voltage weak spot between tagma 25 and the epitaxial loayer 22, when occuring to puncture, puncture at first herein.
Constantly reduce at device feature size, today that chip area constantly dwindles, this technology area occupied is large, is withstand voltagely limited by the turning, has not had undoubtedly advantage.
The utility model content
Complicated for overcoming the conventional art design process, take the large technological deficiency of silicon area, the utility model provides a kind of groove terminal structure of power MOSFET.
The groove terminal structure of a kind of power MOSFET described in the utility model comprises substrate and the epitaxial loayer that is positioned on the substrate, comprises following whole feature: have the first groove and the second groove on the described epitaxial loayer; Gate oxide is arranged in groove; The gate electrode that described the first groove inside has polysilicon to form; The suspension field plate that described the second groove inside has polysilicon to form; Between the first groove and the second groove and the first groove have the tagma by chip boundary one side; At the first groove by going back active area above the tagma of chip boundary one side; Also possess isolating oxide layer at silicon chip surface, have with the source region at isolating oxide layer to form the source class contact structures that good ohmic contacts.
Preferably, described isolation oxidation layer material is BPSG.
Preferably, described resistance substrate rate is 1 ~ 3 ‰ ohm.cm.
Preferably, described substrate thickness is 200 microns.
Preferably, described source class contact structures comprise the metal contact hole on the isolating oxide layer; Ohmic contact regions is injected in the zone of intersecting with metal contact hole on epitaxial loayer; And pass the metal lead wire that metal contact hole stretches out isolating oxide layer from ohmic contact regions.
Adopt the groove terminal structure of power MOSFET described in the utility model, cylinder between tagma in the prior art and epitaxial loayer knot is become present parallel plane knot, overcome the cylinder knot and caused puncture voltage technological deficiency on the low side at corner area owing to the electric field line concentration of local, improve the puncture voltage of silicon chip terminal part with less area occupied, and reduced the design difficulty of silicon chip terminal structure.
Description of drawings
Fig. 1 illustrates the silicon chip terminal structure schematic diagram of conventional art;
Fig. 2 illustrates the structural representation of a kind of embodiment of the present utility model;
The Reference numeral name is called among each figure: 26. ohmic contact regions, 27. source regions, 17. chip boundary 18. first grooves, 19. second groove 21. substrates, 22. epitaxial loayer 23a. gate oxide 24a. gate electrode 24b. suspension field plate 25. tagmas, 16. turnings, 28. metal contact holes, 29. isolating oxide layers, 210. metal lead wires.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in further detail.
The groove terminal structure of a kind of power MOSFET described in the utility model comprises substrate and the epitaxial loayer that is positioned on the substrate, comprises following whole feature:
Have the first groove and the second groove on the described epitaxial loayer; Has gate oxide in groove inside; The gate electrode that described the first groove inside has polysilicon to form; The suspension field plate that described the second groove inside has polysilicon to form;
Between the first groove and the second groove and the first groove have the tagma by chip boundary one side; At the first groove by going back active area above the tagma of chip boundary one side;
Also possess isolating oxide layer at silicon chip surface, have with the source region at isolating oxide layer to form the source class contact structures that good ohmic contacts.
Preferably, described isolation oxidation layer material is BPSG.
Preferably, described resistance substrate rate is 1 ~ 3 ‰ ohm-cm.
Preferably, described substrate thickness is 200 microns.
Preferably, described source class contact structures comprise the metal contact hole on the isolating oxide layer; Ohmic contact regions is injected in the zone of intersecting with metal contact hole on epitaxial loayer; And pass the metal lead wire that metal contact hole stretches out isolating oxide layer from ohmic contact regions.
The groove terminal structure of a kind of power MOSFET described in the utility model, its implementation procedure comprises the steps (Fig. 2):
Step 101. is at the Grown epitaxial loayer; Etching forms the first groove 18 and is positioned at the first groove near the second groove 19 of chip internal one side on epitaxial loayer; At groove growth inside gate oxide 23a;
Step 102. makes polysilicon fill the whole inner surfaces of whole groove at the first groove and the second groove depositing polysilicon, forms gate electrode 24a at the first groove, forms suspension field plate 24b at the second groove;
Step 103. between the first groove and the second groove and the first groove inject to form tagma 25 by chip boundary one side; Inject by the tagma of chip boundary one side at the first groove subsequently and form source region 27;
Step 104. is at silicon chip surface deposit isolating oxide layer 29, and the source class contact structures 26 that contact with source region formation good ohmic at the isolating oxide layer structure.
Adopt said method can obtain the groove terminal structure of a kind of power MOSFET described in the utility model, comprise substrate and the epitaxial loayer that is positioned on the substrate, possess following feature:
Have the first groove and the second groove on the described epitaxial loayer; Has gate oxide in groove inside; The gate electrode that described the first groove inside has polysilicon to form; The suspension field plate that described the second groove inside has polysilicon to form;
Between the first groove and the second groove and the first groove have the tagma by chip boundary one side; At the first groove by going back active area above the tagma of chip boundary one side;
Also possess isolating oxide layer at silicon chip surface, have with the source region at isolating oxide layer to form the source class contact structures that good ohmic contacts.
In the step 101, etching forms two grooves near the edge of silicon chip, the first groove is positioned at the more close chip edge in outside, the second groove is positioned at the first groove near chip internal one side, the degree of depth of groove and width determine specifically that according to parameters such as doping content, requirement of withstand voltage as a rule, groove is darker, the width of groove is larger, and withstand voltage effect is better.Control thickness and quality that the growth needs of gate oxide 23a is strict.
After groove forms, need in groove, form polysilicon electrode as gate electrode and suspension field plate, and make polysilicon fill the whole inner surfaces of whole groove.During depositing polysilicon, can be at first groove and groove contiguous all surfaces on depositing polysilicon, until fill the whole surface, inside of full two grooves; Subsequently, will do not need the surperficial etching polysilicon that covers of polysilicon fall, polysilicon layer is etched back in the groove, and on the surface recessed segment distance.Thereby in the first groove, form gate electrode 24a and unsettled field plate 24b.Gate electrode 24a and unsettled field plate 24b are by gate oxide 23a and epitaxial loayer 22, and namely the tagma of device forms mutual electricity isolation.Gate electrode is drawn by conductor deposited material such as polysilicon or metal at gate electrode contact hole place (not shown in FIG.).The effect of unsettled field plate is to interrupt the power line of PN junction, near field plate, produce opposite with original direction of an electric field, the field plate electric field of effect counteracting, thus improve withstand voltage.
Subsequently, between the first groove and the second groove and the first groove inject to form the tagma by chip boundary one side; Can adopt photomask to block injection, form the tagma 25 of device.The concrete dosage of tagma 25 implanted dopants and energy will decide according to the threshold voltage of this requirement on devices.Inject by the tagma of chip boundary one side at the first groove subsequently and form the source region; Source region 27 implanted dopant types and tagma type opposite, for example the tagma implanted dopant is N-type, then p type impurity is injected in the source region, preferred source region implantation concentration than high two orders of magnitude of concentration of epitaxial loayer 22 to realize preferably device performance.At silicon chip surface deposit isolating oxide layer, isolating oxide layer covers whole device surfaces subsequently, and the local perforate that only picks out at the needs lead-in wire is with the protection device internal structure; The material of isolating oxide layer is preferably BPSG, i.e. boric acid silex glass material.Form the source class contact structures that good ohmic contacts at the isolating oxide layer structure with the source region at last.Realize freely connecting of source class current potential with convenient.
A kind of embodiment of structure source class contact structures is
Step 104a. is the etching metal contact hole on isolating oxide layer;
Ohmic contact regions is injected in the zone that step 104b. intersects with metal contact hole on epitaxial loayer;
Step 104c. depositing metal on ohmic contact regions is full of metal contact hole, makes the depositing metal height be higher than described isolating oxide layer upper surface.
Ohmic contact regions 26 injects the impurity identical with source class implanted dopant type, to reduce the resistance that contacts with depositing metal herein, prevents that opening by mistake of parasitic NPN transistor opened in the device.In a single day this parasitic transistor is opened, and power device will not controlled by grid, cause component failure.Preferably, the Impurity injection concentration of described ohmic contact regions is greater than two orders of magnitude of tagma Impurity injection concentration in the step 103.Prevent preferably that parasitic transistor from opening by mistake and open effect to reach.
Preferably, after step 101 is all finished to 104, carry out attenuate in the following table faces substrate 21 of silicon chip, can polish is thinned to 200um, is beneficial to individual devices or the encapsulation in chip later stage and uses.
As shown in Figure 2, provide a specific embodiment of the present utility model take substrate as N+ as example
Growth N epitaxial loayer 22 forms device drift region on the substrate 21.The resistivity that substrate 21 is heavily doped to N-type impurity is the scope of 1 ~ 3 ‰ ohm.cm, and the N-type impurity doping content of epitaxial loayer 22 decides according to the withstand voltage of this device.In epitaxial loayer 22, dig dark formation the first groove and be positioned at the first groove near the second groove of chip internal one side.At groove growth inside gate oxide 23a.Deposit is mixed with the polysilicon of N-type impurity as gate electrode 24a and unsettled field plate 24b.In groove, form gate electrode 24a and unsettled field plate 24b.Gate electrode 24a and unsettled field plate 24b are by gate oxide 23a and epitaxial loayer 22, and namely the tagma of device forms mutual electricity isolation.
Then utilize photomask to block and inject the tagma 25 that forms device, what tagma 25 was injected is p type impurity, and concrete dosage and energy will decide according to the threshold voltage of this requirement on devices.Reinject and form device source region 27.What source region 27 was injected is N-type impurity, and final concentration gets final product than high two orders of magnitude of concentration of epitaxial loayer 22.Deposit isolating oxide layer 29, material are the BPSG(boron-phosphorosilicate glass).And on isolating oxide layer 29 etching metal contact hole 28.Inject ohmic contact regions 26.What ohmic contact regions 26 injected be p type impurity, and purpose is the resistance that reduces herein with Metal Contact, prevents that opening by mistake of parasitic NPN transistor opened in the device, and this parasitic transistor is in case unlatching, and power MOSFET will not controlled by grid, cause component failure; The Impurity injection concentration of ohmic contact regions gets final product greater than two orders of magnitude of tagma Impurity injection concentration.The depositing metal lead-in wire 210 subsequently, as the source electrode contacting metal of device.
Adopt the groove terminal structure of power MOSFET described in the utility model, cylinder between tagma in the prior art and epitaxial loayer knot is become present parallel plane knot, overcome the cylinder knot and caused puncture voltage technological deficiency on the low side at corner area owing to the electric field line concentration of local, improve the puncture voltage of silicon chip terminal part with less area occupied, and reduced the design difficulty of silicon chip terminal structure.
Previously described is each preferred embodiment of the present utility model; preferred implementation in each preferred embodiment is if not obviously contradictory or take a certain preferred implementation as prerequisite; each preferred implementation arbitrarily stack combinations is used; design parameter among described embodiment and the embodiment only is the utility model proof procedure for clear statement utility model inventor; be not to limit scope of patent protection of the present utility model; scope of patent protection of the present utility model still is as the criterion with its claims; the equivalent structure that every utilization specification of the present utility model and accompanying drawing content are done changes, and in like manner all should be included in the protection range of the present utility model.
Claims (5)
1. the groove terminal structure of a power MOSFET comprises substrate (21) and is positioned at epitaxial loayer (22) on the substrate, comprises following whole feature:
Have the first groove (18) and the second groove (19) on the described epitaxial loayer (22); Gate oxide (23a) is arranged in groove; The gate electrode (24a) that described the first groove inside has polysilicon to form; The suspension field plate (24b) that described the second groove inside has polysilicon to form;
Between the first groove (18) and the second groove (19) and the first groove have tagma (25) by chip boundary (17) one sides; At the first groove by going back active area (27) above the tagma of chip boundary one side;
Also possess isolating oxide layer (29) at silicon chip surface, have with the source region at isolating oxide layer to form the source class contact structures that good ohmic contacts.
2. the groove terminal structure of power MOSFET as claimed in claim 1, it is characterized in that: described isolating oxide layer (29) material is BPSG.
3. the groove terminal structure of power MOSFET as claimed in claim 1, it is characterized in that: described resistance substrate rate is 1 ~ 3 ‰ ohm.cm.
4. the groove terminal structure of power MOSFET as claimed in claim 1, it is characterized in that: described substrate thickness is 200 microns.
5. the groove terminal structure of power MOSFET as claimed in claim 1, it is characterized in that: described source class contact structures comprise the metal contact hole (28) on the isolating oxide layer; Ohmic contact regions (26) is injected in the zone of intersecting with metal contact hole on epitaxial loayer; And pass the metal lead wire (210) that metal contact hole stretches out isolating oxide layer from ohmic contact regions.
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| CN 201320254969 CN203260588U (en) | 2013-05-13 | 2013-05-13 | Groove terminal structure of power MOSFET |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103295911A (en) * | 2013-05-13 | 2013-09-11 | 成都瑞芯电子有限公司 | Power MOSFET (metal-oxide-semiconductor field effect transistor) trench terminal structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103295911A (en) * | 2013-05-13 | 2013-09-11 | 成都瑞芯电子有限公司 | Power MOSFET (metal-oxide-semiconductor field effect transistor) trench terminal structure and manufacturing method thereof |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: Power MOSFET (metal-oxide-semiconductor field effect transistor) trench terminal structure and manufacturing method thereof Effective date of registration: 20140325 Granted publication date: 20131030 Pledgee: Sichuan Yong Zhi financing Company limited by guarantee Pledgor: Chengdu Promising-chip Electronic Co., Ltd. Registration number: 2014510000006 |
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| PLDC | Enforcement, change and cancellation of contracts on pledge of patent right or utility model | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131030 Termination date: 20160513 |