CN203250150U

CN203250150U - Linear multiplex switch

Info

Publication number: CN203250150U
Application number: CN 201320217670
Authority: CN
Inventors: 华桦; 胡晓宁
Original assignee: Shanghai Institute of Technical Physics of CAS
Current assignee: Shanghai Institute of Technical Physics of CAS
Priority date: 2013-04-26
Filing date: 2013-04-26
Publication date: 2013-10-23
Anticipated expiration: 2023-04-26

Abstract

The utility model discloses a linear multiplex switch which is formed by the connection of a computer serial port, a level conversion module, a counter module, a decoder module, a delay driving module and a relay array according to a connection order. The linear multiplex switch has the advantages that a switch on-state resistance is small, and an off-state resistance is large; the switch is controlled by a computer, and the realization of automation is facilitated; the cost is low, and the size is small.

Description

The alignment multi-way switch

Technical field

This patent relates to the matrix switch field, particularly a kind of alignment multi-way switch.

Background technology

Have now two class multi-way switchs, a kind of is simulation of integrated circuit multi-way switch module, and a kind of is midget relay multi-way switch product.Simulation of integrated circuit multi-way switch module low price, volume is little.Midget relay multi-way switch product function is complete, and switch performance is outstanding, can use computing machine automatically to control

The conducting resistance of typical simulation of integrated circuit multi-way switch module CD4051 is about 80-200 ohm, turn-off leakage current and be about 0.1-200nA, the conducting resistance of another kind of typical simulation of integrated circuit multi-way switch modules A DG4051 is about 4-5 Europe, turn-offs leakage current and is about 0.5-5nA.So the switch performance of simulation of integrated circuit multi-way switch module is relatively poor.7075 switch matrix cards of typical midget relay multi-way switch product such as Keithley company, it is expensive, need to cooperate more expensive switch main control system 707b or 707a to use, and its volume is larger, does not possess portability.

Provide a kind of switch performance outstanding, program-controlled, volume is little, and low-cost multi-way switch becomes those skilled in the art's problem demanding prompt solution.

Summary of the invention

In sum, it is outstanding that the purpose of this patent provides a kind of switch performance, program-controlled, and volume is little, low-cost multi-way switch.

This patent provides a kind of alignment multi-way switch, comprising: serial ports of computers, level switch module, counter module, decoder module, delay driver module and relay array is characterized in that:

Described serial ports of computers is the RS232 serial ports;

Described level switch module is to have the level switch module that two-way is converted to level A respectively level B function.Wherein, A=12V or-12V, B=5V or 0V, and when A=12V, B=5V, when A=-12V, B=0V;

Described counter module is TTL integrated circuit N system Counter module, wherein, and N=8 or 16;

Described decoder module is TTL integrated circuit M-N decoder module, wherein, and M=log ₂N;

Described delay driver module is N road delay driver element side by side;

Described relay array is N road midget relay side by side;

In the alignment multi-way switch, the DTR end of serial ports of computers links to each other with the first via level input end of level switch module, the RTS end of serial ports of computers links to each other with the second road level input end of level switch module, the first via level output end of level switch module links to each other with the counting end of counter module, the the second road level output end of level switch module links to each other with the clear terminal of counter module, the output terminal of counter links to each other with the input end of code translator respectively, the output terminal of code translator links to each other with the delay driver element input end that postpones driver module respectively, and the output positive and negative charge that postpones the delay driver element of driver module links to each other with the midget relay input end both positive and negative polarity of relay array.

Delay driver element in this patent, it is characterized in that, comprise: resistance value is 25 ohm resistance, capacitance is the electrochemical capacitor of 200 microfarads, model is the field effect transistor of 2N7000, one end of its resistance links to each other with power supply, the other end of resistance links to each other with electrochemical capacitor is anodal, the electrochemical capacitor negative pole links to each other with the source electrode of field effect transistor, the grounded drain of field effect transistor, the grid of field effect transistor is for postponing the input end of driver element, and the both positive and negative polarity of electrochemical capacitor is respectively the positive-negative output end that postpones driver element.

The beneficial effect of this patent is:

1) switch conduction resistance is little, and the pass resistance break is large.

2) utilize computing machine to control, convenient realization robotization

3) cost is low, and volume is little.

Description of drawings

Fig. 1 is the ingredient synoptic diagram of this patent.

Fig. 2 is the integrated circuit synoptic diagram of this patent specific embodiment.

Fig. 3 is level switch module principle schematic in this patent specific embodiment.

Fig. 4 is this patent specific embodiment Counter module principle synoptic diagram.

Fig. 5 is decoder module principle schematic in this patent specific embodiment.

Fig. 6 postpones the driver module principle schematic in this patent specific embodiment.

Fig. 7 is this patent specific embodiment repeat circuit array principle schematic.

Embodiment

Below, by reference to the accompanying drawings the specific embodiment of this patent is described.

Fig. 2 is a specific embodiment of this patent, present embodiment is 16 route row multi-way switchs, comprises successively according to its order of connection: serial ports of computers 01, level switch module 02, counter module 03, decoder module 04, delay driver module 05 and relay array 06.

Referring to Fig. 3, Fig. 4, Fig. 6, in the present embodiment, supply voltage VCC is 5V.

Referring to Fig. 3, in the present embodiment, described level switch module 02 adopts the universal serial port level to turn the Transistor-Transistor Logic level circuit, the serial ports level voltage of input converts Transistor-Transistor Logic level voltage to by serial ports level transferring chip MAX232, DTR port, the RTS port that concrete connected mode is described serial ports of computers 01 connects respectively 13 pins and 8 pins of described serial ports level transferring chip MAX232, the Transistor-Transistor Logic level voltage after 12 corresponding pins and the 9 pins output conversion.

Referring to Fig. 4, in the present embodiment, described counter module 03 adopts integrated binary counter chip 74LS161N, 7 pins of described integrated binary counter chip 74LS161N, 9 pins, 10 pins connect power supply, zero clearing input port 1 pin connects 12 pins of described serial ports level transferring chip MAX232, and counting input end mouth 2 pins connect 9 pins of described serial ports level transferring chip MAX232 by phase inverter 7404N.14 pins, 13 pins, 12 pins, 11 pins are exported respectively the 1st, the 2nd, the 3rd and the 4th of binary value.

Referring to Fig. 5, in the present embodiment, described decoder module 04 is integrated 4-16 decoder chip 74154N, 18 pins of described integrated 4-16 decoder chip 74154N, 19 pin ground connection, the 1st scale-of-two input port 23 pins, the 2nd scale-of-two input port 22 pins, the 3rd scale-of-two input port 21 pins, the 4th scale-of-two input port 20 pins connect respectively 14 pins, 13 pins, 12 pins and 11 pins of described integrated binary counter chip 74LS161N.

Referring to Fig. 6, in the present embodiment, described delay driver module 05 is 16 tunnel side by side delay driver elements, described 16 the tunnel side by side delay driver element circuit first via input end, the second road input end, Third Road input end, the four road input end ... the ten six road input ends respectively by phase inverter 7074N connect described integrated 4-16 decoder chip 74154N 1 pin, 2 pins, 3 pins, 4 pins ... 16 pins, realize the gating function of 16 tunnel addresses.

Referring to Fig. 7, in the present embodiment, described relay array 06 employing 16 tunnel model side by side is the midget relay of TX2-5V, concrete connected mode is, the first via, the second tunnel, Third Road, the four tunnel ... the positive-negative input end mouth of the tenth No. six midget relaies respectively with 16 the tunnel side by side delay driver element circuit the first via, the second tunnel, Third Road, the four tunnel ... the ten six road positive-negative output ends are connected.

The control of the described 16 route row multi-way switchs of present embodiment utilizes the LabVIEW program of writing on the computing machine to realize, before the program operation, input serial ports of computers address and switch number, the serial ports address is for being generally COM1, switch number is to treat the numbering of the midget relay of gating, and switch number is 1 to 16 in the present embodiment.During the program operation, utilize built-in serial data terminal standby condition (DTR State) program module of LabVIEW software to send 1 group of high and low level pulse to the DTR port of described serial ports of computers 01 described 16 route row switches are resetted, the built-in serial ports request of recycling LabVIEW software sends state (RTS State) program module and sends n to the RTS port of described serial ports of computers 01 and organize the gating that high and low level pulse is realized the particular microchannel relay.Wherein, n is that switch number subtracts 1.

The above only is the preferred embodiment of this patent, and all equalizations of doing according to this patent claim scope change and modify, and all should belong to the covering scope of this patent claim.

Claims

1. alignment multi-way switch, comprising: serial ports of computers, level switch module, counter module, decoder module, delay driver module and relay array is characterized in that:

Described serial ports of computers is the RS-232 serial ports;

Described level switch module is to have the level switch module that two-way is converted to level A respectively level B function, wherein, A=12V or-12V, B=5V or 0V, and when A=12V, B=5V, when A=-12V, B=0V;

Described delay driver module is N road delay driver element side by side;

Described relay array is N road midget relay side by side;

2. a kind of alignment multi-way switch according to claim 1, it is characterized in that: the delay driver element in the described delay driver module comprises that resistance value is 25 ohm resistance, capacitance is the electrochemical capacitor of 200 microfarads, model is the field effect transistor of 2N7000, one end of its resistance links to each other with power supply, the other end of resistance links to each other with electrochemical capacitor is anodal, the electrochemical capacitor negative pole links to each other with the source electrode of field effect transistor, the grounded drain of field effect transistor, the grid of field effect transistor is for postponing the input end of driver element, and the both positive and negative polarity of electrochemical capacitor is respectively the positive-negative output end that postpones driver element.