CN203250095U - Array substrate and displaying device - Google Patents
Array substrate and displaying device Download PDFInfo
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- CN203250095U CN203250095U CN 201320306574 CN201320306574U CN203250095U CN 203250095 U CN203250095 U CN 203250095U CN 201320306574 CN201320306574 CN 201320306574 CN 201320306574 U CN201320306574 U CN 201320306574U CN 203250095 U CN203250095 U CN 203250095U
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Abstract
The utility model discloses an array substrate and a displaying device, and relates to the displaying field. The array substrate and the displaying device resolve the problems that a liquid crystal displayer is greenish, and has a horizontal X-talk problem and other bad displaying problems on the premise that transmittance is not lowered, and improves the picture quality of the displaying device especially a high-resolution product. The array substrate comprises a substrate body, a semiconductor layer, a source-drain electrode layer, a grid insulation layer, a first grid metal layer, a second grid insulation layer and a second grid metal layer, wherein the semiconductor layer, the source-drain electrode layer and the grid insulation layer are sequentially arranged on the substrate body from bottom to top, the first grid metal layer is arranged on the grid insulation layer, the second grid insulation layer is arranged under the semiconductor layer, and the second grid metal layer is arranged between the second grid insulation layer and the substrate body.
Description
Technical field
The utility model relates to the demonstration field, relates in particular to a kind of array base palte and display device.
Background technology
Liquid crystal display is light, low in energy consumption because of its quality, and radiation is little, can save in a large number the advantages such as space, now replaced traditional cathode-ray tube display, is widely used in each demonstration field, such as family, public place, office field and personal electric Related product etc.
As shown in Figure 1, the available liquid crystal display comprises display pixel (unit) and is used for the thin film transistor (TFT) (TFT) that the control display data load.Wherein, thin film transistor (TFT) adopts bottom grating structure (grid of thin film transistor (TFT) is positioned at the below of semiconductor layer 13) usually, specifically comprises: substrate 10, on be successively set on grid metal level 110, gate insulation layer 122, semiconductor layer 13 and source-drain electrode layer 14 on the substrate 10 from bottom to top; Display pixel comprises: public electrode 17, passivation layer 18, the pixel electrode 20 and the liquid crystal that are arranged on the passivation layer 18 (are positioned at the top of pixel electrode 20, not shown), pixel electrode 20 is connected to the drain electrode of thin film transistor (TFT), public electrode 17 is connected to public electrode wire 190, pixel electrode 20 is by TFT loaded and displayed data, public electrode 17 produces with pixel electrode 20 and drives electric fields, thereby liquid crystal molecule deflects under this driving electric field action and demonstrates image.
Adopt bottom grating structure TFT, grid metal level 110 can block the light that sends from the backlight of array base palte side, exterior light (exterior light that enters from color membrane substrates one side) is then blocked by black matrix B M, but the inventor finds: when the contraposition deviation appears in color membrane substrates and array base palte, perhaps the technique of array base palte occurs when bad, semiconductor layer easily occurs to be exposed, this moment, the irradiation because of exterior light caused the leakage current of TFT unusually to increase, and it is bad that the demonstrations such as partially green (Greenish) and horizontal gray scale uneven (X-talk) appear in liquid crystal display as a result.
In addition, the especially high-resolution product of liquid crystal display, need to reduce the resistance of public electrode, otherwise on business the excessive generation of common electrode resistance postpones, liquid crystal display partially green (Greenish) and gray scale uneven (X-talk) etc. also easily occur to be shown bad, affect picture quality, if but reduce the resistance of public electrode by the live width that increases public electrode, can cause again aperture opening ratio to reduce.
The utility model content
Technical problem to be solved in the utility model is to provide a kind of array base palte and display device, can be under the prerequisite that does not reduce transmitance, solve liquid crystal display and the bad problems of demonstration such as partially green (Greenish) and horizontal gray scale uneven (X-talk) occur, improve the especially picture quality of high-resolution products of display device.
For achieving the above object, embodiment of the present utility model adopts following technical scheme:
A kind of array base palte comprises: substrate, be set in turn in semiconductor layer, source-drain electrode layer, gate insulation layer on the described substrate from bottom to top, and described array base palte also comprises:
Be arranged on the first grid metal level on the described gate insulation layer;
Be arranged on the second gate insulation course of the below of described semiconductor layer; And,
Be arranged on the second gate metal level between described second gate insulation course and the described substrate.
Further, described array base palte also comprises:
The first public electrode wire is positioned at same layer with described first grid metal level, perhaps is positioned at same layer with described second gate metal level.
Further, described array base palte also comprises: the second public electrode wire,
When described the first public electrode wire and described first grid metal level were positioned at same layer, described the second public electrode wire and described second gate metal level were positioned at same layer; When described the first public electrode wire and described second gate metal level were positioned at same layer, described the second public electrode wire and described first grid metal level were positioned at same layer.
Preferably, described the second public electrode wire and described the first public electrode line parallel, and the second public electrode wire is identical with the live width of the first public electrode wire.
Further, described array base palte also comprises:
Resin bed covers on the described first grid metal level; And,
Driving the first electrode, second electrode of liquid crystal, and be arranged on the passivation layer between described the first electrode, the second electrode for generation of electric field, described the first electrode is arranged on the described resin bed, and described the second electrode is arranged on the described passivation layer.
Alternatively, described the first electrode is connected with described the first public electrode wire by the via hole in the described resin bed.
Alternatively, described the second electrode links to each other with the drain electrode of described source-drain electrode layer by the drain via in described resin bed and the described gate insulation layer.
Preferably, described the second electrode is slit-shaped.
The array base palte that the utility model provides and display device, in the above and below of semiconductor layer second gate metal level and first grid metal level are set respectively, the first grid metal level that is positioned at semiconductor layer top blocks exterior light from top incident (light that enters from color membrane substrates one side); The second gate metal level that is positioned at the semiconductor layer below blocks from the below (light that the backlight of array base palte side sends), can prevent that like this semiconductor layer is subject to irradiation, the TFT leakage current of avoiding causing because of irradiation increases unusually, and the position correspondence of first grid metal level and second gate metal level is overlapping, therefore can be under the prerequisite that does not reduce transmitance, improve partially green (Greenish) that liquid crystal display occurs and horizontal gray scale uneven (X-talk) etc. and show bad problem, improve the picture quality of display device.
Description of drawings
Fig. 1 is a kind of structural representation of existing array base palte;
The structural representation of the array base palte that Fig. 2 provides for the utility model embodiment one;
The structural representation of the array base palte that Fig. 3 provides for the utility model embodiment two;
The manufacture method process flow diagram of the array base palte that Fig. 4 provides for the utility model embodiment four;
Fig. 5 is the manufacture process schematic diagram of array base palte among the utility model embodiment four;
Fig. 6 is the process flow diagram of step 103 among Fig. 4;
Fig. 7 is the manufacture process schematic diagram of step 103 among Fig. 4.
Description of reference numerals
The 10-substrate, 110-grid metal level, 111-second gate metal level, 112-first grid metal level, 121-second gate insulation course, 122-gate insulation layer, the 13-semiconductor layer, 14-source-drain electrode layer, 15-resin bed, the 16-data line, 17-public electrode, 18-passivation layer, the 190-public electrode wire, 191-the second public electrode wire, 192-the first public electrode wire, 20-pixel electrode.
Embodiment
The utility model embodiment provides a kind of array base palte and display device, can be under the prerequisite that does not reduce transmitance, and improve partially green (Greenish) that liquid crystal display occurs and horizontal X-talk etc. and show badly, improve the picture quality of display device.
Below in conjunction with accompanying drawing the utility model embodiment is described in detail.Embodiment described herein is only in order to explaining the utility model, and is not used in restriction the utility model.
Embodiment one
The utility model embodiment provides a kind of array base palte, and as shown in Figure 2, this array base palte comprises: substrate 10 and be set in turn in semiconductor layer 13, source-drain electrode layer 14, gate insulation layer 122 on the described substrate from bottom to top also comprises:
Be arranged on the first grid metal level 112 on the gate insulation layer 122;
Be arranged on the second gate insulation course 121 of the below of semiconductor layer 13; And,
Be arranged on the second gate metal level 111 between second gate insulation course 121 and the substrate 10.
Wherein, described second gate metal level 111 also can adopt identical material with first grid metal level 112, for example is selected from molybdenum, aluminium, chromium, the copper one or more.Described second gate insulation course 121 also can adopt identical material with gate insulation layer 122, for example can be silicon nitride film, certainly also can adopt different materials.
In addition, the second gate metal level described in the present embodiment 111 includes grid and grid line pattern with first grid metal level 112.Preferably, second gate metal level 111 has identical figure with first grid metal level 112, can adopt same mask plate to carry out photoetching and form.Therefore, second gate metal level 111 includes grid and the grid line that links to each other with grid with first grid metal level 112.
In the implementation, the designer can select in following two schemes as required.The first string is that thin film transistor (TFT) adopts top gate structure, and the gated sweep signal is added on the top grid and grid line of first grid metal level 112 formation, and second gate metal level 111 only plays a part to block backlight; Certainly thin film transistor (TFT) also can adopt bottom grating structure, and the gated sweep signal is added on the bottom gate and grid line of second gate metal level 111 formation, and first grid metal level 112 only works to block exterior light.Second scheme is the thin film transistor (TFT) that forms double channel, and namely thin film transistor (TFT) adopts double-gate structure, and the gated sweep signal is loaded into simultaneously: on the grid line and bottom gate that the grid line that first grid metal level 112 forms and top grid and second gate metal level 111 form.The material of gate insulation layer 122 and second gate insulation course 121 all is SiN
x, all be the interface of carrier moving.The thin film transistor (TFT) of double channel can increase firing current.
The described array base palte of the present embodiment, second gate metal level 111 and first grid metal level 112 are set respectively in the above and below of semiconductor layer 13, and the first grid metal level 112 that is positioned at semiconductor layer 13 tops blocks exterior light from top incident (light that enters from color membrane substrates one side); The second gate metal level 111 that is positioned at semiconductor layer 13 belows blocks from the below (light that the backlight of array base palte side sends), can prevent that like this semiconductor layer 13 is subject to irradiation, the TFT leakage current of avoiding causing because of irradiation increases unusually, and the position correspondence of first grid metal level 112 and second gate metal level 111 is overlapping, and therefore transmitance can not reduce.In the implementation, the deviation of 3～4um can appear in the technique of array base palte usually, and therefore stacked covering (Overlay) error of grid metal level can improve horizontal X-talk characteristic below 1um.
In sum, the described array base palte of the present embodiment can be under the prerequisite that does not reduce transmitance, improves partially green (Greenish) that liquid crystal display occurs and horizontal X-talk etc. and shows badly, improves the picture quality of display device.
Further, described array base palte also comprises: the first public electrode wire 192, be positioned at same layer (as shown in Figure 2) with first grid metal level 112, and perhaps be positioned at same layer with second gate metal level 111.
Also comprise: resin bed 15 covers on the first grid metal level 112; And,
For generation of first electrode (public electrode 17 in corresponding diagram), second electrode (pixel electrode 20 in corresponding diagram) of electric field with the driving liquid crystal, and be arranged on passivation layer 18 between the first electrode, the second electrode, the first electrode (public electrode 17) is arranged on the resin bed 15, and the second electrode (pixel electrode 20) is arranged on the passivation layer 18.
The first electrode and the second electrode in the present embodiment refer to respectively pixel electrode and public electrode, if one of them (such as second electrode) is pixel electrode, another (first electrode) then is public electrode, only, be required to be the slit-shaped electrode at upper electrode, under electrode can be plate electrode, also can be the slit-shaped electrode.And, link to each other with the transistorized drain electrode of said film as second electrode (also can be the first electrode) of pixel electrode, link to each other with public electrode wire as first electrode (being the second electrode accordingly) of public electrode.For example, as shown in Figure 2, the public electrode 17 of below is plate electrode, is connected with the first public electrode wire 192 by the via hole in the resin bed 15; The pixel electrode 20 of top is the slit-shaped electrode, link to each other with the drain electrode of thin film transistor (TFT) by the via hole in resin bed 15 and the gate insulation layer 122, described thin film transistor (TFT) is by comprising: first grid metal level 112, gate insulation layer 122, source-drain electrode layer 14, semiconductor layer 13 consist of.Show that data are loaded into pixel electrode 20 and public electrode 17 through this thin film transistor (TFT), pixel electrode 20 and public electrode 17 produce and drive electric fields, thereby liquid crystal molecule deflects under this driving electric field action and demonstrates image.
The described array base palte of the present embodiment can be under the prerequisite that does not reduce transmitance, improves partially green (Greenish) that liquid crystal display occurs and horizontal X-talk etc. and shows badly, improves the picture quality of display device.
Embodiment two
The utility model embodiment provides a kind of array base palte, is with embodiment illustrated in fig. 2 one difference part, and described array base palte also comprises: the second public electrode wire,
When described the first public electrode wire and described first grid metal level were positioned at same layer, described the second public electrode wire and described second gate metal level were positioned at same layer; When described the first public electrode wire and described second gate metal level were positioned at same layer, described the second public electrode wire and described first grid metal level were positioned at same layer;
Described the second public electrode wire links to each other with described the first public electrode wire by the via hole in described insulation course and the described gate insulation layer.
For better understanding the present embodiment, enumerate a kind of embodiment of the present embodiment at this, as shown in Figure 3, this array base palte comprises: substrate 10 is set in turn in second gate metal level 111, second gate insulation course 121, semiconductor layer 13, source-drain electrode layer 14, gate insulation layer 122 and first grid metal level 112 on the substrate 10 from bottom to top; In addition, this array base palte also comprises:
The first public electrode wire 192 is positioned at same layer with first grid metal level 112;
The second public electrode wire 191 is positioned at same layer with second gate metal level 111;
The second public electrode wire 191 links to each other with the first public electrode wire 192 by the via hole in second gate insulation course 121 and the gate insulation layer 122.
In the present embodiment, the first public electrode wire 192 is positioned at same layer with first grid metal level 112, can be made synchronously through steps such as gluing, exposure, etching, developments by same metallic diaphragm.Similarly, the second public electrode wire 191 also is positioned at same layer with second gate metal level 111, can be made synchronously by same metallic diaphragm equally.
The excessive generation of public electrode resistance postpones and affects picture quality, the demonstrations such as liquid crystal indicator partially green (Greenish) and horizontal X-talk also easily occurs bad, affects picture quality.Form public electrode by width or the use low electrical resistant material that strengthens public electrode, can reduce public electrode resistance, but the width that strengthens public electrode generally can affect pixel aperture ratio; And the use low electrical resistant material, it is limited that the resistance of public electrode reduces, but also may need to change preparation technology, therefore lacks practicality.
And the present embodiment forms the live width of the second public electrode wire 191, the second public electrode wires 191 again less than or equal to the live width of the first public electrode wire 192 below thin film transistor (TFT).The second public electrode wire 191 is in parallel with the first public electrode wire 192, and the position of the second public electrode wire 191 and the first public electrode wire 192 overlaids, mutually block, therefore need not to strengthen live width just can reduce public electrode under the prerequisite that does not affect pixel aperture ratio resistance, avoid the on business excessive generation delay of common electrode resistance, this is particularly important to the especially high-resolution product of display device.Wherein, preferably, the second public electrode wire 191 is in parallel with the first public electrode wire 192, and the second public electrode wire 191 adopts the live width identical with the first public electrode wire 192.
Wherein, described array base palte also comprises: data line 16 is positioned at same layer with the source-drain electrode layer 14 of thin film transistor (TFT).
Further, described array base palte also comprises:
Driving pixel electrode 20, the public electrode 17 of liquid crystal, and be arranged on the passivation layer 18 between pixel electrode 20, the public electrode 17 for generation of electric field, public electrode 17 is arranged on the resin bed 15, and pixel electrode 20 is arranged on the passivation layer 18.
Wherein, alternatively, public electrode 17 is connected with the first public electrode wire 192 by the via hole in the resin bed 15; Pixel electrode 20 links to each other with source leakage metal level 14 (drain electrode of thin film transistor (TFT)) by the via hole in resin bed 15 and the lower gate insulation layer 122 thereof.Be slit-shaped at upper pixel electrode 20, the public electrode 17 that is positioned at the below can be tabular also can be slit-shaped.
In addition, need to prove, what link to each other with drain electrode in the present embodiment is pixel electrode, what link to each other with public electrode wire is public electrode, the position of public electrode and pixel electrode can exchange, only be required to be slit-shaped at upper electrode, under electrode can be tabular also can be slit-shaped.
The array base palte that the present embodiment provides because the effect of blocking of first grid metal level and second gate metal level, can be avoided unusually increasing because semiconductor layer is subject to the TFT leakage current that irradiation causes; Adopt simultaneously the overlapping double structure of first, second public electrode wire, can reduce the resistance of public electrode under the prerequisite that does not affect pixel aperture ratio, avoiding on business, the excessive generation of common electrode resistance postpones.Therefore, the described array base palte of the present embodiment can be under the prerequisite that does not reduce transmitance, improves partially green (Greenish) that liquid crystal display occurs and horizontal X-talk etc. and shows badly, improves the picture quality of display device.
Embodiment three
The utility model embodiment also provides a kind of display device, and it comprises any one array base palte described in embodiment one and two.Described display device can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.
The described display device of the present embodiment, because having adopted on the array base palte described in the utility model, therefore can be under the prerequisite that does not reduce transmitance, to improve partially green (Greenish) that display device occurs and horizontal X-talk etc. and show badly, display effect is improved.
Embodiment four
On the other hand, the utility model embodiment also provides a kind of manufacture method of array base palte, and as shown in Figure 4 and Figure 5, the method comprises:
101, form second gate metal level 111 at substrate 10;
Array base palte also can as shown in Figure 3, comprise that the first public electrode wire 192 and the second public electrode wire 191, the second public electrode wires 191 can be positioned at same layer with second gate metal level 111 in the present embodiment.Alternatively, this step forms the grid metallic diaphragm at substrate 10, usually form film and can adopt the various ways such as deposition, coating, sputter, then by applying the steps such as photoresist gluing, exposure, development and etching, form the pattern of second gate metal level 111 (patterns that comprise grid and grid line) at substrate 10, and the pattern of the second public electrode wire 191.Employed mask plate in the time of can using the first grid metal level that forms thin film transistor (TFT) in the step 103 when preferably, this step is exposed.
102, form second gate insulation course 121 at the substrate of finishing 101 steps;
Second gate insulation course 121 is identical with gate insulation layer 12 figures shown in Figure 1, so this step can adopt employed mask plate when forming gate insulation layer 12 in the prior art, formation drain via when forming gate insulation layer, the transistorized drain electrode of exposed film.Can certainly not use mask plate to form via hole, form the second gate insulation course and get final product.The material of first, second gate insulation layer generally adopts SiN
xDeng insulating material.
103, on the substrate of finishing 102 steps, form successively from bottom to top: semiconductor layer 13, source-drain electrode layer 14, gate insulation layer 122 and first grid metal level 112; Wherein, source-drain electrode layer 14 comprises the pattern of source electrode, drain electrode, data line.
Alternatively, the first public electrode wire 192 shown in Figure 3 can be positioned at same layer with first grid metal level 112, and the first public electrode wire 192 links to each other with the second public electrode wire 191 by the via hole in gate insulation layer 122 and the insulation course 121.
Form thin film transistor (TFT) in this step, and first public electrode wire 192 that also has with synchronously formation of first grid metal level 112, if form in addition the structural drawing of Fig. 3, what also need this moment so to form is: the via hole that is connected of the second public electrode wire 191 and the first public electrode wire 192.
The material that this step semiconductor layer 13, source-drain electrode layer 14, gate insulation layer 122 and first grid metal level 112 adopt and preparation method and prior art are roughly similar, for example, the 2nd time masking process forms semiconductor layer, the 3rd time masking process forms source-drain electrode layer 14, the 4th masking process in gate insulation layer 122, form 191 with 192 be connected via hole and drain via, the 5th masking process forms first grid metal level 112.
Only, because two via holes need be set on the gate insulation layer 122, can not use original mask plate, employed mask plate in the time of can using step 104 to form resin bed 15.
104, form the via pattern of resin bed and resin bed at the substrate of finishing 103 steps;
The via pattern that forms resin bed 15 refers to: the via hole that is connected that forms public electrode 17 and the first public electrode wire 192, further, can when forming this connection via hole of resin bed, form in the lump drain via, etching time and etching difficulty in the time of can reducing follow-up via hole formation.Drain via is used for connecting the drain electrode of pixel electrode and thin film transistor (TFT).
105, form the first transparent conductive film layer at the substrate of finishing 104 steps, adopt composition technique to form the first electrode.Among Fig. 5, the first electrode is public electrode 17, and public electrode 17 links to each other with the first public electrode wire 192 by the via hole in the resin bed 15 of the first public electrode wire 192 tops;
106, form the via pattern of passivation layer 18 and passivation layer at the substrate of finishing 105 steps;
The via pattern that this step forms passivation layer can have 2 schemes: the first string, can form drain via at passivation layer 18, and run through passivation layer 18, resin bed 15 and gate insulation layer 122, expose drain electrode; Second scheme also can form drain via step by step, namely on the basis of the resin bed 15 that is formed with drain via and then form the via hole run through passivation layer 18 and get final product.
107, form the second transparent conductive film layer at the substrate of finishing 106 steps, adopt composition technique to form the second electrode.
Alternatively, as shown in Figure 5, the second electrode is that pixel electrode 20 and pixel electrode 20 link to each other with the drain electrode of thin film transistor (TFT) by the drain via that runs through passivation layer 18, resin bed 15 and gate insulation layer 122.
The manufacturing method of array base plate that the present embodiment provides, need not to increase new mask plate, be provided with first, second grid metal level as the barrier bed of thin film transistor (TFT) semiconductor layer in the array base palte that forms, can avoid unusually increasing because semiconductor layer is subject to the TFT leakage current that irradiation causes; Further, also be provided with the first stacked public electrode wire and the second public electrode wire in the array base palte of formation, can reduce the resistance of public electrode under the prerequisite that does not affect pixel aperture ratio, avoiding on business, the excessive generation of common electrode resistance postpones.Therefore, the described array base palte of the present embodiment can be under the prerequisite that does not reduce transmitance, improves partially green (Greenish) that liquid crystal display occurs and horizontal X-talk etc. and shows badly, improves the picture quality of display device.
Wherein, preferably, the second electrode (pixel electrode 20 among the figure) is slit-shaped.
Wherein, alternatively, step 103 specifically can comprise as shown in Figure 6:
Below the narration process with reference to shown in Figure 7.
1031, form semiconductor layer 13 at described second gate insulation course 121, and adopt composition technique to form the semiconductor layer pattern of described thin film transistor (TFT);
1032, form source-drain electrode layer 14, adopt composition technique to form respectively source electrode and drain electrode and the data line 16 of described thin film transistor (TFT) at semiconductor layer 13;
1033, form gate insulation layer 122;
1034, form first grid metal level 112, adopt composition technique to form grid, grid line, and the first public electrode wire 192, the first public electrode wires 192 are positioned at the correspondence position of the second public electrode wire 191 tops.
The manufacture method of the array base palte that the present embodiment provides, need not to increase new mask plate, the array base palte that forms can be under the prerequisite that does not reduce transmitance, improves partially green (Greenish) that liquid crystal display occurs and horizontal X-talk etc. and shows badly, improves the picture quality of display device.
Need to prove; in the utility model embodiment; the sequence number of described each step can not be used for limiting the sequencing of each step; for those of ordinary skills; under the prerequisite of not paying creative work, the priority of each step is changed also within protection domain of the present utility model
The described technical characterictic of the utility model embodiment in the situation that do not conflict, can be used in combination arbitrarily mutually.
The above; it only is embodiment of the present utility model; but protection domain of the present utility model is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; can expect easily changing or replacing, all should be encompassed within the protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the protection domain of claim.
Claims (9)
1. array base palte comprises: substrate and be set in turn in semiconductor layer, source-drain electrode layer, gate insulation layer on the described substrate from bottom to top, it is characterized in that, and described array base palte also comprises:
Be arranged on the first grid metal level on the described gate insulation layer;
Be arranged on the second gate insulation course of the below of described semiconductor layer; And,
Be arranged on the second gate metal level between described second gate insulation course and the described substrate.
2. array base palte according to claim 1 is characterized in that, also comprises:
The first public electrode wire is positioned at same layer with described first grid metal level, perhaps is positioned at same layer with described second gate metal level.
3. array base palte according to claim 2 is characterized in that, also comprises: the second public electrode wire,
When described the first public electrode wire and described first grid metal level were positioned at same layer, described the second public electrode wire and described second gate metal level were positioned at same layer; When described the first public electrode wire and described second gate metal level were positioned at same layer, described the second public electrode wire and described first grid metal level were positioned at same layer.
4. array base palte according to claim 3 is characterized in that,
Described the second public electrode wire and described the first public electrode line parallel, and the second public electrode wire is identical with the live width of the first public electrode wire.
5. each described array base palte is characterized in that according to claim 1-4, also comprises:
Resin bed covers on the described first grid metal level; And,
Driving the first electrode, second electrode of liquid crystal, and be arranged on the passivation layer between described the first electrode, the second electrode for generation of electric field, described the first electrode is arranged on the described resin bed, and described the second electrode is arranged on the described passivation layer.
6. array base palte according to claim 5 is characterized in that,
Described the first electrode is connected with described the first public electrode wire by the via hole in the described resin bed.
7. array base palte according to claim 5 is characterized in that,
Described the second electrode links to each other with the drain electrode of described source-drain electrode layer by the drain via in described resin bed and the described gate insulation layer.
8. array base palte according to claim 7 is characterized in that,
Described the second electrode is slit-shaped.
9. a display device is characterized in that, comprises each described array base palte of claim 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320306574 CN203250095U (en) | 2013-05-30 | 2013-05-30 | Array substrate and displaying device |
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|---|---|---|---|
| CN 201320306574 CN203250095U (en) | 2013-05-30 | 2013-05-30 | Array substrate and displaying device |
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| CN203250095U true CN203250095U (en) | 2013-10-23 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103309108A (en) * | 2013-05-30 | 2013-09-18 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN106098786A (en) * | 2016-06-13 | 2016-11-09 | 武汉华星光电技术有限公司 | Double grid electrode oxide thin film transistor and preparation method thereof |
-
2013
- 2013-05-30 CN CN 201320306574 patent/CN203250095U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103309108A (en) * | 2013-05-30 | 2013-09-18 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof and display device |
| CN103309108B (en) * | 2013-05-30 | 2016-02-10 | 京东方科技集团股份有限公司 | Array base palte and manufacture method, display device |
| US9484465B2 (en) | 2013-05-30 | 2016-11-01 | Boe Technology Group Co., Ltd. | Array substrate, manufacturing method thereof and display device |
| CN106098786A (en) * | 2016-06-13 | 2016-11-09 | 武汉华星光电技术有限公司 | Double grid electrode oxide thin film transistor and preparation method thereof |
| US10236388B2 (en) | 2016-06-13 | 2019-03-19 | Wuhan China Star Optoelectronics Technology Co., Ltd | Dual gate oxide thin-film transistor and manufacturing method for the same |
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