CN203219280U

CN203219280U - Clock counting device

Info

Publication number: CN203219280U
Application number: CN 201320198414
Authority: CN
Inventors: 李林
Original assignee: HWA CREATE SHANGHAI CO Ltd
Current assignee: Beijing Huali Zhifei Technology Co ltd
Priority date: 2013-04-18
Filing date: 2013-04-18
Publication date: 2013-09-25
Anticipated expiration: 2023-04-18

Abstract

The utility model provides a clock counting device and belongs to the counting field. The clock counting device comprises an accumulating device, a comparator, a feedback unit, and a zeroization circuit, wherein a preset value input end and the output end of the accumulating device are connected with the input end of the comparator, the output end of the comparator is connected with the input end of the feedback unit, the output end of the feedback unit is connected with the zeroization circuit, and the output end of the zeroization circuit is connected with the input end of the accumulating device. The clock counting device is characterized in that a complex calculation process is finished by dividing the complex calculation process into multiple clock periods through pipeline operation. Compared with a conventional accumulating device, the clock counting device is characterized by being capable of working under synchronized clock frequency which is higher than the synchronized clock frequency under which the conventional accumulating device works.

Description

A kind of clock count device

Technical field

The utility model relates to the counting field, particularly a kind of clock count device.

Background technology

At present, be the important tool that synchro system is carried out fixed cycle operator based on the counter of clock, and counter can also be used in places such as address generation, input and output counter.Therefore, counter is the common building block in the ASIC hardware system.So, a counter must can be operated under the various clock frequencies, and possesses the input of change preset value configuration feature.And the hardware of counter is realized should be simple and clear, is easy to proving correctness, uses standard cell lib to realize, is easy to transplant between different foundries processing lines.

Yet the efficient of counter commonly used can't satisfy the requirement of related process at present.In addition, a conventional summary counter carries out data accumulation in single clock cycle only usually, can't work under high synchronised clock frequency.

The utility model content

The purpose of this utility model is to provide a kind of high-frequency clock counting device of dependable performance.

The utility model solves above-mentioned technical problem by such technical scheme: a kind of clock count device comprises accumulator, comparator, feedback unit and zero circuit, the output of preset value input and accumulator all is connected the input of comparator, the output of comparator connects the input of feedback unit, the output of feedback unit connects zero circuit, and the output of zero circuit connects the input of accumulator.

The utlity model has following advantage: only can realize clock counting circuit by logic hardware, simplify the hardware configuration of clock count device; Simultaneously, by pile line operation complex calculation is decomposed to a plurality of clock cycle and finish, compared to the summary counter of routine, can under higher synchronised clock frequency, work.

Description of drawings

The clock count schematic representation of apparatus that Fig. 1 provides for the utility model preferred embodiment;

The sequential chart that Fig. 2 provides for the utility model preferred embodiment.

Embodiment

The clock count schematic representation of apparatus that Fig. 1 provides for the utility model preferred embodiment.See also Fig. 1, the clock count device 10 that the utility model preferred embodiment provides comprises accumulator 100, comparator 102, feedback unit 104 and zero circuit 106.The preset value input 101 of clock count device 10 and the output of accumulator 100 all are connected the input of comparator 102, the output of comparator 102 connects the input of feedback unit 104, the output of feedback unit 104 connects zero circuit 106, and the output of zero circuit 106 connects the input of accumulator 100.

Described feedback unit 104 is used for controlling according to the comparative result of described comparator 102 output of described zero circuit 106; Described zero circuit 106 is used for described accumulator 100 countings of control.

Particularly, comparator 102 comprises the definite value input, input and output add up.Wherein, the definite value input can frequently not change under specific operation mode, and the input value of the input that adds up can be 0 or last one and constantly adds 1.Whether the output result of described output indicates the definite value input and equates with the value of the input input that adds up.In this, the preset value input connects the definite value input, and the output of accumulator connects the input that adds up.Feedback unit 104 comprises two outputs, and one of them output connects the input of zero circuit, and another output then is the output as a result 107 of clock count device.

In present embodiment, accumulator 100 adopts full synchronised clock design, and uses carry lookahead adder.So, accumulator 100 can be operated in than under the routine clock frequency that ripple adder is higher by turn.In addition, accumulator 100 can be forced to count again after the zero clearing.In this, the pressure zero clearing of accumulator 100 is by zero circuit 106 controls.

In present embodiment, comparator 102 comprises combinational circuit and sequence circuit.Wherein, combinational circuit comprises NAND gate, NOR gate and adder.Sequence circuit comprises the synchronised clock register.

In present embodiment, comparator 102 is the synchronous circuits that are operated under the unified clock.Particularly, the definite value input of comparator 102 deducts 4 and obtains interim definite value in two clock cycle, the input that adds up synchronously deducts 4 and is imported temporarily in two clock cycle, comparator 102 is more interim definite value and interim input in two clock cycle.If interim definite value equates that with interim input then the output of the output of comparator 102 equates to indicate to feedback unit 104.If feedback unit 104 obtains to equate sign from the output of comparator 102, then feedback unit 104 control zero circuits 106 send rz signal, and simultaneously, feedback unit 104 is to output 107 output equivalent results as a result.Wherein, the result of output 107 outputs is as a result for example represented by display lamp that green light represents to equate that red light is represented unequal.Yet the present invention does not limit this.In addition, if zero circuit 106 sends rz signal, then the output of zero circuit 106 control accumulator 100 restarts counting, namely forces the accumulator zero clearing.

The sequential chart that Fig. 2 provides for the utility model preferred embodiment.Followingly describe in detail with reference to Fig. 2.

In present embodiment, the operation principle of clock count device 10 is as follows.As shown in Figure 2, if the value of preset value input input is 18, and this moment, the value of accumulator output output was 10, because described preset value input connects described definite value input, the output of described accumulator connects the described input that adds up, therefore, the value of definite value input is 18, the value 10 of the input that adds up.Deduct 4 according to the definite value input of comparator in two clock cycle and obtain interim definite value, the input that adds up synchronously deducts 4 and imported temporarily in two clock cycle, and hence one can see that: interim definite value is 14, is input as 6 temporarily.In addition, in this two cycles, accumulator continues to add up, and becomes 12 by 10.Described comparator is more described interim definite value and described interim input in two clock cycle, at this moment, both are unequal, and because comparison procedure has also spent two clock cycle, at this moment, the value that accumulator adds up is 14, according to above-mentioned principle, proceed comparison, equate with interim input until interim definite value, the zero clearing of zero circuit control accumulator restarts counting.

The clock count device that preferred embodiment provides according to the utility model the utlity model has following advantage: only can realize clock counting circuit by logic hardware, simplify the hardware configuration of clock count device; Simultaneously, by pile line operation complex calculation is decomposed to a plurality of clock cycle and finish, compared to the summary counter of routine, can under higher synchronised clock frequency, work.

The above only is preferred embodiments of the present utility model; protection range of the present utility model is not limited with above-mentioned execution mode; as long as the equivalence that those of ordinary skills do according to the utility model institute disclosure is modified or changed, all should include in the protection range of putting down in writing in claims.

Claims

1. clock count device, it is characterized in that, comprise accumulator, comparator, feedback unit and zero circuit, the output of preset value input and described accumulator all is connected the input of described comparator, the output of described comparator connects the input of described feedback unit, the output of described feedback unit connects described zero circuit, and the output of described zero circuit connects the input of described accumulator.

2. clock count device as claimed in claim 1 is characterized in that, described feedback unit is used for controlling according to the comparative result of described comparator the output of described zero circuit; Described zero circuit is used for the described accumulator count of control.

3. clock count device as claimed in claim 2 is characterized in that, if described feedback unit indicates that from the output acquisition of described comparator is equal then described feedback unit is controlled described zero circuit and sent rz signal.

4. clock count device as claimed in claim 3 is characterized in that, if described zero circuit sends described rz signal, then the output of described zero circuit is controlled described accumulator and restarted counting.

5. clock count device as claimed in claim 1 is characterized in that, described accumulator adopts full synchronised clock design, and uses carry lookahead adder.

6. clock count device as claimed in claim 1 is characterized in that, described comparator comprises combinational circuit and sequence circuit, and wherein, described combinational circuit comprises NAND gate, NOR gate and adder, and described sequence circuit comprises the synchronised clock register.

7. clock count device as claimed in claim 1, it is characterized in that, described comparator comprises the definite value input, input and output add up, described preset value input connects described definite value input, the output of described accumulator connects the described input that adds up, and whether the output result of described output indicates described definite value input and equate with the described value that adds up the input input.

8. clock count device as claimed in claim 7, it is characterized in that, described comparator is the synchronous circuit that is operated under the unified clock, the described definite value input of described comparator deducts 4 and obtains interim definite value in two clock cycle, the described input that adds up synchronously deducts 4 and is imported temporarily in two clock cycle, described comparator is more described interim definite value and described interim input in two clock cycle, if described interim definite value equates that with described interim input then the output of the output of described comparator equates that sign is to described feedback unit.