CN203217560U

CN203217560U - Bus converter

Info

Publication number: CN203217560U
Application number: CN 201320181126
Authority: CN
Inventors: 刘军; 吴勇; 徐阳; 刘月; 刘华涵
Original assignee: Beijing BNC Technologies Co Ltd
Current assignee: Beijing BNC Technologies Co Ltd
Priority date: 2013-04-11
Filing date: 2013-04-11
Publication date: 2013-09-25
Anticipated expiration: 2023-04-11

Abstract

The utility model discloses a bus converter which is connected with an outer ISA device. The bus converter comprises a CPU, a bus converter and a data resolver. The CPU is connected with the bus converter and the data resolver. The bus converter is connected with the CPU, the data resolver and the outer ISA device. The bus converter receives multiple paths of parallel interrupt signals which are transmitted by the outer ISA device, generates a path of serial interrupt signals after coding the parallel interrupt signals and transmits the path of serial interrupt signals to the data resolver. The bus converter is further responsible for data interaction between an ISA bus and a PCI bus. The data resolver receives the serial interrupt signals sent by the bus converter and resolves the serial interrupt signals to generate complete analysis data. The CPU receives the analysis data sent by the data resolver, processes the analysis data, responds correspondingly, generates control data and transmits the control data to the bus converter. The bus converter then transmits the control data to the outer ISA device.

Description

A kind of bus conversion device

Technical field

The utility model is the field of using about computer bus, relates to a kind of bus conversion device.

Background technology

(Central Processing Unit CPU) is X86CPU or ARM to the central processing unit that present most of mainboard adopts, and these key chips are foreign country and produce, and chip production company may leave the back door in chip, have potential safety hazard.And the restricted and stranger of the key component that makes product, inconvenience is used for as key areas such as armies.

Now, the isa bus interface belongs to the bus interface of eliminating, and only also has at some special dimensions such as military projects and uses, so be fit to the solution deficiency of present stage on the market, can't satisfy some special dimensions such as military project to safety, the specific (special) requirements of reliability and stability.

The utility model content

The technical matters that the utility model solves has overcome the shortcoming of prior art, utilizes a kind of information security and reliability each side stronger central processing unit and bus converter, carries out the conversion of bus, to satisfy the application to isa bus.

The utility model provides a kind of bus conversion device, is connected in exterior I SA equipment, and described bus conversion device comprises: a central processing unit, a bus converter and a data parser; Described central processing unit is connected in described bus converter and described data parser, and described bus converter is connected in described central processing unit, described data parser and described exterior I SA equipment; Be connected for isa bus between described bus converter and the described exterior I SA equipment, be connected for pci bus between described bus converter and the described central processing unit, be connected for single string line between described bus converter and the described data parser, be connected for pci bus between described central processing unit and the described data parser; Wherein, described bus converter receives the multidiameter delay look-at-me that described exterior I SA equipment sends, and described multidiameter delay look-at-me coding back is generated one tunnel serial look-at-me, and be sent to described data parser; Described data parser receives the serial look-at-me that described bus converter sends, and described serial look-at-me is resolved, and generates complete resolution data, is sent to described central processing unit; Described central processing unit receives the resolution data that described data parser sends, described resolution data is handled, and made corresponding response, generate the control data, be sent to described bus converter, described bus converter is sent to described exterior I SA equipment with described control data again; Described exterior I SA equipment receives described control data, and according to the control data exterior I SA device data is sent to described bus converter; Described bus converter also receives described exterior I SA device data, and described exterior I SA device data is sent to described central processing unit.

Further, described central processing unit is the Loongson2F central processing unit.

Further, described bus converter is the IT8888G chip.

Further, described data parser is fpga chip or CPLD chip.

The utility model mainly adopts the Loongson2F central processing unit, than the scheme that adopts foreign chip obvious enhancing is being arranged aspect information security and the reliability; Avoided the potential safety hazard of using foreign chip to bring, and can promote the development of homemade CPU, avoided under one's control at key technology area.The isa bus interface that utilizes in the utility model belongs to the bus interface of having eliminated, only also has at some special dimensions such as military projects and uses, so be fit to the solution deficiency of present stage on the market; This scheme can satisfy these special dimensions to the demand of isa bus, and pci bus and isa bus commonly used are changed, and can avoid some ripe ISA equipment problems because there not being the suitable applications device to use in these fields.

Description of drawings

Accompanying drawing described herein is used to provide further understanding of the present utility model, constitutes the application's a part, does not constitute restriction of the present utility model.In the accompanying drawings:

Fig. 1 is the structural representation of utility model bus conversion device of the present invention.

Figure 2 shows that the structural representation of the bus conversion device of the utility model one specific embodiment.

Figure 3 shows that the structural representation of the bus conversion device of another specific embodiment of the utility model.

Embodiment

For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing the utility model embodiment is described in further details.At this, the utility model be used for is explained in illustrative examples of the present utility model and explanation thereof, but not as to restriction of the present utility model.

Fig. 1 is the structural representation of utility model bus conversion device of the present invention.As shown in Figure 1, bus conversion device 10 is external in exterior I SA equipment 20, comprises central processing unit 101, bus converter 102 and data parser 103; Central processing unit 101 is connected in described bus converter 102 and data parser 103, and bus converter 102 is connected in central processing unit 101, data parser 103 and exterior I SA equipment 104; Be connected for isa bus between bus converter 102 and the described exterior I SA equipment 20, be connected for pci bus between bus converter 102 and the central processing unit 101, be connected for single string line between bus converter 102 and the data parser 103, be connected for pci bus between central processing unit 101 and the data parser; Wherein,

Exterior I SA equipment 20 sends the bus converter 102 of multidiameter delay look-at-me to the bus conversion device 10, bus converter 102 receives described multidiameter delay look-at-me, described multidiameter delay look-at-me is integrated the coding back generate one tunnel serial look-at-me, and be sent to described data parser.

In the present embodiment, bus converter 102 is the IT8888G chip.

Data parser 103 receives the serial look-at-me that bus converter 102 sends, and described serial look-at-me is resolved the complete resolution data that generation can supply central processing unit 101 to read, and resolution data is sent to described central processing unit 101;

In the present embodiment, data parser 103 is fpga chip or CPLD chip.

Central processing unit 101 receives the resolution data that data parser 103 sends, resolution data is handled, and made corresponding response, generate control data, be sent to bus converter 102, bus converter 102 will be controlled data again and be sent to described exterior I SA equipment 20.

In the present embodiment, central processing unit 101 is the Loongson2F central processing unit.The Loongson2F central processing unit is the homemade general risc processor of 64 MIPS III of a realization instruction set.

MIPS is a kind of CPU framework, and what Loongson2F central processing unit and following Loongson1A central processing unit were used is this framework.

In the present embodiment, after central processing unit 101 reads resolution data, carrying out data handles, judge on the exterior I SA equipment 20 what situation has taken place, arriving as data can be for reading, and data are to be sent etc., central processing unit 101 is made corresponding response to this, as begin to transmit instruction such as exterior I SA equipment 20 data, generate the control data, and these control data are sent to exterior I SA equipment 20 via bus converter 102.

Exterior I SA equipment 20 according to the instruction of central processing unit 101, is carried out corresponding operation after receiving the described control data that central processing units 101 send, such as transmit outer ISA device data etc.

Bus converter 102 is responsible for the data interaction on isa bus and the pci bus, receives exterior I SA device data, these data is passed through pci bus again and transfers in the central data 101.

Figure 2 shows that the structural representation of the bus conversion device of the utility model one specific embodiment.As shown in Figure 2, Loongson2F central processing unit 301 is central processing unit, is responsible for control and the operation of whole device.IT8888G chip 302 is responsible for the pci bus of drawing on the Loongson2F central processing unit 301 is converted to isa bus.Because interrupt line quantity too much (at least 20) on the isa bus, and only provide 4 interrupt lines on the pci bus, so the parallel look-at-me of the multichannel on the isa bus (at least 20) can't be passed to pci bus one to one, also can't directly pass to Loongson2F central processing unit 301, because remaining interrupt pin quantity also can't satisfy the requirement of so many interrupt line on the Loongson2F central processing unit 301.So IT8888G chip 302 is passed to fpga chip 303 to the signal integration coding back of sending on the interrupt line surplus parallel 20 by a serial port bundle of lines look-at-me, fpga chip 303 just can resolve to complete interrupting information to described serial look-at-me and be sent to Loongson2F central processing unit 301, after process Loongson2F central processing unit 301 carries out the data processing, return control data and give exterior I SA equipment 20, with 20 next step operations of indication exterior I SA equipment.

In the present embodiment, because fpga chip 303 also is responsible for the CAN function on device, resolve the serial look-at-me just wherein with the fraction function, if do not need the CAN function, can change fpga chip 303 into function that the CPLD chip realizes resolving look-at-me, can reduce cost like this.

In the present embodiment, IT8888G chip 302 is converted to isa bus to pci bus, because ISA interface interrupt pin is many but the pci bus interrupt pin is few, so integrating code conversion to parallel look-at-me, IT8888G chip 302 becomes the serial look-at-me, originally the pin that needed 20 has only been become and need get final product by 1 pin, reduce the shared area of winding displacement, and reduced the difficulty of manufacture craft.

Figure 3 shows that the structural representation of the bus conversion device of another specific embodiment of the utility model.As shown in Figure 3, the bus conversion device 30 of the Fig. 2 that compares, the bus conversion device 30 of present embodiment also comprises a Loongson1A central processing unit 304; Described Loongson1A central processing unit 304 connects Loongson2F central processing unit 301 by pci bus, serves as south bridge in the present embodiment, controls some IO equipment, such as network interface, serial ports, parallel port, ide interface, audio interface etc.

The utility model acp chip mainly adopts Loongson2F central processing unit and Loongson1A central processing unit.Than the scheme that adopts foreign chip obvious enhancing is being arranged aspect information security and the reliability; Avoided the potential safety hazard of using foreign chip to bring, and can promote the development of homemade CPU, avoided under one's control at key technology area.And the isa bus interface that utilizes in the utility model belongs to the bus interface of having eliminated, only also has at some special dimensions such as military projects and uses, so be fit to the solution deficiency of present stage on the market; This scheme can satisfy these special dimensions to the demand of isa bus, and pci bus and isa bus commonly used are changed, and can avoid some ripe ISA equipment problems because there not being the suitable applications device to use in these fields.

Above-described specific embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiment of the utility model; and be not used in and limit protection domain of the present utility model; all within spirit of the present utility model and principle, any modification of making, be equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.

Claims

1. a bus conversion device is characterized in that, is connected in exterior I SA equipment, and described bus conversion device comprises: a central processing unit, a bus converter and a data parser; Described central processing unit is connected in described bus converter and described data parser, and described bus converter is connected in described central processing unit, described data parser and described exterior I SA equipment; Be connected for isa bus between described bus converter and the described exterior I SA equipment, be connected for pci bus between described bus converter and the described central processing unit, be connected for single string line between described bus converter and the described data parser, be connected for pci bus between described central processing unit and the described data parser; Wherein,

Described bus converter receives the multidiameter delay look-at-me that described exterior I SA equipment sends, and described multidiameter delay look-at-me coding back is generated one tunnel serial look-at-me, and be sent to described data parser;

Described data parser receives the serial look-at-me that described bus converter sends, and described serial look-at-me is resolved, and generates complete resolution data, is sent to described central processing unit;

Described central processing unit receives the resolution data that described data parser sends, described resolution data is handled, and made corresponding response, generate the control data, be sent to described bus converter, described bus converter is sent to described exterior I SA equipment with described control data again;

Described exterior I SA equipment receives described control data, and according to the control data exterior I SA device data is sent to described bus converter;

Described bus converter also receives described exterior I SA device data, and described exterior I SA device data is sent to described central processing unit.

2. device according to claim 1 is characterized in that, described central processing unit is the Loongson2F central processing unit.

3. device according to claim 1 is characterized in that, described bus converter is the IT8888G chip.

4. device according to claim 1 is characterized in that, described data parser is fpga chip or CPLD chip.