CN203206106U - Power factor correction circuit and control circuit thereof - Google Patents
Power factor correction circuit and control circuit thereof Download PDFInfo
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- CN203206106U CN203206106U CN2013201300381U CN201320130038U CN203206106U CN 203206106 U CN203206106 U CN 203206106U CN 2013201300381 U CN2013201300381 U CN 2013201300381U CN 201320130038 U CN201320130038 U CN 201320130038U CN 203206106 U CN203206106 U CN 203206106U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
A power factor correction circuit and a control circuit thereof are disclosed. The PFC circuit includes: a switching circuit including a main switch; a conduction time control circuit for generating a conduction time control signal; a first off time control circuit generating a first off time control signal; a second off-time control circuit generating a second off-time control signal; and a logic circuit receiving the on-time control signal, the first off-time control signal, and the second off-time control signal, wherein the first off-time control signal controls the on-state of the main switch in a continuous current mode, and the second off-time control signal controls the on-state of the main switch in an interrupted current mode. The circuit can work in a continuous current mode and an intermittent current mode, and has higher efficiency and power factor when in light load than the traditional continuous current mode control method.
Description
Technical field
The utility model embodiment relates to the control circuit of power supply, is specifically related to circuit of power factor correction and control circuit thereof.
Background technology
Power factor correction (PFC) circuit is widely used in the power conversion system, is used for the phase place of correcting current, improves power factor.Fig. 1 shows a kind of waveform schematic diagram of PFC control.As shown in the figure, input voltage vin is steamed bun waveform shape, and the sinusoidal ac signal that input voltage is generally civil power obtains behind over commutation.In order to realize PFC control, need the waveform of control inputs electric current I in to follow the waveform of input voltage vin, make the phase place of input current Iin consistent with input voltage vin.Usually, the lower input current average value Iin_avg of higher input voltage vin correspondence.In the switching mode pfc circuit, input current Iin is the sawtooth waveforms shape, thus the waveform of average current Iin_avg that can be by control inputs electric current I in follow input voltage waveform and improve power factor, realize power factor correction.
Simultaneously, international energy management organization has also proposed higher requirement to the conversion efficiency of pfc circuit.Yet the efficient of existing pfc circuit product under low loading condition can't well meet the requirement of energy administrative institutions expectation.
Therefore, be necessary pfc circuit is improved, to raising the efficiency, particularly the efficient under the low carrier strip spare does not increase again too many cost simultaneously.
The utility model content
In order to solve a previously described problem or a plurality of problem, the utility model proposes a kind of pfc circuit and control circuit thereof.
According to some embodiment, provide a kind of pfc circuit to comprise: switching circuit, comprise main switch, switching circuit has input and output, and wherein input receives input voltage and has input current, and output provides output voltage; The ON time control circuit, the shutoff that produces ON time control signal control main switch; The first turn-off time control circuit produces the first turn-off time control signal; The second turn-off time control circuit produces the second turn-off time control signal; And logical circuit, receiving ON time control signal, the first turn-off time control signal and the second turn-off time control signal, output control signal control main switch optionally works in continuous current mode or discontinuous current mode; Wherein under continuous current mode, the first turn-off time control signal is controlled the conducting of main switch; Under discontinuous current mode, the conducting of the second turn-off time control signal control main switch.Pfc circuit can further comprise the 3rd turn-off time control circuit, the 3rd turn-off time control circuit produces the 3rd turn-off time control signal, wherein logical circuit further receives the 3rd turn-off time control signal and controls main switch and optionally works in the critical current pattern, the wherein conducting of the 3rd turn-off time control signal control main switch under the critical current pattern.Wherein the main switch frequency under the discontinuous current mode is lower than the main switch frequency under the continuous current mode.In one embodiment, switching circuit comprises boost conversion circuit.In one embodiment, the ON time control circuit has first input end, the second input and output, wherein first input end couples the input voltage detection signal that characterizes input voltage, the second input couples the output voltage feedback signal that characterizes output voltage, output output ON time control signal.In one embodiment, the ON time control circuit comprises: the first current source produces the electric current that is proportional to output voltage; The first electric capacity couples the first current source, and the first electric capacity has first end and the second end, and wherein first end couples with reference to ground, and the second end provides the first capacitance voltage; The first switch, have first end, the second end and control end, wherein the first end of the first switch couples the first end of the first electric capacity, the second end of the first switch couples the second end of the first electric capacity, conducting when the first switch turn-offs at main switch, the first switch turn-offs when the main switch conducting, and when the first switch turn-offed, the first current source was to the first capacitor charging; Subtraction circuit couples input voltage detection signal and output voltage feedback signal, produces secondary signal; Comparison circuit has first input end, the second input and output, and wherein the first input end of comparison circuit receives the first capacitance voltage, and the second input of comparison circuit receives secondary signal, the output output ON time control signal of comparison circuit.In one embodiment, the first turn-off time control circuit comprises comparison circuit, comparison circuit has first input end, the second input and output, wherein first input end couples the first reference current signal, the second input couples the input current feedback signal that characterizes input current, and comparison circuit comparison the first reference current signal and input current feedback signal are also exported the first turn-off time control signal at output.In one embodiment, the second turn-off time control circuit comprises: the second current source produces the electric current that is proportional to the first reference current signal; The second charge switch, and the series connection of the second current source; The 3rd current source produces the electric current that is proportional to two times of reference signals of average current, and wherein two times of reference signals of average current characterize the twice of input current average expected volume; Discharge switch, and the series connection of the 3rd current source; The second electric capacity has first end and the second end, and wherein first end couples with reference to ground, and the second end provides the second capacitance voltage; Wherein when input current greater than zero the time, the second charge switch conducting, the second current source raises the second capacitance voltage to the second capacitor charging; When input current is zero, the 3rd charging open pipe conducting, the 3rd current source reduces the second capacitance voltage to the second capacitor discharge; And comparison circuit, have first input end, the second input and output, wherein first input end couples the second capacitance voltage, the second input couples the second reference signal, and comparison circuit comparison the second capacitance voltage and the second reference signal are also exported the second turn-off time control signal at the output of comparison circuit.Logical circuit can comprise: pattern decision circuit, export the first enable signal and the second enable signal based on the two times of reference signals of average current and the input current peak signal that characterize input current average expected volume twice, wherein the first enable signal couples the first turn-off time control circuit, the second enable signal couples the second turn-off time control circuit, and pattern decision circuit optionally suppresses the first turn-off time control circuit or the second turn-off time control circuit; Or door, have first end, the second end and output, wherein first end receives the first turn-off time control signal, and the second termination is received the second turn-off time control signal; And latch cicuit, have set end, reset terminal and output, wherein the set end couples or the output of door, and reset terminal receives the ON time control signal, the turn-on and turn-off of output control main switch.In one embodiment, above-mentioned pfc circuit further comprises: the reference signal circuit for generating produces two times of reference signals of average current based on input voltage detection signal and output voltage feedback signal; The peak current sample circuit couples the input current feedback signal, output input current peak signal; And subtraction circuit, couple two times of reference signals of average current and input current peak signal, export the first reference current signal.Wherein the reference signal circuit for generating can comprise: error amplifying circuit, have first input end, the second input and output, wherein first input end couples output voltage feedback signal, and the second input couples reference voltage, and output provides the output voltage compensation signal; The input voltage average circuit has input and output, and wherein input couples the input voltage detection signal, and output provides the input voltage average signal; And mlultiplying circuit, have first input end, the second input, the 3rd input and output, wherein first input end couples the output of error amplifying circuit for receiving the output voltage compensation signal, the second input couples the input voltage detection signal, the output that the 3rd input couples the input voltage average circuit is used for receiving the input voltage average signal, and output provides average current two times of reference signals.
According to some embodiment, a kind of PFC control circuit is provided, the main switch between input and the output of being coupled to that is used for the control switch circuit, wherein input has input voltage and input current, output has output voltage, the PFC control circuit comprises: the ON time control circuit produces the ON time control signal based on input voltage and output voltage, the shutoff of control main switch; The first turn-off time control circuit produces the first turn-off time control signal; The second turn-off time control circuit produces the second turn-off time control signal; And logical circuit, the control main switch optionally works in continuous current mode or discontinuous current mode; Wherein under continuous current mode, the first turn-off time control signal is controlled the conducting of main switch; Under discontinuous current mode, the conducting of the second turn-off time control signal control main switch.In one embodiment, the main switch frequency under the discontinuous current mode is lower than the main switch frequency under the continuous current mode.The ON time control circuit can comprise: the first current source is proportional to output voltage; The first electric capacity, by the charging of the first current source, the first electric capacity has first end and the second end, and wherein first end couples with reference to ground, and the second end provides the first capacitance voltage; The first switch has first end, the second end and control end, and wherein the first end of the first switch couples the first end of the first electric capacity, and the second end of the first switch couples the second end of the first electric capacity, conducting when the first switch turn-offs at main switch; Subtraction circuit couples input voltage detection signal and output voltage feedback signal, produces secondary signal; And comparison circuit, relatively the first capacitance voltage and secondary signal, when the first capacitance voltage during greater than secondary signal, the output output signal control main switch of comparison circuit turn-offs.The first turn-off time control circuit can comprise comparison circuit, comparison circuit with input current feedback signal and the first reference current signal relatively, when input current feedback signal during less than the first reference current signal, the output control main switch conducting of comparison circuit.The second turn-off time control circuit can comprise: the second current source, be proportional to the first reference current signal, and wherein the first reference current signal is the difference signal of two times of reference signals of average current and input current peak signal; The 3rd current source is proportional to two times of reference signals of average current; And second electric capacity, have first end and the second end, wherein first end couples with reference to ground, the second end provides the second capacitance voltage, wherein to the second capacitor charging the second capacitance voltage is raise when input current second current source greater than zero time, the 3rd current source reduces the second capacitance voltage to the second capacitor discharge when input current is 0; And comparison circuit, compare the second capacitance voltage and the second reference signal and export the second turn-off time control signal.Control circuit can further comprise: error amplifying circuit, have first input end, the second input and output, and wherein first input end couples output voltage feedback signal, and the second input couples reference voltage, and output provides the output voltage compensation signal; The input voltage average circuit has input and output, and wherein input couples the input voltage detection signal, and output provides the input voltage average signal; Mlultiplying circuit, have first input end, the second input, the 3rd input and output, wherein first input end couples the output of error amplifying circuit for receiving the output voltage compensation signal, the second input couples the input voltage detection signal, the output that the 3rd input couples the input voltage average circuit is used for receiving the input voltage average signal, and output provides average current two times of reference signals; The peak current sample circuit couples the input current feedback signal, output input current peak signal; And subtraction circuit, couple two times of reference signals of average current and input current peak signal, export the first reference current signal.
The pfc circuit and control circuit and the control method that provide according to embodiment of the present utility model, can work in continuous current mode and also can work in discontinuous current mode, have under the high and low carrier strip spare of power factor efficient high, realize analog circuit control and low cost and other advantages.
Description of drawings
In order better to understand the utility model, will be described embodiment of the present utility model according to the following drawings:
Fig. 1 shows a kind of oscillogram for PFC control;
Fig. 2 shows the pfc circuit block diagram according to the utility model one embodiment;
Fig. 3 shows the pfc circuit schematic diagram according to the utility model one specific embodiment;
Fig. 4 shows the pfc circuit schematic diagram according to another embodiment of the utility model;
Fig. 5 shows the ON time control circuit according to the utility model one embodiment;
Fig. 6 show according to the utility model one embodiment in the predetermined ON time oscillogram of steamed bun of input voltage in period of wave;
Fig. 7 shows the first turn-off time control circuit according to the utility model one embodiment;
Fig. 8 shows the waveform schematic diagram according to the first turn-off time control circuit in the corresponding diagram 7 of the utility model one embodiment;
Fig. 9 shows the second turn-off time control circuit according to the utility model one embodiment;
Figure 10 shows the waveform schematic diagram according to the second turn-off time control circuit in the corresponding diagram 9 of the utility model one embodiment;
Figure 11 shows the 3rd turn-off time control circuit according to the utility model one embodiment;
Figure 12 shows according to the input current waveform figure under the different loads of the utility model one embodiment;
Figure 13 shows according to the frequency diagram under the different loads of the utility model one embodiment;
Figure 14 shows the waveform schematic diagram according to pfc circuit in the corresponding diagram 4 of the utility model one embodiment.
Accompanying drawing does not show all circuit or the structure of embodiment.Run through institute's identical Reference numeral of drawings attached and represent same or analogous parts or feature.
Embodiment
The below will describe specific embodiment of the utility model in detail, should be noted that the embodiments described herein only is used for illustrating, and be not limited to the utility model.To in the detailed description of the present utility model, in order to understand better the utility model, a large amount of details has been described below.Yet it will be understood by those skilled in the art that does not have these details, and the utility model can be implemented equally.In order to set forth the utility model clearly, this paper has simplified the detailed description of some concrete structures and function.In addition, the similar 26S Proteasome Structure and Function of having described in detail in certain embodiments repeats no more in other embodiments.Although every term of the present utility model is to describe one by one in conjunction with concrete example embodiment, these terms should not be construed as the demonstration execution mode that is confined to set forth here.
" coupling " of mentioning in the specification of the present utility model can refer to directly to connect or the connection by indirect thing, such as the connection by conductor, this conductor has resistance, also parasitic parameter can be arranged, as have inductance value and a capacitance, and as the connection by semiconductor device such as diode etc.
Fig. 2 shows the pfc circuit block diagram 200 according to the utility model one embodiment.Pfc circuit 200 comprises switching circuit 21 and PFC control circuit 20.Switching circuit 21 comprises main switch M, and switching circuit 21 has input 211 and output 212, and wherein input 211 receives input voltage vin, and input 211 further has modulated input current Iin under the control of pfc circuit 200.The switch motion of PFC control circuit 20 control main switch M, pfc circuit 200 converts input voltage vin to output voltage V out and exports at the output 212 of switching circuit 21 under the switch motion of main switch M.Control circuit 20 comprises ON time control circuit 24 (ON), the first turn-off time control circuit 22 (OFF1), the second turn-off time control circuit 23 (OFF2) and logical circuit 25.ON time control circuit 24 produces the ON time of ON time control signal R1 control main switch M, and controls the shutoff of main switch M at the terminal point of ON time.In illustrated embodiment, ON time control signal R1 produces ON time control signal R1 based on input voltage vin and output voltage V out.
Input voltage vin detect to obtain input voltage detection signal Vi through input voltage detection circuit, and wherein input voltage detection circuit can be arbitrarily voltage detecting circuit, and such as resistor voltage divider circuit etc., for for purpose of brevity, input voltage detection circuit does not specifically illustrate.Input current Iin detects through the input current feedback circuit and obtains input current feedback signal Ii.In one embodiment, input current detection signal Ii is a magnitude of voltage, and input current feedback signal Ii is proportional to the value of input current Iin.For for purpose of brevity, the input current feedback circuit does not specifically illustrate.Output voltage V out detects through the output voltage feedback circuit and obtains output voltage feedback signal Vfb.In one embodiment, the output voltage feedback circuit is resistor voltage divider circuit.
Therefore, ON time control signal R1 can produce based on input voltage detection signal Vi and output voltage feedback signal Vfb.In another embodiment, ON time control signal R1 only produces based on input voltage detection signal Vi.
The first turn-off time control circuit 22 produces the first turn-off time control signal S1, is used for the conducting of control main switch M under continuous current mode, with the length of control main switch turn-off time.In one embodiment, the first turn-off time control circuit 22 produces the first turn-off time control signal S1 based on input current feedback signal Ii and output voltage feedback signal Vfb.In one embodiment, the first turn-off time control circuit 22 produces the first turn-off time control signal S1 based on input current feedback signal Ii, input voltage detection signal Vi and output voltage feedback signal Vfb.
The second turn-off time control circuit 23 produces the second turn-off time control signal S2, is used for the conducting of control main switch M under discontinuous current mode, with the length of control main switch turn-off time.In one embodiment, the second turn-off time control circuit 23 produces the second turn-off time control signal S2 based on input current feedback signal Ii and output voltage feedback signal Vfb.In another embodiment, the second turn-off time control circuit 23 produces the second turn-off time control signal S2 based on input current feedback signal Ii, output voltage feedback signal Vfb and input voltage detection signal Vi.
Fig. 3 shows pfc circuit 300 schematic diagrames according to the utility model one specific embodiment.Pfc circuit 300 comprises rectification circuit 37, switching circuit 31 and control circuit 30.In another embodiment, pfc circuit 300 does not comprise rectification circuit 37.In illustrated embodiment, rectification circuit 37 carries out rectification with sinusoidal voltage Vac, exports steamed bun ripple Vin, namely is positioned at the input voltage vin of switching circuit 31 inputs.In description, mark Vin and Vout, except representing input voltage vin and output voltage V out, but the also input of representation switch circuit 31 and output.Mark Vi, Ii, Vfb, GND and Vg also can represent each end points of control circuit 31 except representing input voltage detection signal Vi, input current feedback signal Ii, output voltage feedback signal Vfb, reference ground GND and switch controlling signal Vg.
In illustrated embodiment, switching circuit 31 comprises boost conversion circuit.Switching circuit 31 has input Vin and output end vo ut.Switching circuit 31 inside comprise main switch M, inductance L 1, diode D and output capacitance Co.Inductance L 1 first end receives input voltage vin, inductance L 1 second end couples the first end of main switch M, the second end of main switch M couples with reference to ground GND, the anode of diode D couples the second end of inductance L 1, the negative electrode of diode D couples the first end of output capacitance Co, and the second end of output capacitance Co couples with reference to ground GND.The first end of the negative electrode of diode D and output capacitance Co provides output voltage V out.In another embodiment, diode D is replaced by switching tube.Although input capacitance Ci has been shown in the illustrated embodiment, in another embodiment, pfc circuit does not comprise input capacitance Ci.Under the on-off action of main switch M, the size of 31 couples of output voltage V out of switching circuit and input current Iin is regulated, so that the waveform of input current Iin is followed the waveform of input voltage vin.In another embodiment, switching circuit 31 comprises the voltage boosting-reducing translation circuit.
The second turn-off time control circuit 33 is based on average current reference signal Ith, and input current peak signal Ipk and current status detection signal Vpd produce the second turn-off time control signal S2.In illustrated embodiment, the second turn-off time control circuit 33 is based on the first reference current signal Iref, and two times of reference signal Id of average current and current status detection signal Vpd produce the second turn-off time control signal S2.Wherein two times of reference signal Id of average current are two times of values of average current reference signal Ith.Fig. 9 shows the second turn-off time control circuit according to the utility model one embodiment, and chapters and sections are described in detail below.
ON time control circuit 34 has first input end 341, the second input 342 and output 343, wherein first input end 341 couples input voltage detection signal Vi, the second input 342 couples output voltage feedback signal Vfb, output 343 output ON time control signal R1.Fig. 5 shows the ON time control circuit according to the utility model one embodiment, and chapters and sections are below described in detail.
In illustrated embodiment, reference signal circuit for generating 38 comprises error amplifying circuit 361, input voltage average circuit 362, the first mlultiplying circuits 363 and the second mlultiplying circuit 365.The difference integrated signal of error amplifying circuit 361 output output voltage feedback signal Vfb and reference voltage Vref or title output voltage compensation signal Vcomp control so that output voltage feedback signal Vfb finally is stabilized in the reference voltage Vref value through control circuit 30.Wherein error amplifying circuit 361 has the first input end that couples output voltage feedback signal Vfb, couples the second input of reference voltage Vref and the output of output voltage compensation signal Vcomp is provided.Input voltage average circuit 362 obtains the mean value of input voltage detection signal Vi in some cycles, such as the mean value in the switch periods, and the mean value of this mean value reflection input voltage vin.The input of input voltage average circuit 362 couples input voltage detection signal Vi, and the output of input voltage average circuit 362 provides input voltage average signal Viav to the first mlultiplying circuit 363.Wherein the first input end A of the first mlultiplying circuit 363 couples the output of error amplifying circuit 361 for receiving output voltage compensation signal Vcomp, the second input B of the first mlultiplying circuit 363 couples input voltage detection signal Vi, the output that the 3rd input C of the first mlultiplying circuit 363 couples input voltage average circuit 362 is used for receiving input voltage average signal Viav, the output of the first mlultiplying circuit 363 provides average current reference signal Ith, so that Ith=(Vi*Vcomp)/Viav
2
Average current reference signal Ith is the reference signal of the input current average value of reflection expectation.The second mlultiplying circuit 365 couples the output of the first mlultiplying circuit 363, produces average current two times of reference signal Id, i.e. Id=2*Ith of being twice in average current reference signal Ith.In one embodiment, 38 of reference signal circuit for generatings comprise a mlultiplying circuit, the function of the first mlultiplying circuit 363 and the second mlultiplying circuit 365 in this mlultiplying circuit execution graph 3, namely the first input end of this mlultiplying circuit couples the output of error amplifying circuit 361 for receiving output voltage compensation signal Vcomp, the second input couples input voltage detection signal Vi, the output that the 3rd input couples input voltage average circuit 362 is used for receiving the input voltage average signal, and output directly provides average current two times of reference signal Id.In one embodiment, control circuit 30 does not comprise subtraction circuit 366, and reference signal circuit for generating 38 further couples input current peak signal Ipk, exports simultaneously two times of reference signal Id of average current and the first reference current signal Iref.
Peak current sample circuit 364 couples input current feedback signal Ii, output input current peak signal Ipk, and wherein input current peak signal Ipk is proportional to the peak current of input current Iin in a switch periods.
The input of current status testing circuit 367 couples input current feedback signal Ii, output output current state detection signal Vpd.When input current Iin greater than zero the time, current status detection signal Vpd is high level, current status detection signal Vpd is low level when input current Iin equals zero.
In a preferred embodiment, ON time control circuit 34 among Fig. 3 comprises ON time control circuit 500 as shown in Figure 5, the first turn-off time control circuit 32 comprises that as shown in Figure 7 the first turn-off time control circuit 700, the second turn-off time control circuit 33 comprises the second turn-off time control circuit 900 as shown in Figure 9.Clear for ease of showing, ON time control circuit 500, the first turn-off time control circuit 700 and the second turn-off time control circuit 900 show separately in Fig. 5,7 and 9 and will specifically describe in the paragraph below.
Fig. 4 shows pfc circuit 400 schematic diagrames according to another embodiment of the utility model.Compare pfc circuit 300, control circuit 40 in the pfc circuit 400 comprises that further the 3rd turn-off time control circuit 43 and zero current detecting circuit 47, the three turn-off time control circuits 43 produce conducting opportunity and the turn-off time length that the 3rd turn-off time control signal S3 is used for control main switch M under the critical current pattern.In the logical circuit 45 or door 451 further contain the 3rd input and couple the 3rd turn-off time control signal S3.Or door 451 generation turn-off time control signal S control main switch M optionally work in continuous current mode, discontinuous current mode and critical current pattern.
Zero current detecting circuit 47 produces zero current detection signal Vzcd, and zero current detection signal Vzcd produces high level pulse at the null trailing edge of input current Iin.The 3rd turn-off time control circuit 43 receives zero current detection signal Vzcd and the 3rd enable signal D3, produces the 3rd turn-off time control signal S3.
In a preferred embodiment, the first turn-off time control circuit 41 among Fig. 4 comprises the first turn-off time control circuit 700 among Fig. 7, the second turn-off time control circuit 42 comprises the second turn-off time control circuit 900 among Fig. 9, the 3rd turn-off time control circuit 43 comprises the 3rd turn-off time control circuit 1100 among Figure 11, and ON time control circuit 44 comprises the ON time control circuit 500 among Fig. 5.
Fig. 5 shows the ON time control circuit 500 according to the utility model one embodiment.ON time control circuit 500 comprises the first current source I1, the first capacitor C 1, the first K switch 1, subtraction circuit 54 and comparison circuit 55.The first current source I1 couples output voltage and produces the electric current that is proportional to output voltage, namely is proportional to output voltage feedback signal Vfb.The first capacitor C 1 couples the first current source I1, in the situation that the first K switch 1 is turn-offed the first current source I1 to 1 charging of the first capacitor C.The first capacitor C 1 has first end 53 and the second end 52, and wherein first end 53 couples with reference to ground GND, and the second end 52 provides the first capacitance voltage Vc1.The first K switch 1 has first end, the second end and control end, wherein the first end of the first K switch 1 couples the first end 53 of the first electric capacity, the second end of the first K switch 1 couples the second end 52 of the first electric capacity, the first K switch 1 couple logical circuit output so that the conducting when main switch M turn-offs of the first K switch 1 when main switch M conducting, turn-off.In illustrated embodiment, ON time control circuit 500 further comprises drive circuit 56, the input of drive circuit 56 couples switch controlling signal Vg, the output of drive circuit 56 couples the control end of the first K switch 1, when switch controlling signal Vg is low level, 1 conducting of drive circuit 56 controls the first K switch, when switch controlling signal Vg was high level, drive circuit 56 controls the first K switch 1 was turn-offed.Subtraction circuit 54 has first input end, the second input and output, and wherein first input end couples input voltage detection signal Vi, and the second input couples output voltage feedback signal Vfb, produces secondary signal X2, wherein secondary signal X2=Vfb-Vi.The second end 52 that the first input end of comparison circuit 55 couples the first capacitor C 1 is used for receiving the first capacitance voltage Vc1, the output that the second input of comparison circuit 55 couples subtraction circuit 54 is used for receiving secondary signal X2, the output of comparison circuit 55 is exported ON time control signal R1, couples the first input end of logical circuit.When main switch M turn-offed, switch controlling signal Vg was low level, 1 conducting of the first K switch, and the first capacitance voltage Vc1 is null value, ON time control signal R1 is low level.When main switch M conducting, the first K switch 1 is turn-offed, the first current source I1 begins 1 charging of the first capacitor C, the first capacitance voltage Vc1 rises, and as the first capacitance voltage Vc1 during greater than secondary signal X2, the ON time control signal R1 control main switch M of comparison circuit 55 output high level turn-offs, determine thus ON time length T on=" Vout-Vin)/Vout) * Tcst; wherein, Tcst=a1*C1, wherein a1 is a constant.Therefore the predetermined ON time Ton of ON time control signal R1 becomes negative correlation with input voltage vin.Ton reduces with input voltage vin and increases, and increases with input voltage vin to reduce.
Fig. 6 show according to the utility model one embodiment in the predetermined ON time Ton oscillogram 600 of steamed bun of input voltage in period of wave.Wherein hour (0, T/2), ON time Ton is maximum, and wherein T is the cycle of input voltage vin in input voltage vin.When input voltage vin is maximum (T/4), ON time Ton is minimum.The less larger ON time of input voltage correspondence, the corresponding input voltage peak value of curve top among the figure is the ON time of the steamed bun ripple of Vin1, the corresponding input voltage peak value of following curve is the ON time of the steamed bun ripple of Vin2, wherein voltage Vin2＞Vin1.
Fig. 7 shows the first turn-off time control circuit 700 according to the utility model one embodiment.The first turn-off time control circuit 700 comprises comparison circuit 70, and comparison circuit 70 has first input end, the second input and output.First input end (+) couples the first reference current signal Iref, and the second input (-) couples input current feedback signal Ii, and output is coupled to the second input of logical circuit and exports the first turn-off time control signal S1.As input current feedback signal Ii during less than the first reference current signal Iref, the first turn-off time control signal S1 is the useful signal of high level.In illustrated embodiment, first input end is in-phase end (+), and the second input is end of oppisite phase (-).In one embodiment, the first turn-off time control circuit 700 further couples the first enable signal D1, when the first enable signal D1 is high level, and 700 work of the first turn-off time control circuit.When the first enable signal D1 was low level, the first turn-off time control signal S1 kept low level.In another embodiment, the first turn-off time control circuit 700 is not controlled by the first enable signal D1 can.
Fig. 8 shows the waveform schematic diagram 800 according to the first turn-off time control circuit in the corresponding diagram 7 of the utility model one embodiment.When Iref=2Ith-Ipk greater than zero the time, main switch M works in continuous current mode, the conducting of the first turn-off time control signal S1 control main switch M.As shown in the figure, input current peak signal Ipk upgrades once in each switch periods, and is stepped.Average current reference signal Ith reference value is followed the input voltage vin wave form varies, and average current reference signal Ith also follows input voltage vin and is steamed bun ripple (sine wave of half period).In one embodiment, Ith=(Vi*Vcomp)/Viav
2
In this embodiment, can obtain the first reference current signal Iref by input current peak signal Ipk and average current reference signal Ith, make Iref=2Ith-Ipk.At time t1, the ON time control circuit sets low switch controlling signal Vg, and main switch M turn-offs, and input current feedback signal Ii descends.At time t2, input current feedback signal Ii drops to when being lower than the first reference current signal Iref, the first turn-off time control signal S1 of comparison circuit 70 output high level sets high control main switch M conducting with switch controlling signal Vg, controls thus turn-off time length T off.In one embodiment, adopt ON time control circuit shown in Figure 5, then the switch periods of main switch M is steady state value Tcst.
Fig. 9 shows the second turn-off time control circuit 900 according to the utility model one embodiment.The second turn-off time control circuit 900 couples the second enable signal D2, when the second enable signal D2 is high level, the second turn-off time control circuit 900 is controlled the conducting of main switch M under discontinuous current mode, namely control turn-off time length, when the second enable signal D2 was low level, the second turn-off time control signal S2 was low level.
The second turn-off time control circuit 900 comprises the second current source I2, the second charge switch K2, the 3rd current source I3, discharge switch K3, the second capacitor C 2 and comparison circuit 93.Wherein the second current source I2 couples and produces the electric current that is proportional to the first reference current signal Iref, wherein the electric current I 2=k* of the second current source (Iref)=k* (Ipk-2Ith), wherein k is positive number.Input current peak signal Ipk and average current reference signal Ith are referring to shown in Figure 3.In one embodiment, the second turn-off time control circuit 900 further comprises subtraction circuit, input current peak signal Ipk is deducted two times of reference signal Id of average current obtain the second reference current signal Iref2=Ipk-2Ith, make the electric current I 2=k*Iref2=k* (Ipk-2Ith) of the second current source.In another embodiment, the second turn-off time control circuit 900 and the first turn-off time control circuit share a subtraction circuit, be used for generating the first reference current signal Iref=2Ith-Ipk, and the electric current I 2 of the second current source is proportional to the inverse value-Iref of the first reference current signal.The second charge switch K2 has the control end that couples logic circuit output end, the second charge switch K2 and the second current source I2 coupled in series.The 3rd current source I3 couples and produces the electric current that is proportional to two times of reference signal Id of average current, i.e. electric current I 3=k*Id=k*2Ith, discharge switch K3 and the 3rd current source I3 coupled in series.Discharge switch K3 has the control end that is coupled to logic circuit output end.The second capacitor C 2 has first end 91 and the second end 92, and wherein the first end 91 of the second capacitor C 2 couples with reference to ground GND, and the second end 92 of the second capacitor C 2 provides the second capacitance voltage Vc2.Wherein when input current Iin greater than zero the time, when namely current status detection signal Vpd is high level, the second charge switch K2 conducting, the second current source I2 raises the second capacitance voltage Vc2 to 2 chargings of the second capacitor C.When input current Iin is zero, when namely current status detection signal Vpd is low level, discharge switch K3 conducting, 2 discharges descend the second capacitance voltage Vc2 to the 3rd current source I3 to the second capacitor C.The second end 92 that the first input end of comparison circuit 93 couples the second capacitor C 2 is used for receiving the second capacitance voltage Vc2, the second input of comparison circuit 93 couples the second reference signal Vth, comparison circuit 93 is the second capacitance voltage Vc2 and the second reference signal Vth and export the second turn-off time control signal S2 at the output of comparison circuit 93 relatively, and be coupled to the 3rd input of logical circuit.
Figure 10 shows the waveform schematic diagram 1000 according to the second turn-off time control circuit in the corresponding diagram 9 of the utility model one embodiment.When Iref=2Ith-Ipk less than zero the time, main switch works in discontinuous current mode, the conducting of the second turn-off time control signal S2 control main switch.As shown in the figure, in one-period T, at time t3 during the time t5, be in the time T1, input current Iin is detected greater than zero, and current status detection signal Vpd is high level, this moment, the second current source I2 was to 2 chargings of the second capacitor C, and the second capacitance voltage Vc2 rises; During time t5 to t6, input current Iin equals zero, and current status detection signal Vpd is low level, and this moment, the 3rd current source I3 was to 2 discharges of the second capacitor C, and the second capacitance voltage Vc2 descends.At time t6, as the second capacitance voltage Vc2 during less than the second reference signal Vth, the second turn-off time control signal S2 of comparison circuit 93 output high level sets high switch controlling signal Vg, control main switch M conducting.This moment, input current feedback signal Ii rose, and current status detection signal Vpd changes high level into, and the second current source I2 charges to the second capacitor C 2 again.Because charging current is proportional to-Iref=Ipk-2Ith, discharging current is proportional to two times of reference signal Id=2Ith of average current, so T=Ipk*T1/2Ith, wherein T is the time of one-period, T1 be in the cycle T input current greater than time of zero, Ith*T=Ipk*T1/2 then, namely the area A among Figure 10 2 equals A1, has realized well interrupted Controlled in Current Mode and Based.
Figure 11 shows the 3rd turn-off time control circuit 1100 according to the utility model one embodiment.The 3rd turn-off time control circuit 1100 comprises and door 1101.Comprise first end, the second end and output with door 1101, wherein first end couples zero current detection signal Vzcd, and the second end couples the 3rd enable signal D3, and output provides the 3rd turn-off time control signal S3.When D3 was high level, pfc circuit 400 worked in the critical current pattern, and the logical value of the 3rd turn-off time control signal S3 is consistent with zero current detection signal Vzcd.Therefore, under the critical current pattern, if zero current detection signal Vzcd is high level, main switch M is switched on.
Figure 12 shows according to the input current waveform figure under the different loads of the utility model one embodiment.Figure 120 1-1203 shows the oscillogram of input current Iin and the average electric current I av of steamed bun period of wave interior (corresponding half sine wave).Average current Iav follows input voltage, is steamed bun waveform shape.Oscillogram 1201 shows the input current Iin waveform under the case of heavy load, and wherein main switch all works under the continuous current mode (CCM) at whole steamed bun in period of wave (as shown in the figure between 0 to T/2, corresponding half sine wave period).Figure 120 2 shows the input current waveform in the intermediate part load situation, wherein main switch is at a steamed bun in period of wave, when input current Iin is larger, work in continuous current mode (CCM), as shown in the figure near cycle T/4, hour work in discontinuous current mode (DCM) at input current Iin, as shown in the figure near cycle 0 and the T/2.Figure 120 3 shows the input current waveform in the underloading situation, and wherein main switch all works in discontinuous current mode (DCM) at whole steamed bun in period of wave.Wherein underloading, heavily loaded level can be set according to actual needs.In one embodiment, the setting of underloading, heavily loaded level can be adjusted by current source and the electric capacity regulated in the ON time control circuit.
Figure 13 shows according to the frequency diagram 1300 under the different loads of the utility model one embodiment.There is shown the frequency diagram of a steamed bun in period of wave.Under case of heavy load, main switch works in continuous current mode (CCM), and frequency is steady state value.Under intermediate part load, when input current is larger, work in continuous current mode (CCM), frequency is steady state value; When input current hour, work in discontinuous current mode (DCM), changeable frequency.Wherein the frequency under the discontinuous current mode is less than the frequency under the continuous current mode, and input current is less, and frequency is lower.Main switch works in discontinuous current mode (DCM) under the underloading condition, and its frequency is less than the frequency under the continuous current mode.
Figure 14 shows the waveform schematic diagram 1400 according to pfc circuit in the corresponding diagram 4 of the utility model one embodiment.There is shown under intermediate part load, main switch works in discontinuous current mode (DCM) when input current is relatively lower, work in continuous current mode (CCM) when input current is higher.Main switch also partly works in critical current pattern (BCM).There is shown input current feedback signal Ii, input current peak signal Ipk, average current reference signal Ith, the first reference current signal Iref, the first turn-off time control signal S1, the second turn-off time control signal S2, the second capacitance voltage Vc2, the 3rd turn-off time control signal S3 and switch controlling signal Vg.Wherein under continuous current mode (CCM), switch controlling signal Vg conducting when the first turn-off time, control signal S1 was high level is turn-offed after predetermined ON time.Under discontinuous current mode (DCM), switch controlling signal Vg conducting when the second turn-off time, control signal S2 was high level is turn-offed after predetermined ON time.According to ON time control circuit 500 shown in Figure 5, the predetermined ON time of ON time control signal R1 is shorter under continuous current mode, longer under discontinuous current mode, the corresponding well low characteristic of frequency under the frequency ratio continuous current mode under the discontinuous current mode has improved the switch efficiency under the discontinuous current mode.Under the critical current pattern, switch controlling signal Vg conducting when the 3rd turn-off time, control signal S3 was high level is turn-offed after predetermined ON time.
In one embodiment, when the first reference current signal approximates zero, namely-during Iz＜2Ith-Ipk＜Iz, pfc circuit works in the critical current pattern, when the first reference current signal greater than zero, when being 2Ith-Ipk＞Iz, pfc circuit works in continuous current mode, when the first reference current signal less than zero, namely during Ipk-2Ith＞Iz, pfc circuit works in discontinuous current mode, and wherein reference value Iz approximates zero less positive number.Particularly, when the first reference current signal greater than zero, namely when the twice of input current average current reference signal during greater than the input current peak signal, during Iref=2Ith-Ipk＞Iz, main switch M works in continuous current mode (CCM), and this moment, the second turn-off time control signal S2 and the 3rd turn-off time control signal S3 were low level.When input current feedback signal Ii dropped to the first reference current signal Iref, the first turn-off time control signal S1 was high level, and switch controlling signal Vg raises, main switch M conducting, and input current feedback signal Ii raises.After the predetermined ON time of ON time control signal R1, switch controlling signal Vg descends, and main switch M turn-offs, and input current feedback signal Ii descends, the beginning next cycle.When the first reference current signal less than zero, be that the twice of input current average current reference signal is during less than the input current peak signal, be Iref=2Ith-Ipk＜-during Iz, main switch M is operated in discontinuous current mode (DCM), and this moment, the first turn-off time control signal S1 and the 3rd turn-off time control signal S3 were low level.The second capacitance voltage Vc2 is in input current feedback signal Ii charging greater than zero time, discharge when input current feedback signal Ii equals zero, when the second capacitance voltage Vc2 drops to a reference voltage, the second turn-off time control signal S2 presents high level pulse, switch controlling signal Vg raises, main switch M conducting, input current feedback signal Ii raises simultaneously.After the predetermined ON time of ON time control signal R1, switch controlling signal Vg descends, and main switch M turn-offs, and input current feedback signal Ii descends simultaneously, the beginning next cycle.When the first reference current signal approximates zero, namely-Iz＜2Ith-Ipk＜during Iz, main switch M is operated in critical current pattern (BCM), and this moment, the first turn-off time control signal S1 and the second turn-off time control signal S2 were low level.In another embodiment, this moment the first turn-off time control signal S1 and the second turn-off time control signal S2 conductively-closed.When electric current equalled zero, the 3rd turn-off time control signal S3 was high level, and switch controlling signal Vg raises, main switch M conducting.After the predetermined ON time of ON time control signal R1, switch controlling signal Vg descends, and main switch M turn-offs, the beginning next cycle.
From the oscillogram of Figure 14, can see, the average value signal Ith of input current is steamed bun waveform shape, realize PFC control, simultaneously be lower than frequency under the continuous current mode (CCM) in the frequency under the discontinuous current mode (DCM), optimized the switch efficiency under the low carrier strip spare.Simultaneously, the circuit among above-mentioned a plurality of embodiment adopts analog circuit, and system cost is lower.
Should be known in that the logical value in the specification can adopt opposite logic level.For example, switch controlling signal Vg signal can impel main switch M conducting when high level, also can impel main switch M conducting when low level.
Some above-mentioned specific embodiments only describe the utility model in an exemplary fashion, and these embodiment are not fully detailed, and are not used in the scope of the present utility model that limits.It all is possible changing and revise for disclosed embodiment, the selectivity embodiment that other are feasible and can be understood by those skilled in the art the equivalent variations of element among the embodiment.Other variations of embodiment disclosed in the utility model and modification do not exceed the protection range of spirit of the present utility model and claim restriction.
Claims (15)
1. a power factor correction (PFC) circuit is characterized in that, comprising:
Switching circuit comprises main switch, and switching circuit has input and output, and wherein input receives input voltage, and output provides output voltage;
The ON time control circuit, the shutoff that produces ON time control signal control main switch;
The first turn-off time control circuit produces the first turn-off time control signal;
The second turn-off time control circuit produces the second turn-off time control signal; And
Logical circuit receives ON time control signal, the first turn-off time control signal and the second turn-off time control signal, and output control signal control main switch optionally works in continuous current mode or discontinuous current mode; Wherein
Under continuous current mode, the conducting of the first turn-off time control signal control main switch;
Under discontinuous current mode, the conducting of the second turn-off time control signal control main switch.
2. pfc circuit as claimed in claim 1, it is characterized in that, further comprise the 3rd turn-off time control circuit, the 3rd turn-off time control circuit produces the 3rd turn-off time control signal, wherein logical circuit further receives the 3rd turn-off time control signal and controls main switch and optionally works in the critical current pattern, the wherein conducting of the 3rd turn-off time control signal control main switch under the critical current pattern.
3. pfc circuit as claimed in claim 1 is characterized in that, the main switch frequency under the discontinuous current mode is lower than the main switch frequency under the continuous current mode.
4. pfc circuit as claimed in claim 1 is characterized in that, switching circuit comprises boost conversion circuit.
5. pfc circuit as claimed in claim 1, it is characterized in that, described ON time control circuit has first input end, the second input and output, wherein first input end couples the input voltage detection signal that characterizes input voltage, the second input couples the output voltage feedback signal that characterizes output voltage, output output ON time control signal.
6. pfc circuit as claimed in claim 5 is characterized in that, described ON time control circuit comprises:
The first current source produces the electric current that is proportional to output voltage;
The first electric capacity couples the first current source, and the first electric capacity has first end and the second end, and wherein first end couples with reference to ground, and the second end provides the first capacitance voltage;
The first switch, have first end, the second end and control end, wherein the first end of the first switch couples the first end of the first electric capacity, the second end of the first switch couples the second end of the first electric capacity, conducting when the first switch turn-offs at main switch, the first switch turn-offs when the main switch conducting, and when the first switch turn-offed, the first current source was to the first capacitor charging;
Subtraction circuit couples input voltage detection signal and output voltage feedback signal, produces secondary signal;
Comparison circuit has first input end, the second input and output, and wherein the first input end of comparison circuit receives the first capacitance voltage, and the second input of comparison circuit receives secondary signal, the output output ON time control signal of comparison circuit.
7. pfc circuit as claimed in claim 1, it is characterized in that, the first turn-off time control circuit comprises comparison circuit, comparison circuit has first input end, the second input and output, wherein first input end couples the first reference current signal, the second input couples the input current feedback signal that characterizes the input current be associated with input voltage, and comparison circuit comparison the first reference current signal and input current feedback signal are also exported the first turn-off time control signal at output.
8. pfc circuit as claimed in claim 7 is characterized in that, the second turn-off time control circuit comprises:
The second current source produces the electric current that is proportional to the first reference current signal;
The second charge switch, and the series connection of the second current source;
The 3rd current source produces the electric current that is proportional to two times of reference signals of average current, and wherein two times of reference signals of average current characterize the twice of input current average expected volume;
Discharge switch, and the series connection of the 3rd current source;
The second electric capacity has first end and the second end, and wherein first end couples with reference to ground, and the second end provides the second capacitance voltage; Wherein
When input current greater than zero the time, the second charge switch conducting, the second current source raises the second capacitance voltage to the second capacitor charging;
When input current is zero, the 3rd charging open pipe conducting, the 3rd current source reduces the second capacitance voltage to the second capacitor discharge; And
Comparison circuit, have first input end, the second input and output, wherein first input end couples the second capacitance voltage, the second input couples the second reference signal, and comparison circuit comparison the second capacitance voltage and the second reference signal are also exported the second turn-off time control signal at the output of comparison circuit.
9. pfc circuit as claimed in claim 1 is characterized in that, logical circuit comprises:
Pattern decision circuit, export the first enable signal and the second enable signal based on the two times of reference signals of average current and the input current peak signal that characterize input current average expected volume twice, wherein the first enable signal couples the first turn-off time control circuit, the second enable signal couples the second turn-off time control circuit, and pattern decision circuit optionally suppresses the first turn-off time control circuit or the second turn-off time control circuit;
Or door, have first end, the second end and output, wherein first end receives the first turn-off time control signal, and the second termination is received the second turn-off time control signal; And
Latch cicuit has set end, reset terminal and output, and wherein the set end couples or the output of door, and reset terminal receives the ON time control signal, the turn-on and turn-off of output control main switch.
10. pfc circuit as claimed in claim 1 is characterized in that, further comprises:
The reference signal circuit for generating produces two times of reference signals of average current based on input voltage detection signal and output voltage feedback signal;
The peak current sample circuit couples the input current feedback signal, output input current peak signal; And
Subtraction circuit couples two times of reference signals of average current and input current peak signal, exports the first reference current signal.
11. pfc circuit as claimed in claim 10 is characterized in that, the reference signal circuit for generating comprises:
Error amplifying circuit has first input end, the second input and output, and wherein first input end couples output voltage feedback signal, and the second input couples reference voltage, and output provides the output voltage compensation signal;
The input voltage average circuit has input and output, and wherein input couples the input voltage detection signal, and output provides the input voltage average signal; And
Mlultiplying circuit, have first input end, the second input, the 3rd input and output, wherein first input end couples the output of error amplifying circuit for receiving the output voltage compensation signal, the second input couples the input voltage detection signal, the output that the 3rd input couples the input voltage average circuit is used for receiving the input voltage average signal, and output provides average current two times of reference signals.
12. a PFC control circuit is used for the main switch between input and the output of being coupled to of control switch circuit, wherein input has input voltage and input current, and output has output voltage, it is characterized in that, the PFC control circuit comprises:
The ON time control circuit produces the ON time control signal based on input voltage and output voltage, the shutoff of control main switch;
The first turn-off time control circuit produces the first turn-off time control signal;
The second turn-off time control circuit produces the second turn-off time control signal; And
Logical circuit, the control main switch optionally works in continuous current mode or discontinuous current mode; Wherein
Under continuous current mode, the conducting of the first turn-off time control signal control main switch;
Under discontinuous current mode, the conducting of the second turn-off time control signal control main switch.
13. control circuit as claimed in claim 12, it is characterized in that, the first turn-off time control circuit comprises comparison circuit, comparison circuit compares input current feedback signal and the first reference current signal, when input current feedback signal during less than the first reference current signal, the conducting of the output of comparison circuit control main switch.
14. control circuit as claimed in claim 12 is characterized in that, the second turn-off time control circuit comprises:
The second current source is proportional to the first reference current signal, and wherein the first reference current signal is the difference signal of two times of reference signals of average current and input current peak signal;
The 3rd current source is proportional to two times of reference signals of average current; And
The second electric capacity, have first end and the second end, wherein first end couples with reference to ground, the second end provides the second capacitance voltage, wherein to the second capacitor charging the second capacitance voltage is raise when input current second current source greater than zero time, the 3rd current source reduces the second capacitance voltage to the second capacitor discharge when input current is 0; And
Comparison circuit compares the second capacitance voltage and the second reference signal and exports the second turn-off time control signal.
15. control circuit as claimed in claim 12 is characterized in that, further comprises:
Error amplifying circuit has first input end, the second input and output, and wherein first input end couples output voltage feedback signal, and the second input couples reference voltage, and output provides the output voltage compensation signal;
The input voltage average circuit has input and output, and wherein input couples the input voltage detection signal, and output provides the input voltage average signal;
Mlultiplying circuit, have first input end, the second input, the 3rd input and output, wherein first input end couples the output of error amplifying circuit for receiving the output voltage compensation signal, the second input couples the input voltage detection signal, the output that the 3rd input couples the input voltage average circuit is used for receiving the input voltage average signal, and output provides average current two times of reference signals;
The peak current sample circuit couples the input current feedback signal, output input current peak signal; And
Subtraction circuit couples two times of reference signals of average current and input current peak signal, exports the first reference current signal.
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| CN103151912A (en) * | 2013-03-21 | 2013-06-12 | 成都芯源系统有限公司 | Power factor correction circuit and control method thereof |
| CN104779785A (en) * | 2014-01-11 | 2015-07-15 | 亚荣源科技（深圳）有限公司 | Control circuit module of power factor correction converter |
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| CN113241941A (en) * | 2020-12-31 | 2021-08-10 | 上海晶丰明源半导体股份有限公司 | Switching power supply control circuit, system and control method |
| CN113241941B (en) * | 2020-12-31 | 2022-09-02 | 上海晶丰明源半导体股份有限公司 | Switching power supply control circuit, system and control method |
| CN112953219A (en) * | 2021-01-22 | 2021-06-11 | 昂宝电子（上海）有限公司 | Boost control circuit |
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