CN203204602U - Graphics processing unit-based wiring system - Google Patents
Graphics processing unit-based wiring system Download PDFInfo
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- CN203204602U CN203204602U CN 201320178887 CN201320178887U CN203204602U CN 203204602 U CN203204602 U CN 203204602U CN 201320178887 CN201320178887 CN 201320178887 CN 201320178887 U CN201320178887 U CN 201320178887U CN 203204602 U CN203204602 U CN 203204602U
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Abstract
The utility model relates to an integrated circuit design, and discloses a graphics processing unit-based wiring system. The wiring system comprises a central processing unit and a plurality of graphics processing units, wherein the graphics processing units are electrically connected in parallel with the central processing unit; the central processing unit is used for outputting wiring information to the graphics processing units; and the graphics processing units are used for outputting wiring results obtained by performing parallel wiring to the central processing unit according to the wiring information input by the central processing unit. The hyper parallel processing capability of the graphics processing units is used for wiring, so that the wiring time is greatly shortened, the wiring speed is more than one magnitude order higher than the conventional wiring speed, and the result performance of the whole system is maintained.
Description
Technical field
The utility model relates to the integrated circuit (IC) design field, particularly the wiring system of integrated circuit.
Background technology
In the special IC wiring system, and in the programmable logic device (PLD) wiring system, because need device count to be processed can be up to up to ten million, a part the most consuming time in the normally whole integrated circuit physical Design flow process that therefore connects up.In actual applications, wiring system usually will just can be finished with several days time the wiring of millions of gauzes.In at present all wiring techniques, the circuit that the line speed of single gauze is relevant, more large-scale, more complicated with the size of the interconnection resource figure of integrated circuit (IC) chip, the cloth linear velocity is slower.
In the corded arrangement of integrated circuit, what the most extensively be employed is Li Shi Maze Routing system (Lee ' s Maze) and based on the A* wiring system of Li Shi method improvement, and under the prerequisite of not losing optimum solution, A* is the fastest wiring method known today.But the present inventor finds, the A* method uses Priority Queues that the expense of node is managed, this is so that the cloth line search is a series process, final wiring time is not only relevant with the search volume that comprises starting point, terminal point (three-dimensional) size, and is also relevant with the error of the actual cost of node and expect cost in the search procedure.
In addition, the serial processing characteristic that current integrated circuit wiring method all is based on the computing machine CPU (central processing unit) designs, CPU (central processing unit) is to process the hardware configuration of elementary arithmetic, logic and input and output in the computing machine, and it is the most crucial unit of current computer system.Although up-to-date CPU (central processing unit) has the characteristic of multithreading, design the wiring method of a multithreading and be not easy.The various multithreading wiring methods of now knowing all are to carry out parallel computation at different circuit gauzes, and the wiring of same gauze still gives same computer processing unit to carry out serial processing.Have 1000 gauzes to need wiring such as working as, and CPU (central processing unit) can be opened 8 threads simultaneously, so at one time, each thread is still only processed the single line net, and always having 8 gauzes can be connected up simultaneously.For every gauze, its cloth linear velocity is not accelerated.And because the ability limited of the parallel computation of CPU (central processing unit), so the effect that integrated circuit wiring accelerates with multithreading also is limited.
The utility model content
The purpose of this utility model is to provide a kind of wiring system based on Graphics Processing Unit, utilize the super parallel processing capability of Graphics Processing Unit to connect up, greatly shortened wiring time, acquisition is than the fast cloth linear velocity more than the magnitude of traditional wiring, and do not sacrifice the as a result performance of whole system.
For solving the problems of the technologies described above, embodiment of the present utility model discloses a kind of wiring system based on Graphics Processing Unit, comprises CPU (central processing unit) and a plurality of Graphics Processing Unit, and described Graphics Processing Unit is electrically connected with described CPU (central processing unit) is parallel;
Described CPU (central processing unit) is used for to described Graphics Processing Unit output wiring information;
Described Graphics Processing Unit is used for carrying out the wiring result that parallel routing obtains according to the wiring information of described CPU (central processing unit) input and exports to described CPU (central processing unit).
The utility model embodiment compared with prior art, the key distinction and effect thereof are:
Wiring system of the present utility model comprises CPU (central processing unit) and a plurality of Graphics Processing Unit, these Graphics Processing Unit are electrically connected with above-mentioned CPU (central processing unit) is parallel, wherein above-mentioned CPU (central processing unit) is used for to above-mentioned Graphics Processing Unit output wiring information, these Graphics Processing Unit are used for carrying out the wiring result that parallel routing obtains according to the wiring information of above-mentioned CPU (central processing unit) input and export to this CPU (central processing unit), connect up by the super parallel processing capability that utilizes Graphics Processing Unit, greatly shortened wiring time, acquisition is than the fast cloth linear velocity more than the magnitude of traditional wiring, and do not sacrifice the as a result performance of whole system.
Description of drawings
Fig. 1 is the schematic flow sheet of a kind of wiring method based on Graphics Processing Unit in the utility model the first embodiment;
Fig. 2 is a kind of schematic flow sheet based on the wiring step in the wiring method of Graphics Processing Unit in the utility model the first embodiment;
Fig. 3 is the parallel search method schematic diagram of Graphics Processing Unit in the utility model the first embodiment;
Fig. 4 is the structural representation of a kind of wiring system based on Graphics Processing Unit in the utility model the 3rd embodiment;
Fig. 5 is the structural representation of a kind of wiring system based on Graphics Processing Unit in the utility model the 3rd embodiment;
Fig. 6 is a kind of structural representation based on the super parallel routing device in the wiring system of Graphics Processing Unit in the utility model the 3rd embodiment.
Embodiment
In the following description, in order to make the reader understand the application better many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs with based on many variations and the modification of following each embodiment, also can realize each claim of the application technical scheme required for protection.
For making the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing embodiment of the present utility model is described in further detail.
The utility model the first embodiment relates to a kind of wiring method based on Graphics Processing Unit.Fig. 1 is that this is based on the schematic flow sheet of the wiring method of Graphics Processing Unit.As shown in Figure 1, should may further comprise the steps based on the wiring method of Graphics Processing Unit:
Input information step input logic link information.
In the present embodiment, this logical connection information comprises circuit meshwork list, technological parameter and device position information etc.Be appreciated that in other embodiments of the present utility model, can also comprise the information of other wiring needs, be not limited to above-mentioned information.
Loose routing resource map constitution step global routing cell is according to this logical connection information structure loose routing resource map.
In special IC and programmable logic device (PLD) circuit, according to the technological parameter that integrated circuit is produced, different zones has different wiring capacity.With the wiring calculation of capacity of All Ranges in the circuit out, and the figure that constructs according to the concrete physical location in zone is called interconnection resource figure, in the figure, node is different wiring zone, the limit is the interconnection resource that connects the various wirings zone, the expense on limit is the quantity of interconnection resource, and the corresponding expense in the limit that interconnection resource is few is higher.
The super parallel routing device of loose routing step connects up according to this logical connection information and this loose routing resource map and exports the wiring result, wherein should comprise Graphics Processing Unit by super parallel routing device, the state that above-mentioned Graphics Processing Unit is monitored each node in this loose routing resource map simultaneously carries out the cloth line search, connects thereby finish wiring.
According to the logic netlist of circuit, from the interconnection resource figure node at the output port place of a certain device, by the limit of a series of interconnection resource figure, the path that arrives the node at other device input port places that the net table formulates is called as integrated circuit wiring.The physical routing scheme that realizes logic netlist may have a lot, and the expense summation on the wiring limit that relates in each scheme is decided to be the expense of this scheme.In all schemes, the scheme of expense minimum is the optimum wiring of this logic gauze.
Detailed routing resource map constitution step detailed routing unit is constructed detailed routing resource map according to this logical connection information on this loose routing resource map basis through wiring;
This super parallel routing device of detailed routing step connects up according to this logical connection information and this detailed routing resource map and exports the wiring result, wherein should comprise Graphics Processing Unit by super parallel routing device, the state that above-mentioned Graphics Processing Unit is monitored each node in this detailed routing resource map simultaneously carries out the cloth line search, connects thereby finish wiring;
Wherein, the difference of loose routing and detailed routing is the precision of corresponding wiring line resource map: the node of loose routing resource map is the various wirings zone in the integrated circuit, and the limit is interregional cut-off rule, and the expense on limit is decided by the interconnection resource number between the zone; The node of detailed routing resource map is prefabricated line rail and interface unit in the wiring lattice point of pre-planning of integrated circuit or the programmable logic device (PLD), the limit is the metal connecting line of wiring between the lattice point, and the expense on limit is the association attributes (such as electric conductivity etc.) of this metal connecting line.Loose routing is connected with detailed routing and is called identical super parallel routing device and carry out gauze and connect.Loose routing connects up speed based on the information of simplifying; Detailed routing can be accelerated its cloth linear velocity greatly at the basic enterprising row wiring of loose routing.And for the large gauze of the overall situation in the super large integrated circuit, because we are divided into loose routing and detailed routing with wiring method, therefore the large gauzes of these overall situations are divided for sectional little gauze, thereby existed hardly the overlay area of a gauze can not completely import the situation of Graphics Processing Unit internal memory into.But as the emergency plan of system, when the Graphics Processing Unit low memory occurring and treat the situation of cloth gauze with covering, we just use CPU (central processing unit) to connect this gauze.
Be appreciated that in other embodiments of the present utility model, can not be divided into loose routing and detailed routing, also can realize scheme of the present utility model.
The above-mentioned detailed routing resource map of wiring is finished in the output of output step.
Specifically:
As shown in Figure 2, above-mentioned wiring step may further comprise the steps:
Whether the gauze that the above-mentioned super parallel routing device of step a checks this interconnection resource figure cloth and without the wiring conflict, if, then finish wiring, if not, then determine to treat the cloth gauze.This treats the gauze that the cloth gauze comprises cloth gauze not and the wiring conflict is arranged, and this super parallel routing device is with the rerouting of taking out stitches of the gauze of the Xiang Yingyou wiring conflict determined.
The wiring zone copy that the cloth gauze covers for the treatment of that the above-mentioned super parallel routing device of step b will be determined enters in the above-mentioned Graphics Processing Unit.
In the present embodiment, preferably, the gauze overlay area is a rectangular area, can cover all end points of gauze.Be appreciated that in other embodiments of the present utility model, can adopt according to actual conditions the gauze overlay area of other shapes.
The state that the above-mentioned Graphics Processing Unit of step c is monitored each node in this wiring zone simultaneously carries out the cloth line search, connects thereby finish wiring.
The above-mentioned super parallel routing device output wiring result of steps d also upgrades this interconnection resource figure, and the new gauze that is about to above-mentioned wiring zone is replaced former gauze, returns step a.
In step c, above-mentioned Graphics Processing Unit is monitored each node state in the wiring zone simultaneously, and processes synchronously.
Whether the gauze that checks above-mentioned interconnection resource figure before wiring cloth and without the wiring conflict, and the gauze that will need to connect up copies in the above-mentioned Graphics Processing Unit, has further improved the processing speed of Graphics Processing Unit.
Be appreciated that before wiring directly whole gauze to be copied in the above-mentioned Graphics Processing Unit not on inspection, also can realize the technical solution of the utility model.
When initial, the expense that above-mentioned Graphics Processing Unit arranges start node is 0, node state is the search rim condition, all the other node expenses is set is search condition not for infinitely great, node state.
When the state of node is the search rim condition, above-mentioned Graphics Processing Unit is calculated the neighborhood of nodes expense of this node, if the neighborhood of nodes expense of calculating is less than former neighborhood of nodes expense, then upgrade this neighborhood of nodes expense and this neighborhood of nodes state and be set to search for rim condition, after handling this node, this node state is set to search for completion status.
Above-mentioned Graphics Processing Unit re-treatment node state is the node of search rim condition, until find goal node.
By on can see, the core of the super parallel processor that the utility model proposes is based on the super parallel search wiring method of Graphics Processing Unit, in a preferred example, this super parallel search wiring method is described below with pseudo-language:
Algorithm?SUPER-ROUTER(B,s,t,P)
input:B,s,t
output:P
begin
cost[s]=0;
wave_front[s]=TRUE;
while?visited[t]=FALSE?do
The cost of the neighborhood of nodes of the node of synchronous each wave_front=TRUE of calculating
Synchronous node set visited=TRUE with all wave_front=TRUE
Synchronously all had the node of new cost, with their state set wave_front=TRUE
RETRACE(L,P);
end
In this super parallel search method, the large quantum thread that utilizes numerous Graphics Processing Unit and each unit to tell removes to monitor the state of each node.When the state of a node is wave_front=TRUE(search rim condition) time, thread that should node is just calculated next time the expense of the neighborhood of nodes of this node when processing synchronously, if this expense is less (except start node than the expense of former neighborhood of nodes, the initial cost of all nodes is infinitely great), the expense of this neighborhood of nodes will be updated so, and the state of this neighborhood of nodes can be set wave_front=TRUE(search rim condition).Node is living through wave_front=TRUE(search rim condition one time) expansion after, can become visited=TRUE state (search completion status).The legend of this super parallel search method such as Fig. 3, wherein the A node is the search edge nodes of expanding for the first time, and the B node is the search edge nodes of expanding for the second time, and the C node is the search edge nodes of expanding for the third time.In the drawings, from the off, four new nodes that are labeled as A have been searched for regard to synchronization of access for the first time; 8 the new nodes that are marked as B of for the second time having searched for synchronization of access; For the third time search has found to comprise other new nodes of terminal point.The time of whole wiring method is relevant with the path from origin-to-destination, and irrelevant with the size of wiring space.
Can find out from above discussion, the processing power of super parallel search algorithm is directly relevant with the parallel ability of current Graphics Processing Unit.Current graphic process unit contains 3072 Graphics Processing Unit, and each processing unit can move up to a hundred threads simultaneously, and this is so that graphic process unit can be carried out the simple operation of 100,000 magnitudes simultaneously.If our interconnection resource figure has the nodal point number above this amount, we can allow a plurality of nodes of thread monitor so, because when expanding each time, most of nodes can tangible expansion demand, and therefore the validity of super parallel search algorithm can be not influenced.
The utility model utilizes the super parallel processing capability of Graphics Processing Unit, Priority Queues most crucial in traditional integrated circuit wiring method is removed, the state that changes to monitor simultaneously each node among the interconnection resource figure carries out the cloth line search, by this way, the time of wiring is only relevant with the length of routing path, irrelevant with the size of wiring space, and can use hundreds of processing unit to connect up simultaneously to single line, it is far away from current any other known method that the cloth linear velocity is wanted, and do not sacrifice the as a result performance of whole system.In addition, whole wiring is divided into loose routing and detailed routing, has further accelerated whole cloth linear velocity and made the internal memory of Graphics Processing Unit be enough to the to load application needs of current VLSI (very large scale integrated circuit).
The utility model the second embodiment relates to a kind of wiring method based on Graphics Processing Unit.
The second embodiment improves on the basis of the first embodiment, main improvements are that the data in the above-mentioned Graphics Processing Unit internal memory are that of former interconnection resource diagram data simplifies subset, wherein only comprise node numbering and limit expense, can further improve the processing speed of Graphics Processing Unit, specifically:
Rear copy is simplified in the above-mentioned wiring zone that covers until the cloth gauze enter above-mentioned Graphics Processing Unit, the wiring zone after simplifying is comprised of the cost information on node numbering and limit.
Because the internal memory of Graphics Processing Unit lacks than CPU (central processing unit) usually, so the wiring diagram that we import Graphics Processing Unit into includes only the numbering of node and the cost information on limit, and less resource map information also helps to accelerate the speed of memory copying.Be appreciated that also the wiring zone copy of not simplifying to be entered in the Graphics Processing Unit to process, also can realize the technical solution of the utility model.
Each method embodiment of the present utility model all can be realized in modes such as software, hardware, firmwares.No matter the utility model is to realize with software, hardware or firmware mode, instruction code can be stored in the storer of computer-accessible of any type (for example permanent or revisable, volatibility or non-volatile, solid-state or non-solid-state, fixing or removable medium etc.).Equally, storer can for example be programmable logic array (Programmable Array Logic, be called for short " PAL "), random access memory (Random Access Memory, be called for short " RAM "), programmable read only memory (Programmable Read Only Memory, be called for short " PROM "), ROM (read-only memory) (Read-Only Memory, be called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, be called for short " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc is called for short " DVD ") etc.
The utility model the 3rd embodiment relates to a kind of wiring system based on Graphics Processing Unit.Fig. 4, Fig. 5 are that this is based on the structural representation of the wiring system of Graphics Processing Unit.As shown in Figure 4, should comprise CPU (central processing unit) and a plurality of Graphics Processing Unit based on the wiring system of Graphics Processing Unit, these Graphics Processing Unit are electrically connected with this CPU (central processing unit) is parallel;
Above-mentioned CPU (central processing unit) is used for to above-mentioned Graphics Processing Unit output wiring information;
Above-mentioned Graphics Processing Unit is used for carrying out the wiring result that parallel routing obtains according to the wiring information of above-mentioned CPU (central processing unit) input and exports to above-mentioned CPU (central processing unit).
Specifically, as shown in Figure 5, the wiring system that above-mentioned CPU (central processing unit) and above-mentioned Graphics Processing Unit form comprises:
Input block is used for the input logic link information.
In the present embodiment, this logical connection information comprises circuit meshwork list, technological parameter and device position information etc.Be appreciated that in other embodiments of the present utility model, can also comprise the information of other wiring needs, be not limited to above-mentioned information.
Global routing cell is for constructing loose routing resource map according to this logical connection information and calling super parallel routing device and connect up;
The detailed routing unit is used for constructing detailed routing resource map through this loose routing resource map basis of wiring and calling this super parallel routing device and connect up according to this logical connection information;
Output unit is used for the above-mentioned detailed routing resource map that wiring is finished in output; And
Super parallel routing device, be used for connecting up and exporting the wiring result according to this logical connection information and above-mentioned interconnection resource figure, wherein should comprise Graphics Processing Unit by super parallel routing device, the state that above-mentioned Graphics Processing Unit is monitored each node among the above-mentioned interconnection resource figure simultaneously carries out the cloth line search, connects thereby finish wiring.
Be appreciated that in other embodiments of the present utility model, can not be divided into global routing cell and detailed routing unit, also can realize scheme of the present utility model.
Specifically:
As shown in Figure 6, above-mentioned super parallel routing device comprises:
Whether inspection unit, the gauze that be used for to check this interconnection resource figure cloth and without the wiring conflict.
Determining unit if be used for not cloth or the wiring conflict is arranged of this gauze, then determines to treat the cloth gauze.
Copy cell, the wiring zone copy that the cloth gauze covers for the treatment of that is used for determining enters above-mentioned Graphics Processing Unit.
Graphics Processing Unit is used for monitoring simultaneously this state for the treatment of each node of wiring zone that the cloth gauze covers and carries out the cloth line search, connects thereby finish wiring.
The output updating block is used for output wiring result and upgrades this interconnection resource figure.
Whether the gauze that checks above-mentioned interconnection resource figure before wiring cloth and without the wiring conflict, and the gauze that will need to connect up copies in the above-mentioned Graphics Processing Unit, further improves the processing speed of Graphics Processing Unit.
Be appreciated that before wiring directly whole gauze to be copied in the above-mentioned Graphics Processing Unit not on inspection, also can realize the technical solution of the utility model.
Wherein above-mentioned Graphics Processing Unit is monitored each node state simultaneously, and processes synchronously.
When initial, the expense that above-mentioned Graphics Processing Unit arranges start node is 0, node state is the search rim condition, all the other node expenses is set is search condition not for infinitely great, node state.
When the state of node is the search rim condition, Graphics Processing Unit is calculated the neighborhood of nodes expense of this node, if the neighborhood of nodes expense of calculating is less than former neighborhood of nodes expense, then upgrade this neighborhood of nodes expense and this neighborhood of nodes state and be set to search for rim condition, after handling this node, this node state is set to search for completion status.
Graphics Processing Unit re-treatment node state is the node of search rim condition, until find goal node.
The utility model utilizes the super parallel processing capability of Graphics Processing Unit, Priority Queues most crucial in traditional integrated circuit wiring method is removed, the state that changes to monitor simultaneously each node among the interconnection resource figure carries out the cloth line search, by this way, the time of wiring is only relevant with the length of routing path, irrelevant with the size of wiring space, and can use hundreds of processing unit to connect up simultaneously to single line, it is far away from current any other known method that the cloth linear velocity is wanted, and do not sacrifice the as a result performance of whole system; And whole wiring is divided into loose routing and detailed routing, has further accelerated whole cloth linear velocity and made the internal memory of Graphics Processing Unit be enough to the to load application needs of current VLSI (very large scale integrated circuit).
The first embodiment is the method embodiment corresponding with present embodiment, present embodiment can with the enforcement of working in coordination of the first embodiment.The correlation technique details of mentioning in the first embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in the present embodiment also can be applicable in the first embodiment.
The utility model the 4th embodiment relates to a kind of wiring system based on Graphics Processing Unit.
The 4th embodiment improves on the basis of the 3rd embodiment, main improvements are that the data in the above-mentioned Graphics Processing Unit internal memory are that of former interconnection resource diagram data simplifies subset, wherein only comprise node numbering and limit expense, further improve the processing speed of Graphics Processing Unit, specifically:
In above-mentioned super parallel routing device, add and simplify the unit, be used for simplifying above-mentioned wiring zone for the treatment of that the cloth gauze covers, wiring zone after simplifying is comprised of the cost information on node numbering and limit, and the wiring zone copy of above-mentioned copy cell after this is simplified enters in the above-mentioned Graphics Processing Unit.
Be appreciated that also the wiring zone copy of not simplifying to be entered in the Graphics Processing Unit to process, also can realize the technical solution of the utility model.
The second embodiment is the method embodiment corresponding with present embodiment, present embodiment can with the enforcement of working in coordination of the second embodiment.The correlation technique details of mentioning in the second embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in the present embodiment also can be applicable in the second embodiment.
The in recent years widespread use of Graphics Processing Unit is so that a lot of problem can go to solve with a kind of new angle.Compare with traditional CPU (central processing unit), Graphics Processing Unit has powerful synchronous processing capacity, can have simultaneously hundreds of microprocessor to perform mathematical calculations.The utility model utilizes the super parallel processing capability of current Graphics Processing Unit, wiring method and the system of redesign integrated circuit, accomplish also can connect up simultaneously with hundreds of processing unit to single line, greatly improve the cloth linear velocity of integrated circuit, programmable logic device (PLD).
Need to prove, each unit of mentioning in each equipment embodiment of the utility model all is logical block, physically, a logical block can be a physical location, it also can be the part of a physical location, can also realize with the combination of a plurality of physical locations, the physics realization mode of these logical blocks itself is not most important, and the combination of the function that these logical blocks realize is only the key of the technical matters that solution the utility model proposes.In addition, for outstanding innovation part of the present utility model, above-mentioned each the equipment embodiment of the utility model will concern with the technical matters that solution the utility model proposes not too not close unit introducing, and this does not show that there is not other unit in the said equipment embodiment.
Also need to prove, in the claim and instructions of this patent, relational terms such as the first and second grades only is used for an entity or operation are separated with another entity or operational zone, and not necessarily requires or hint and have the relation of any this reality or sequentially between these entities or the operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby not only comprise those key elements so that comprise process, method, article or the equipment of a series of key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.In the situation that not more restrictions, the key element that " comprises " and limit by statement, and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
Although by reference some preferred implementation of the present utility model, the utility model is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and do not depart from spirit and scope of the present utility model.
Claims (1)
1. the wiring system based on Graphics Processing Unit is characterized in that, comprises CPU (central processing unit) and a plurality of Graphics Processing Unit, and described Graphics Processing Unit is electrically connected with described CPU (central processing unit) is parallel;
Described CPU (central processing unit) is used for to described Graphics Processing Unit output wiring information;
Described Graphics Processing Unit is used for carrying out the wiring result that parallel routing obtains according to the wiring information of described CPU (central processing unit) input and exports to described CPU (central processing unit).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320178887 CN203204602U (en) | 2013-04-10 | 2013-04-10 | Graphics processing unit-based wiring system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320178887 CN203204602U (en) | 2013-04-10 | 2013-04-10 | Graphics processing unit-based wiring system |
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| CN203204602U true CN203204602U (en) | 2013-09-18 |
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| CN 201320178887 Expired - Lifetime CN203204602U (en) | 2013-04-10 | 2013-04-10 | Graphics processing unit-based wiring system |
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| CN (1) | CN203204602U (en) |
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Address after: 200434 Room 202, building 5, No. 500, Memorial Road, Hongkou District, Shanghai Patentee after: Shanghai Anlu Information Technology Co.,Ltd. Address before: 200437 room 112, building 1, 623 Miyun Road, Hongkou District, Shanghai Patentee before: ANLOGIC INFOTECH Co.,Ltd. |
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Granted publication date: 20130918 |