CN103150461A - Parallel integration method and system for integrated circuit design - Google Patents
Parallel integration method and system for integrated circuit design Download PDFInfo
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- CN103150461A CN103150461A CN2013101236110A CN201310123611A CN103150461A CN 103150461 A CN103150461 A CN 103150461A CN 2013101236110 A CN2013101236110 A CN 2013101236110A CN 201310123611 A CN201310123611 A CN 201310123611A CN 103150461 A CN103150461 A CN 103150461A
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Abstract
The invention relates to the field of integrated circuit design and discloses a parallel integration method and system for integrated circuit design. The parallel integration method comprises the steps of: simultaneously generating a plurality of functional equivalent subgraphs of specific-mode subgraphs in an original CDFG (Control Data Flow Graph) by using the parallel processing capability in a computer technology, combining the functional equivalent subgraphs of each specific-mode subgraph into a plurality of CDFGs, carrying out parallel treatment and optimization on the plurality of CDFGs, simultaneously generating a plurality of low-level hardware circuits, and finally, selecting and determining the low-level hardware circuit with the optimal performance for one time. And therefore, the integration time required by the plurality of CDFGs is only one cycle time of the traditional integration flow, the time required for integration is greatly shortened, and in addition, as the combination of all the functional equivalent subgraphs is structured into a special CDFG to be optimized independently, the optimal circuit finally determined through parallel integration via parallel search is the optimal result which can be found out in all solution spaces.
Description
Technical field
The present invention relates to the integrated circuit (IC) design field, particularly for parallel integrated approach and the system thereof of integrated circuit (IC) design.
Background technology
It is comprehensively the process of low level hardware description form that high-level hardware description form is transformed into.Method at Register Transfer Level comprehensive (RTL Synthesis) is that use hardware description language (Hardware Description Language is called for short " HDL ") is transformed into process with the gate level circuit of function information as the register transfer level circuit of Verilog or VHDL description.Gate leve comprehensive (Gate-level Synthesis) is to convert the gate level circuit with function information to the gate level circuit of physical message process.Physical level comprehensive (Physical Synthesis) is the position and the process that interconnects wire shape that will determine with the gate level circuit of physical message rule makers' according to integrated circuit at the final physical chip.
Overwhelming majority hardware circuit design is all with the behavior of HDL language description Method at Register Transfer Level hardware, then generate gate level circuit by the integrated circuit (IC) design automated software, carry out various gate leves and physical level optimization, produce at last the receptible physical level descriptor format of integrated circuit manufacturing plant.Method at Register Transfer Level to the comprehensive traditional process of physical level as shown in Figure 1.At first, hardware description language is carried out language analysis and generates the syntax tree of a descriptive language internal relations, syntax tree is carried out semantic analysis control data flowchart (Control Date Flow Graph is called for short " CDFG ") to construct one.Second step is to seek various specific patterns to be optimized on CDFG, such as the balance of resource sharing optimization, arithmetical logic optimization, logic tree etc., each CDFG node is generated gate level circuit.The 3rd step was that gate level circuit is carried out various distortion optimizations, produced the physical level gate circuit that is complementary according to the physics manufacturing process.The 4th step was physical level optimization, determined the position of gate cell and the shape of interconnection line according to the physics manufacturing process, according to the function of physical location and the interconnection line shape adjustments gate cell of gate cell.The various aspects of performance of last computational physics level circuit.Area, speed and power consumption are topmost three indexs.If all indexs all satisfy design object, comprehensively be successfully completed output circuit physical Design scheme; If index does not satisfy design object, general flow need to determine according to the deviation of index to re-start selectively physical level optimization, gate leve optimization, or even CDFG optimizes.
The present inventor's discovery, such loop optimization process usually needs a plurality of circulations could satisfy design object, spends very long computer running time, has a strong impact on the efficient of integrated circuit hardware design.And because each circulation is to carry out local optimum on a specific CDFG structure, do not have the overall situation to consider simultaneously the various deformation structure of CDFG, repeatedly circulation can not produce best circuit.
Summary of the invention
The object of the present invention is to provide a kind of parallel integrated approach and system thereof for integrated circuit (IC) design, it has greatly shortened the comprehensive time, and can obtain the low level hardware circuit of best performance.
For solving the problems of the technologies described above, embodiments of the present invention disclose a kind of parallel integrated approach for integrated circuit (IC) design, and above-mentioned is comprehensively that high-level hardware description is transformed into low level hardware description, and the method comprises the following steps:
Analytical procedure is constructed original control data flowchart CDFG to hardware designed language HDL analysis;
Construction step generates the different function equivalence subgraph of a plurality of structures of the AD HOC subgraph of original CDFG, and the function equivalence subgraph that makes up above-mentioned AD HOC subgraph is to form a plurality of CDFG;
Optimization Steps carries out parallel processing and optimizes to generate simultaneously a plurality of low level hardware circuits a plurality of CDFG;
Select the low level hardware circuit of step selectivity optimum from a plurality of low level hardware circuits;
The low level hardware circuit of the above-mentioned best performance of integrated circuit (IC) design requirement is satisfied in the output of output step.
Embodiments of the present invention also disclose a kind of parallel system ensemble for integrated circuit (IC) design, and above-mentioned is comprehensively that high-level hardware description is transformed into low level hardware description, and this system comprises:
Analysis module is used for hardware designed language HDL analysis is constructed original control data flowchart CDFG;
Build the different function equivalence subgraph of a plurality of structures that module is used for generating the AD HOC subgraph of original CDFG, and the function equivalence subgraph that makes up above-mentioned AD HOC subgraph is to form a plurality of CDFG;
Optimizing module is used for a plurality of CDFG are carried out parallel processing and optimize to generate simultaneously a plurality of low level hardware circuits;
Select module for the low level hardware circuit from a plurality of low level hardware circuit selectivity optimums;
Output module is used for the low level hardware circuit that the above-mentioned best performance of integrated circuit (IC) design requirement is satisfied in output.
Embodiment of the present invention compared with prior art, the key distinction and effect thereof are:
the present invention utilizes the parallel processing capability in computer technology, generate simultaneously a plurality of function equivalence subgraphs of the AD HOC subgraph in original CDFG, the function equivalence subgraph of each AD HOC subgraph is combined to form a plurality of CDFG, and above-mentioned a plurality of CDFG are carried out parallel processing and optimization, generate simultaneously a plurality of low level hardware circuits, the low level hardware circuit of best performance is determined in last property selection, the generalized time that therefore a plurality of CDFG need is the time of a circulation of traditional general flow, greatly shortened the comprehensive required time, and because the combination of all functions subgraph of equal value all is configured to special CDFG and optimizes separately, the above-mentioned parallel comprehensive optimum circuit of determining at last through parallel search is exactly that all solve the optimal result that can find in the space.
Further, a plurality of function equivalence subgraphs of above-mentioned AD HOC subgraph are stored in super CDFG with chain sheet form or array format, be convenient to management and combination to above-mentioned functions subgraph of equal value, thereby can consider simultaneously the various deformation structure of CDFG from the overall situation, effectively to find out optimum circuit.
Further, select to delete to carry out two-stage before forming a plurality of CDFG at the function equivalence subgraph of the above-mentioned AD HOC subgraph of combination, reduced further generalized time.
Description of drawings
Fig. 1 is existing general flow schematic diagram;
Fig. 2 is the schematic flow sheet of a kind of parallel integrated approach in first embodiment of the invention;
Fig. 3 is the schematic flow sheet of a kind of construction step of parallel integrated approach in second embodiment of the invention;
Fig. 4 carries out the schematic diagram of AD HOC subgraph identification to original CDFG in second embodiment of the invention;
Fig. 5 is that in second embodiment of the invention, a kind of CDFG shares subgraph;
Fig. 6, Fig. 7 are respectively a kind of function equivalence subgraphs of Fig. 5;
Fig. 8 is the schematic diagram of preserving the super CDFG of all functions subgraph of equal value in second embodiment of the invention;
Fig. 9 is the structural representation of a kind of parallel system ensemble in third embodiment of the invention;
Figure 10 is the structural representation of a kind of parallel system ensemble in third embodiment of the invention;
Figure 11 is the structural representation of the structure module of a kind of parallel system ensemble in four embodiment of the invention.
Embodiment
In the following description, in order to make the reader understand the application better, many ins and outs have been proposed.But, persons of ordinary skill in the art may appreciate that even without these ins and outs with based on many variations and the modification of following each embodiment, also can realize each claim of the application technical scheme required for protection.
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing, embodiments of the present invention are described in further detail.
First embodiment of the invention relates to a kind of parallel integrated approach for integrated circuit (IC) design.Fig. 2 is the schematic flow sheet of this parallel integrated approach.Above-mentioned is comprehensively that high-level hardware description is transformed into low level hardware description, and as shown in Figure 2, the method comprises the following steps:
Analytical procedure is constructed original control data flowchart CDFG to hardware designed language HDL analysis.Be appreciated that CDFG comprises the digraph of controlling node and data processing node.
Construction step generates the different function equivalence subgraph of a plurality of structures of the AD HOC subgraph of original CDFG, and the function equivalence subgraph that makes up above-mentioned AD HOC subgraph is to form a plurality of CDFG.
Optimization Steps carries out parallel processing and optimizes to generate simultaneously a plurality of low level hardware circuits a plurality of CDFG.
Select the low level hardware circuit of step selectivity optimum from a plurality of low level hardware circuits.Be appreciated that in above-mentioned performance, area, speed and power consumption are topmost three indexs.
The low level hardware circuit of the above-mentioned best performance of integrated circuit (IC) design requirement is satisfied in the output of output step.
Alternatively, above-mentioned is comprehensively comprehensive from the Method at Register Transfer Level to the physical level, be about to be transformed into the physical level circuit with the register transfer level circuit that HDL language (Verilog or VHDL) is described, in this comprehensive Optimization Steps, each CDFG generates independent physical level circuit through CDFG optimization, gate leve optimization, physical level optimization separately; Above-mentioned can be also comprehensively comprehensive from the Method at Register Transfer Level to the gate leve, in this comprehensive Optimization Steps, each CDFG separately through CDFG optimize, gate leve optimization and generate independent gate level circuit.
In addition, because present computer technology has developed into the cloud computing epoch, computer technology provides the parallel computing of at least two levels: many computing machines in (1) high in the clouds carry out Distributed Calculation simultaneously; (2) each computing machine all has the computation capability of multithreading, and some computing machines also have been equipped with the graphic process unit that hundreds and thousands of microprocessing units are arranged.Therefore, be appreciated that in each embodiment, can be walked abreast comprehensively by many computing machines in computer network, also can be walked abreast comprehensively by a plurality of little processing core in a computing machine.
the present invention utilizes the parallel processing capability in computer technology, generate simultaneously a plurality of function equivalence subgraphs of the AD HOC subgraph in original CDFG, the function equivalence subgraph of each AD HOC subgraph is combined to form a plurality of CDFG, and above-mentioned a plurality of CDFG are carried out parallel processing and optimization, generate simultaneously a plurality of low level hardware circuits, the low level hardware circuit of best performance is determined in last property selection, the generalized time that therefore a plurality of CDFG need is the time of a circulation of traditional general flow, greatly shortened the comprehensive required time, and because the combination of all functions subgraph of equal value all is configured to special CDFG and optimizes separately, the above-mentioned parallel comprehensive optimum circuit of determining at last through parallel search is exactly that all solve the optimal result that can find in the space.
Second embodiment of the invention relates to a kind of parallel integrated approach for integrated circuit (IC) design.Fig. 3 is the schematic flow sheet of construction step in this parallel integrated approach.
The second embodiment improves on the basis of the first embodiment, mainly construction step is improved.Specifically:
As shown in Figure 3, above-mentioned construction step comprises the following steps:
Steps A is carried out the identification of AD HOC subgraph to original CDFG, and generates the different function equivalence subgraph of a plurality of structures of above-mentioned AD HOC subgraph.
Be appreciated that above-mentioned functions subgraph of equal value has the performances such as different areas, speed and power consumption because of the difference of structure.
Step B constructs all functions subgraph of equal value of above-mentioned AD HOC subgraph to form super CDFG based on original CDFG;
Step C forms a plurality of CDFG by the function equivalence subgraph of above-mentioned AD HOC subgraph in the super CDFG of combination.
As preferred implementation, in above-mentioned construction step, the combination of these function equivalence subgraphs is and selects to delete the exhaustive combination that combines.Be appreciated that in other embodiments of the present invention, also can adopt other array mode, as long as can obtain the various deformation of CDFG.
Exhaustive combination is to select successively each function equivalence subgraph of each AD HOC to form a complete CDFG.For the super CDFG with k AD HOC, the function equivalence subgraph number of each AD HOC is expressed as n successively
1, n
2..., n
k, be n=n through the constructable CDFG number of super CDFG after exhaustive combination
1* n
2* ... * n
kThe CDFG number that constructs may be a lot, and therefore, in technical solution of the present invention, with selecting to delete that method reduces n, preferably, this selection is deleted and deleted for the two-stage selection:
The first order deletes it is only to generate the function equivalence subgraph with physical level AD HOC subgraph of particular electrical circuit hardware when realizing.
In a preferred example, the following several AD HOC subgraphs of main identification:
(1) only comprise the arithmetic subgraph of two or more arithmetic function nodes (as totalizer, subtracter, multiplier, divider etc.);
(2) only comprise the control subgraph of two or more MUX;
Two data inputs of (3) MUX are respectively the shared subgraphs of arithmetic subgraph.
As shown in Figure 4, four AD HOC are extracted out: G1, tree-shaped MUX subgraph; G2, totalizer is shared subgraph; G3 comprises the arithmetic subgraph of multiplier and totalizer; G4, chain MUX subgraph.Fig. 5 provides the shared subgraph example that pattern-recognition is found out, two data inputs of a MUX are respectively the arithmetic subgraphs, an arithmetic subgraph is realized the arithmetic function of a*b+c, another arithmetic subgraph is realized the function of e*f+d, the value of the output y of MUX is the result of a*b+c by selecting signal s to determine, or the result of e*f+d.Fig. 6 subgraph has the different function equivalence subgraph of a plurality of structures.What Fig. 6 provided is a kind of function equivalence subgraph of selector switch in the middle of multiplier and totalizer.What Fig. 7 provided is that selector switch is at a kind of function equivalence subgraph of a/b/c/d/e/f input end.Although Fig. 5, Fig. 6, Fig. 7 subgraph function equivalence, their performance index are all different.Make a concrete analysis of as follows:
Fig. 5 (selector switch is at the y output terminal): use 2 multipliers, 2 totalizers, 1 MUX, the maximum duration from signal s to output y postpones to only have the delay of 1 MUX;
Fig. 6 (selector switch is in the middle of multiplier and totalizer): use 2 multipliers, 1 totalizer, 2 MUX, it is the cumulative delay of 1 MUX and 1 totalizer that the maximum duration from signal s to output y postpones;
Fig. 7 (selector switch is at the a/b/c/d/e/f input end): use 1 multiplier, 1 totalizer, 3 MUX, it is the cumulative delay of 1 MUX, 1 multiplier and 1 totalizer that the maximum duration from signal s to output y postpones.
In general flow, the time delays information of each signal is to change along with the selection of different subgraphs, and especially the time delays information on the initial CDFG of flow process is very uncertain, because also do not have physical circuit to realize at each node of flow process primary stage.In traditional general flow, usually all do the selection of Greedy, each subgraph is selected the structure of area minimum or the structure of signal specific time delay minimum.But because each node does not also have physical circuit to realize, area and time delay all can only be estimated, can't accurately calculate.After the ad hoc structure of wolfishly having selected a possible errors, this wrong ad hoc structure further affects again next step CDFG structure optimization and selects.And the present invention considers the various deformation structure of CDFG simultaneously by a plurality of function equivalence subgraphs of AD HOC subgraph from the overall situation, can effectively find out optimum circuit.
Be appreciated that and also can identify as required other AD HOC subgraphs in other embodiments of the present invention, generate a plurality of function equivalence subgraphs, thereby consider simultaneously the various deformation structure of CDFG from the overall situation, effectively to find out optimum circuit, be not limited to above-mentioned several AD HOC.
The second level deletes it is that analysis and filter is fallen the function equivalence subgraph that combination property obviously is worse than original AD HOC subgraph before the function equivalence subgraph of the above-mentioned AD HOC subgraph of combination.
Function equivalence subgraph at the above-mentioned AD HOC subgraph of combination is selected to delete to carry out two-stage before forming a plurality of CDFG, has reduced further generalized time.
In addition, be appreciated that in other embodiments of the present invention, also can carry out one-level and select to delete, even do not select to delete, direct exhaustive combination also can realize technical scheme of the present invention.
Preferably, a plurality of function equivalence subgraphs of above-mentioned each AD HOC subgraph are stored in super CDFG with array format or chain sheet form.As shown in Figure 8, G1-1, G1-2 are together with G1 is kept at, and G2-1 is together with G2 is kept at, and G3-1 is together with G3 is kept at, and G4-1, G4-2 are together with G4 is kept at, and each AD HOC subgraph has at least two function equivalence subgraphs that structure is different.
A plurality of function equivalence subgraphs of above-mentioned AD HOC subgraph are stored in super CDFG with chain sheet form or array format, be convenient to management and combination to above-mentioned functions subgraph of equal value, thereby the various deformation structure of CDFG can be considered simultaneously from the overall situation, effectively to find out optimum circuit.
In addition, be appreciated that in other embodiments of the present invention, above-mentioned functions subgraph of equal value also can other forms be stored in this super CDFG.
Each method embodiment of the present invention all can be realized in modes such as software, hardware, firmwares.No matter the present invention realizes with software, hardware or firmware mode, instruction code can be stored in the storer of computer-accessible of any type (for example permanent or revisable, volatibility or non-volatile, solid-state or non-solid-state, fixing or removable medium etc.).equally, storer can be for example programmable logic array (Programmable Array Logic, be called for short " PAL "), random access memory (Random Access Memory, be called for short " RAM "), programmable read only memory (Programmable Read Only Memory, be called for short " PROM "), ROM (read-only memory) (Read-Only Memory, be called for short " ROM "), Electrically Erasable Read Only Memory (Electrically Erasable Programmable ROM, be called for short " EEPROM "), disk, CD, digital versatile disc (Digital Versatile Disc, be called for short " DVD ") etc.
Third embodiment of the invention relates to a kind of parallel system ensemble for integrated circuit (IC) design.Fig. 9, Figure 10 are the structural representations of this parallel system ensemble.This is comprehensively that high-level hardware description is transformed into low level hardware description, and as shown in Figure 9, said system comprises:
Analysis module is used for hardware designed language HDL analysis is constructed original control data flowchart CDFG;
Build the different function equivalence subgraph of a plurality of structures that module is used for generating the AD HOC subgraph of original CDFG, and the function equivalence subgraph that makes up above-mentioned AD HOC subgraph is to form a plurality of CDFG;
Optimizing module is used for a plurality of CDFG are carried out parallel processing and optimize to generate simultaneously a plurality of low level hardware circuits.
Select module for the low level hardware circuit from a plurality of low level hardware circuit selectivity optimums.
Output module is used for the low level hardware circuit that the above-mentioned best performance of integrated circuit (IC) design requirement is satisfied in output.
Alternatively, above-mentioned is comprehensively comprehensive from the Method at Register Transfer Level to the physical level, above-mentioned optimization module comprises that CDFG optimizes that the unit is optimized in unit, gate leve, physical level is optimized the unit, and it carries out separately respectively CDFG optimization, gate leve optimization, physical level optimization and generate independent physical level circuit each CDFG; Above-mentioned can be also comprehensively comprehensive from the Method at Register Transfer Level to the gate leve, and above-mentioned optimization module comprises that CDFG optimizes the unit, gate leve is optimized the unit, its to each CDFG carry out separately respectively that CDFG optimizes, gate leve optimization and generate independent gate level circuit.
Preferably, as shown in figure 10, said system can be realized by a plurality of processors of mutual electrical connection and the storer that is electrically connected to above-mentioned a plurality of processors respectively, display.
In above-mentioned a plurality of processor one, be used for controlling above-mentioned storer and export the high-level hardware description information that this storer is stored, and will hardware description information exchange high-level according to this cross a plurality of CDFG that the function equivalence subgraph of combination AD HOC subgraph forms and export to above-mentioned a plurality of processor;
Above-mentioned a plurality of processor is exported to aforementioned display device for the low level hardware circuit of a plurality of low level hardware circuit performance optimums that will generate after above-mentioned a plurality of CDFG parallel optimizations and is shown.
Alternatively, above-mentioned processor is central processing unit, graphic process unit, or the combination of central processing unit and graphic process unit.
the present invention utilizes the parallel processing capability in computer technology, generate simultaneously a plurality of function equivalence subgraphs of the AD HOC subgraph in original CDFG, the function equivalence subgraph of each AD HOC subgraph is combined to form a plurality of CDFG, and above-mentioned a plurality of CDFG are carried out parallel processing and optimization, generate simultaneously a plurality of low level hardware circuits, the low level hardware circuit of best performance is determined in last property selection, the generalized time that therefore a plurality of CDFG need is the time of a circulation of traditional general flow, greatly shortened the comprehensive required time, and because the combination of all functions subgraph of equal value all is configured to special CDFG and optimizes separately, above-mentioned parallel system ensemble is exactly that all solve the optimal result that can find in the space through the optimum circuit that parallel search is determined at last.
The first embodiment is the method embodiment corresponding with present embodiment, present embodiment can with the enforcement of working in coordination of the first embodiment.The correlation technique details of mentioning in the first embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the first embodiment.
Four embodiment of the invention relates to a kind of parallel system ensemble for integrated circuit (IC) design.Figure 11 is the structural representation of this parallel system ensemble.
The 4th embodiment improves on the basis of the 3rd embodiment, and main the improvement improved building module.Specifically:
As shown in figure 11, above-mentioned structure module comprises:
CDFG subgraph generation unit is used for original CDFG is carried out the identification of AD HOC subgraph, and generates the different function equivalence subgraph of a plurality of structures of AD HOC subgraph.
Super CDFG generation unit is used for based on original CDFG, constructs all functions subgraph of equal value of above-mentioned AD HOC subgraph to form super CDFG;
Assembled unit is used for making up the function equivalence subgraph of the above-mentioned AD HOC subgraph of super CDFG, to form a plurality of CDFG.
Preferably, a plurality of function equivalence subgraphs of each AD HOC subgraph are stored in super CDFG with array format or chain sheet form.
A plurality of function equivalence subgraphs of above-mentioned AD HOC subgraph are stored in super CDFG with chain sheet form or array format, be convenient to management and combination to above-mentioned functions subgraph of equal value, thereby the various deformation structure of CDFG can be considered simultaneously from the overall situation, effectively to find out optimum circuit.
In addition, be appreciated that in other embodiments of the present invention, the function equivalence subgraph also can other forms be stored in this super CDFG.
As preferred implementation, build module and to the combination of the function equivalence subgraph of above-mentioned AD HOC subgraph be and select to delete the exhaustive combination that combines.Be appreciated that in other embodiments of the present invention, also can adopt other array mode, as long as can obtain the various deformation of CDFG.
Preferably, above-mentioned selection is deleted and is selected to delete for two-stage:
The first order deletes it is only to generate the function equivalence subgraph with physical level AD HOC subgraph of particular electrical circuit hardware when realizing;
The second level deletes it is that analysis and filter is fallen the function equivalence subgraph that combination property obviously is worse than original AD HOC subgraph before the function equivalence subgraph of the above-mentioned AD HOC subgraph of combination.
Function equivalence subgraph at the above-mentioned AD HOC subgraph of combination is selected to delete to carry out two-stage before forming a plurality of CDFG, has reduced further generalized time.
In addition, be appreciated that in other embodiments of the present invention, also can carry out one-level and select to delete, even do not select to delete, direct exhaustive combination also can realize technical scheme of the present invention.
The second embodiment is the method embodiment corresponding with present embodiment, present embodiment can with the enforcement of working in coordination of the second embodiment.The correlation technique details of mentioning in the second embodiment is still effective in the present embodiment, in order to reduce repetition, repeats no more here.Correspondingly, the correlation technique details of mentioning in present embodiment also can be applicable in the second embodiment.
Need to prove, each unit of mentioning in each equipment embodiment of the present invention is all logical block, physically, a logical block can be a physical location, it can be also the part of a physical location, can also realize with the combination of a plurality of physical locations, the physics realization mode of these logical blocks itself is not most important, and the combination of the function that these logical blocks realize is only the key that solves technical matters proposed by the invention.In addition, for outstanding innovation part of the present invention, above-mentioned each equipment embodiment of the present invention will not introduced not too close unit with solving technical matters relation proposed by the invention, and this does not show that there is not other unit in the said equipment embodiment.
Although pass through with reference to some of the preferred embodiment of the invention, the present invention is illustrated and describes, but those of ordinary skill in the art should be understood that and can do various changes to it in the form and details, and without departing from the spirit and scope of the present invention.
Claims (10)
1. parallel integrated approach that is used for integrated circuit (IC) design, described is comprehensively that high-level hardware description is transformed into low level hardware description, it is characterized in that, said method comprising the steps of:
Analytical procedure is constructed original control data flowchart CDFG to hardware designed language HDL analysis;
Construction step generates the different function equivalence subgraph of a plurality of structures of the AD HOC subgraph of described original CDFG, and the function equivalence subgraph that makes up described AD HOC subgraph is to form a plurality of CDFG;
Optimization Steps carries out parallel processing and optimizes to generate simultaneously a plurality of low level hardware circuits described a plurality of CDFG;
Select the low level hardware circuit of step selectivity optimum from described a plurality of low level hardware circuits;
The low level hardware circuit of the described best performance of integrated circuit (IC) design requirement is satisfied in the output of output step.
2. parallel integrated approach according to claim 1, is characterized in that, described construction step comprises the following steps:
Steps A is carried out the identification of AD HOC subgraph to described original CDFG, and generates the different function equivalence subgraph of a plurality of structures of described AD HOC subgraph;
Step B constructs all functions subgraph of equal value of described AD HOC subgraph to form super CDFG based on described original CDFG;
Step C forms a plurality of CDFG by the function equivalence subgraph of AD HOC subgraph described in the described super CDFG of combination.
3. parallel integrated approach according to claim 2, is characterized in that, a plurality of function equivalence subgraphs of each AD HOC subgraph are stored in described super CDFG with array format or chain sheet form.
4. the described parallel integrated approach of any one according to claim 1 to 3, it is characterized in that, in described construction step, the combination of the function equivalence subgraph of described AD HOC subgraph is and selects to delete the exhaustive combination that combines, wherein, described selection is deleted and is selected to delete for two-stage, the first order deletes it is only to generate the function equivalence subgraph with physical level AD HOC subgraph of particular electrical circuit hardware when realizing, the second level deletes it is that analysis and filter is fallen the function equivalence subgraph that combination property obviously is worse than original AD HOC subgraph before the function equivalence subgraph of the described AD HOC subgraph of combination.
5. the described parallel integrated approach of any one according to claim 1 to 3, it is characterized in that, described is comprehensively comprehensive from the Method at Register Transfer Level to the physical level, in described comprehensive Optimization Steps, each CDFG generates independent physical level circuit through CDFG optimization, gate leve optimization, physical level optimization separately; Or
Described is comprehensively comprehensive from the Method at Register Transfer Level to the gate leve, in described comprehensive Optimization Steps, each CDFG separately through CDFG optimize, gate leve optimization and generate independent gate level circuit.
6. parallel integrated approach according to claim 4, it is characterized in that, described is comprehensively comprehensive from the Method at Register Transfer Level to the physical level, and in described comprehensive Optimization Steps, each CDFG generates independent physical level circuit through CDFG optimization, gate leve optimization, physical level optimization separately; Or
Described is comprehensively comprehensive from the Method at Register Transfer Level to the gate leve, in described comprehensive Optimization Steps, each CDFG separately through CDFG optimize, gate leve optimization and generate independent gate level circuit.
7. parallel system ensemble that is used for integrated circuit (IC) design, described is comprehensively that high-level hardware description is transformed into low level hardware description, it is characterized in that, described system comprises:
Analysis module is used for hardware designed language HDL analysis is constructed original control data flowchart CDFG;
Build the different function equivalence subgraph of a plurality of structures that module is used for generating the AD HOC subgraph of described original CDFG, and the function equivalence subgraph that makes up described AD HOC subgraph is to form a plurality of CDFG;
Optimizing module is used for described a plurality of CDFG are carried out parallel processing and optimize to generate simultaneously a plurality of low level hardware circuits;
Select module for the low level hardware circuit from described a plurality of low level hardware circuit selectivity optimums;
Output module is used for the low level hardware circuit that the described best performance of integrated circuit (IC) design requirement is satisfied in output.
8. parallel system ensemble according to claim 7, is characterized in that, described structure module comprises:
CDFG subgraph generation unit is used for described original CDFG is carried out the identification of AD HOC subgraph, and generates the different function equivalence subgraph of a plurality of structures of described AD HOC subgraph;
Super CDFG generation unit is used for based on described original CDFG, constructs all functions subgraph of equal value of described AD HOC subgraph to form super CDFG;
Assembled unit is used for making up the function equivalence subgraph of AD HOC subgraph described in described super CDFG, forms a plurality of CDFG.
9. parallel system ensemble according to claim 8, is characterized in that, a plurality of function equivalence subgraphs of each AD HOC subgraph are stored in described super CDFG with array format or chain sheet form.
10. the described parallel system ensemble of any one according to claim 7 to 9, it is characterized in that, described is comprehensively comprehensive from the Method at Register Transfer Level to the physical level, described optimization module comprises that CDFG optimizes that the unit is optimized in unit, gate leve, physical level is optimized the unit, and it carries out separately respectively CDFG optimization, gate leve optimization, physical level optimization and generate independent physical level circuit each CDFG; Or
Described is comprehensively comprehensive from the Method at Register Transfer Level to the gate leve, and described optimization module comprises that CDFG optimizes the unit, gate leve is optimized the unit, its to each CDFG carry out separately respectively that CDFG optimizes, gate leve optimization and generate independent gate level circuit;
In addition, described structure module is and selects to delete the exhaustive combination that combines the combination of the function equivalence subgraph of described AD HOC subgraph, wherein, described selection is deleted and is selected to delete for two-stage, the first order deletes it is only to generate the function equivalence subgraph with physical level AD HOC subgraph of particular electrical circuit hardware when realizing, the second level deletes it is that analysis and filter is fallen the function equivalence subgraph that combination property obviously is worse than original AD HOC subgraph before the function equivalence subgraph of the described AD HOC subgraph of combination.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105677960A (en) * | 2016-01-04 | 2016-06-15 | 中国兵器工业集团第二一四研究所苏州研发中心 | Implementing method for Auto-DC automation integrated design |
| CN106462431A (en) * | 2014-06-02 | 2017-02-22 | 赛灵思公司 | Extracting system architecture in high level synthesis |
| CN112541309A (en) * | 2020-12-18 | 2021-03-23 | 广东高云半导体科技股份有限公司 | Logic synthesis realization control method and device |
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| CN105677960A (en) * | 2016-01-04 | 2016-06-15 | 中国兵器工业集团第二一四研究所苏州研发中心 | Implementing method for Auto-DC automation integrated design |
| CN112541309A (en) * | 2020-12-18 | 2021-03-23 | 广东高云半导体科技股份有限公司 | Logic synthesis realization control method and device |
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