CN203191890U - Board card capable of achieving high-speed bus retransmission - Google Patents
Board card capable of achieving high-speed bus retransmission Download PDFInfo
- Publication number
- CN203191890U CN203191890U CN 201320170686 CN201320170686U CN203191890U CN 203191890 U CN203191890 U CN 203191890U CN 201320170686 CN201320170686 CN 201320170686 CN 201320170686 U CN201320170686 U CN 201320170686U CN 203191890 U CN203191890 U CN 203191890U
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- China
- Prior art keywords
- circuit board
- speed bus
- printed circuit
- board card
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 238000000034 method Methods 0.000 description 3
- 239000005441 aurora Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
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Abstract
The utility model provides a board card capable of achieving high-speed bus retransmission. The board card structurally comprises a printed circuit board. QSFP connectors are symmetrically arranged on the two opposite sides of the printed circuit board, and at least two DDR2 connectors, a power connector, a data processing accelerating chip and a data forwarding chip are further arranged on the printed circuit board. Compared with the prior art, the board card capable of achieving high-speed bus retransmission has the advantages of being reasonable in design, simple in structure, convenient to use and the like. The board card capable of achieving high-speed bus retransmission achieves data processing and data retransmission of a CPU high-speed bus based on FPGA and QSFP. The board card supports FPGAAURORA interconnection protocols, supports the QSFP connectors to achieve high-speed interconnection between board cards and is easy to popularize and use.
Description
Technical field
The utility model relates to field of computer technology, specifically a kind of simple in structure, realize the integrated circuit board that high-speed bus is transmitted.
Background technology
In the Computer Service applicator platform of prior art, CPU is transferred to data on the integrated circuit board need be through the processing of a series of chips and interface and transmit and could realize and other integrated circuit board interconnected, whole process needs two integrated circuit boards at least, the signal conversion process very complicated, thereby need a kind of integrated circuit board that can realize that high speed is transmitted.
Summary of the invention
Technical assignment of the present utility model is to solve the deficiencies in the prior art, provide a kind of simple in structure, realize the integrated circuit board that high-speed bus is transmitted.
The technical solution of the utility model realizes in the following manner, this a kind of integrated circuit board of realizing that high-speed bus is transmitted, its structure comprises printed circuit board, the relative symmetria bilateralis of described printed circuit board is provided with the QSFP connector, also is provided with at least two DDR3 connectors, power connector, data and handles speed-up chip and data and pass on chip on printed circuit board.
As preferably, described QSFP connector is provided with 12, and the every side of printed circuit board is provided with 6.
Further, described data are handled speed-up chip and data and are passed on chip and be fpga chip.
In sum, the beneficial effect that compared with prior art produces of the utility model is:
A kind of integrated circuit board of realizing that high-speed bus is transmitted of the present utility model has characteristics such as simple in structure, easy to use, novel, this integrated circuit board is realized data processing and the forwarding of CPU high-speed bus based on FPGA and QSFP, support FPGA AURORA interconnection protocol, support the QSFP connector to realize the high-speed interconnect between integrated circuit board, thereby have good value for applications.
Description of drawings
Accompanying drawing 1 is structural representation block diagram of the present utility model.
Mark in the accompanying drawing is represented respectively:
1, printed circuit board, 2, the QSFP connector, 3, fpga chip, 4, the DDR3 connector, 5, power connector.
Embodiment
Below in conjunction with accompanying drawing a kind of integrated circuit board of realizing that high-speed bus is transmitted of the present utility model is done following detailed description the in detail.
As shown in Figure 1, this a kind of integrated circuit board of realizing that high-speed bus is transmitted, its structure comprises printed circuit board 1, the relative symmetria bilateralis of described printed circuit board 1 is provided with QSFP connector 2, also is provided with at least two DDR3 connectors 4, power connector 5, data and handles speed-up chip and data and pass on chip on printed circuit board 1.
Described QSFP connector 2 is provided with 12, and printed circuit board 1 every side is provided with 6.
Described data are handled speed-up chip and data and are passed on chip and be fpga chip 3.
Calculate the data of CPU of plate by the enter FPGA of downside of the downside QSFP connector on the integrated circuit board, after this FPGA utilizes DDR3 for the processing and acceleration of buffer memory process to data, through the FPGA of data transmission to upside, the FPGA of upside is forwarded to other integrated circuit boards to the data that receive by the QSFP connector by the high speed interconnection protocol AURORA between FPGA.Integrated circuit board is given two FPGA power supplies by the power connector on the right in addition, realizes that by the control signal connector other integrated circuit boards are to the control of fpga chip.
Except the described technical characterictic of instructions, be the known technology of those skilled in the art.
Claims (3)
1. integrated circuit board of realizing that high-speed bus is transmitted, it is characterized in that: its structure comprises printed circuit board, the relative symmetria bilateralis of described printed circuit board is provided with the QSFP connector, also is provided with at least two DDR3 connectors, power connector, data and handles speed-up chip and data and pass on chip on printed circuit board.
2. a kind of integrated circuit board of realizing that high-speed bus is transmitted according to claim 1, it is characterized in that: described QSFP connector is provided with 12, and the every side of printed circuit board is provided with 6.
3. a kind of integrated circuit board of realizing that high-speed bus is transmitted according to claim 1 is characterized in that: described data are handled speed-up chip and data and are passed on chip and be fpga chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320170686 CN203191890U (en) | 2013-04-08 | 2013-04-08 | Board card capable of achieving high-speed bus retransmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320170686 CN203191890U (en) | 2013-04-08 | 2013-04-08 | Board card capable of achieving high-speed bus retransmission |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203191890U true CN203191890U (en) | 2013-09-11 |
Family
ID=49108737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320170686 Expired - Fee Related CN203191890U (en) | 2013-04-08 | 2013-04-08 | Board card capable of achieving high-speed bus retransmission |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203191890U (en) |
-
2013
- 2013-04-08 CN CN 201320170686 patent/CN203191890U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130911 Termination date: 20150408 |
|
| EXPY | Termination of patent right or utility model |