CN203180853U - Combination type power amplifier - Google Patents
Combination type power amplifier Download PDFInfo
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- CN203180853U CN203180853U CN 201320121138 CN201320121138U CN203180853U CN 203180853 U CN203180853 U CN 203180853U CN 201320121138 CN201320121138 CN 201320121138 CN 201320121138 U CN201320121138 U CN 201320121138U CN 203180853 U CN203180853 U CN 203180853U
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- electric capacity
- power amplifier
- resistance
- potentiometer
- inductance
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Abstract
The utility model discloses a combination type power amplifier. The combination type power amplifier comprises a primary power amplifier and a secondary power amplifier. The input end of the power amplifier is connected with the signal output end of a virtual signal generator. The output end of the primary power amplifier is connected with the input end of the secondary power amplifier. The combination type power amplifier is characterized in that the primary power amplifier comprises a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a first inductor, a second inductor, a first resistor, a second resistor, a third resistor, a first potentiometer, a second potentiometer and a first transistor. The combination type power amplifier is formed by the primary power amplifier and the secondary power amplifier, gain of the combination type power amplifier can be relatively stable in a quite wide pass band, output signals of the primary power amplifier serve as input signals of the secondary power amplifier, and the secondary power amplifier serves as a last-stage power amplifier of a transmitter so as to acquire a large output power and high output efficiency.
Description
Technical field
The utility model relates to a kind of power amplifier, particularly relates to a kind of combined power amplifier.
Background technology
Power amplifier namely produces the input audio signal of true, efficient and low distortion again on the sounding output element with the volume that requires and power level.Audio frequency amplifier is divided into D class A amplifier A, linear amplifier, class-a amplifier, class-b amplifier and class ab ammplifier five big classes substantially, compare with the design of D class A amplifier A, even the most effective linear output stage of class-a amplifier, class-b amplifier and class ab ammplifier, their output stage power consumption is also very big.This difference makes the D class A amplifier A have significant advantage in many application, and is less because low-power consumption produces heat, saves printing board PCB area and cost, and can prolong the battery life of portable system.Yet use separately the D class A amplifier A also to exist at some under to the demanded power output condition with higher and obtain the needs that power output can not satisfy the client.
The utility model content
The purpose of this utility model is the combined power amplifier that a kind of simple in structure, power output gain stabilization is provided in order to address the above problem.
The utility model is achieved through the following technical solutions:
A kind of combined power amplifier, comprise prime power amplifier and time stage power amplifier, described prime power amplifier input terminal is connected with the signal output part of virtual signal generator, the output of described prime power amplifier is connected with the input of described stage power amplifier, described prime power amplifier comprises first electric capacity, second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, first inductance, second inductance, first resistance, second resistance, the 3rd resistance, first potentiometer, second potentiometer and the first transistor, first end of described first electric capacity is connected with the output of described virtual signal generator, second end of described first electric capacity is connected with the base stage of described the first transistor, first end of described first potentiometer is connected with first end of described first resistance, second end of described first resistance is connected with first end of described first inductance and first end of described second electric capacity respectively, second end of described first inductance respectively with the collector electrode of described the first transistor, second end of second electric capacity is connected with first end of described the 3rd electric capacity, the emitter of described the first transistor is connected with first end of described second resistance and first end of described the 5th electric capacity respectively, second end of described the 5th electric capacity respectively with the sliding end of described first potentiometer, first end of first potentiometer, first end of second potentiometer connects, second end of described second resistance is connected with second end of described second potentiometer and the sliding end of second potentiometer respectively, first end of described the 3rd electric capacity is connected with first end of described second inductance and the input of described stage power amplifier respectively, second end of described second inductance is connected with first end of described the 3rd resistance and first end of described the 4th electric capacity respectively, and second end of described the 3rd resistance is connected back ground connection with second end of described the 4th electric capacity.
Further, described time stage power amplifier comprises transistor seconds, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 6th electric capacity, the 7th electric capacity, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity, the 11 electric capacity, the 12 electric capacity and the 3rd potentiometer, the base stage of described transistor seconds is connected with second end of described the 3rd electric capacity and first end of described second inductance respectively, the collector electrode of described transistor seconds respectively with first end of described the 6th electric capacity, first end of the 7th electric capacity is connected with first end of described the 3rd inductance, second end of described the 6th electric capacity respectively with first end of described the 7th electric capacity, second end of the 3rd inductance, first end of the 8th electric capacity is connected with first end of described the 4th inductance, second end of described the 4th inductance is connected with first end of power supply and described the 9th electric capacity respectively, second end of described the 8th electric capacity is connected back ground connection with second end of described the 9th electric capacity, first end of described the 3rd inductance respectively with first end of described the tenth electric capacity, first end of the 11 electric capacity and first end of described the 12 electric capacity are connected, second end of described the tenth electric capacity is connected with first end of described the 5th resistance, second end of described the 5th resistance is connected back ground connection with first end of described the 6th resistance and first end of described the 7th resistance respectively, second end of described the 6th resistance is connected with second end of described the 11 electric capacity, second end of described the 7th resistance is connected with second end of described the 12 electric capacity, the emitter of described transistor seconds is connected with first end of described the 4th resistance, second end of described the 4th resistance is connected with first end of described the 3rd potentiometer and the sliding end of described the 3rd potentiometer respectively, the second end ground connection of described the 3rd potentiometer.
The beneficial effects of the utility model are:
The utility model is made up of prime power amplifier and time stage power amplifier, can in wideer passband, make the power amplifier gain relatively stable, the output signal of prime power amplifier is as the input signal of time stage power amplifier, inferior stage power amplifier as the last stage of transmitter power amplifier to obtain bigger power output and higher efficient.
Description of drawings
Fig. 1 is circuit diagram of the present utility model.
Embodiment
The utility model is described in further detail below in conjunction with drawings and the specific embodiments:
As shown in Figure 1, the combined power amplifier of the utility model, comprise prime power amplifier and time stage power amplifier, described prime power amplifier input terminal is connected with the signal output part of virtual signal generator, the output of described prime power amplifier is connected with the input of described stage power amplifier, described prime power amplifier comprises first capacitor C 1, second capacitor C 2, the 3rd capacitor C 3, the 4th capacitor C 4, the 5th capacitor C 5, first inductance L 1, second inductance L 2, first resistance R 1, second resistance R 2, the 3rd resistance R 3, the first potentiometer RP1, the second potentiometer RP2 and the first transistor VT1, first end of described first capacitor C 1 is connected with the output of described virtual signal generator, second end of described first capacitor C 1 is connected with the base stage of described the first transistor VT1, first end of the described first potentiometer RP1 is connected with first end of described first resistance R 1, second end of described first resistance R 1 is connected with first end of described first inductance L 1 and first end of described second capacitor C 2 respectively, second end of described first inductance L 1 respectively with the collector electrode of described the first transistor VT1, second end of second capacitor C 2 is connected with first end of described the 3rd capacitor C 3, the emitter of described the first transistor VT1 is connected with first end of described second resistance R 2 and first end of described the 5th capacitor C 5 respectively, second end of described the 5th capacitor C 5 respectively with the sliding end of the described first potentiometer RP1, first end of the first potentiometer RP1, first end of the second potentiometer RP2 connects, second end of described second resistance R 2 is connected with second end of the described second potentiometer RP2 and the sliding end of the second potentiometer RP2 respectively, first end of described the 3rd capacitor C 3 is connected with first end of described second inductance L 2 and the input of described stage power amplifier respectively, second end of described second inductance L 2 is connected with first end of described the 3rd resistance R 3 and first end of described the 4th capacitor C 4 respectively, and second end of second end of described the 3rd resistance R 3 and described the 4th capacitor C 4 is connected back ground connection.
Described time stage power amplifier comprises transistor seconds VT2, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 6th capacitor C 6, the 7th capacitor C 7, the 8th capacitor C 8, the 9th capacitor C 9, the tenth capacitor C 10, the 11 capacitor C 11, the 12 capacitor C 12 and the 3rd potentiometer RP3, the base stage of described transistor seconds VT2 is connected with second end of described the 3rd capacitor C 3 and first end of described second inductance L 2 respectively, the collector electrode of described transistor seconds VT2 respectively with first end of described the 6th capacitor C 6, first end of the 7th capacitor C 7 is connected with first end of described the 3rd inductance L 3, second end of described the 6th capacitor C 6 respectively with first end of described the 7th capacitor C 7, second end of the 3rd inductance L 3, first end of the 8th capacitor C 8 is connected with first end of described the 4th inductance L 4, second end of described the 4th inductance L 4 is connected with first end of power supply with described the 9th capacitor C 9 respectively, second end of second end of described the 8th capacitor C 8 and described the 9th capacitor C 9 is connected back ground connection, first end of described the 3rd inductance L 3 respectively with first end of described the tenth capacitor C 10, first end of the 11 capacitor C 11 is connected with first end of described the 12 capacitor C 12, second end of described the tenth capacitor C 10 is connected with first end of described the 5th resistance R 5, second end of described the 5th resistance R 5 is connected back ground connection with first end of described the 6th resistance R 6 and first end of described the 7th resistance R 7 respectively, second end of described the 6th resistance R 6 is connected with second end of described the 11 capacitor C 11, second end of described the 7th resistance R 7 is connected with second end of described the 12 capacitor C 12, the emitter of described transistor seconds VT2 is connected with first end of described the 4th resistance R 4, second end of described the 4th resistance R 4 is connected with first end of described the 3rd potentiometer RP3 and the sliding end of described the 3rd potentiometer RP3 respectively, the second end ground connection of described the 3rd potentiometer RP3.
Claims (2)
1. combined power amplifier, comprise prime power amplifier and time stage power amplifier, described prime power amplifier input terminal is connected with the signal output part of virtual signal generator, the output of described prime power amplifier is connected with the input of described stage power amplifier, it is characterized in that: described prime power amplifier comprises first electric capacity, second electric capacity, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, first inductance, second inductance, first resistance, second resistance, the 3rd resistance, first potentiometer, second potentiometer and the first transistor, first end of described first electric capacity is connected with the output of described virtual signal generator, second end of described first electric capacity is connected with the base stage of described the first transistor, first end of described first potentiometer is connected with first end of described first resistance, second end of described first resistance is connected with first end of described first inductance and first end of described second electric capacity respectively, second end of described first inductance respectively with the collector electrode of described the first transistor, second end of second electric capacity is connected with first end of described the 3rd electric capacity, the emitter of described the first transistor is connected with first end of described second resistance and first end of described the 5th electric capacity respectively, second end of described the 5th electric capacity respectively with the sliding end of described first potentiometer, first end of first potentiometer, first end of second potentiometer connects, second end of described second resistance is connected with second end of described second potentiometer and the sliding end of second potentiometer respectively, first end of described the 3rd electric capacity is connected with first end of described second inductance and the input of described stage power amplifier respectively, second end of described second inductance is connected with first end of described the 3rd resistance and first end of described the 4th electric capacity respectively, and second end of described the 3rd resistance is connected back ground connection with second end of described the 4th electric capacity.
2. a kind of combined power amplifier according to claim 1, it is characterized in that: described time stage power amplifier comprises transistor seconds, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 6th electric capacity, the 7th electric capacity, the 8th electric capacity, the 9th electric capacity, the tenth electric capacity, the 11 electric capacity, the 12 electric capacity and the 3rd potentiometer, the base stage of described transistor seconds is connected with second end of described the 3rd electric capacity and first end of described second inductance respectively, the collector electrode of described transistor seconds respectively with first end of described the 6th electric capacity, first end of the 7th electric capacity is connected with first end of described the 3rd inductance, second end of described the 6th electric capacity respectively with first end of described the 7th electric capacity, second end of the 3rd inductance, first end of the 8th electric capacity is connected with first end of described the 4th inductance, second end of described the 4th inductance is connected with first end of power supply and described the 9th electric capacity respectively, second end of described the 8th electric capacity is connected back ground connection with second end of described the 9th electric capacity, first end of described the 3rd inductance respectively with first end of described the tenth electric capacity, first end of the 11 electric capacity and first end of described the 12 electric capacity are connected, second end of described the tenth electric capacity is connected with first end of described the 5th resistance, second end of described the 5th resistance is connected back ground connection with first end of described the 6th resistance and first end of described the 7th resistance respectively, second end of described the 6th resistance is connected with second end of described the 11 electric capacity, second end of described the 7th resistance is connected with second end of described the 12 electric capacity, the emitter of described transistor seconds is connected with first end of described the 4th resistance, second end of described the 4th resistance is connected with first end of described the 3rd potentiometer and the sliding end of described the 3rd potentiometer respectively, the second end ground connection of described the 3rd potentiometer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320121138 CN203180853U (en) | 2013-03-18 | 2013-03-18 | Combination type power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320121138 CN203180853U (en) | 2013-03-18 | 2013-03-18 | Combination type power amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203180853U true CN203180853U (en) | 2013-09-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320121138 Expired - Fee Related CN203180853U (en) | 2013-03-18 | 2013-03-18 | Combination type power amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203180853U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103178797A (en) * | 2013-03-18 | 2013-06-26 | 成都龙腾中远信息技术有限公司 | Combined power amplifier |
| CN113629983A (en) * | 2021-07-08 | 2021-11-09 | 尤建兴 | Power supply circuit with high efficiency and stable output |
-
2013
- 2013-03-18 CN CN 201320121138 patent/CN203180853U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103178797A (en) * | 2013-03-18 | 2013-06-26 | 成都龙腾中远信息技术有限公司 | Combined power amplifier |
| CN113629983A (en) * | 2021-07-08 | 2021-11-09 | 尤建兴 | Power supply circuit with high efficiency and stable output |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130904 Termination date: 20140318 |