CN203166964U - DSP-based buss adaptor - Google Patents
DSP-based buss adaptor Download PDFInfo
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- CN203166964U CN203166964U CN 201320105227 CN201320105227U CN203166964U CN 203166964 U CN203166964 U CN 203166964U CN 201320105227 CN201320105227 CN 201320105227 CN 201320105227 U CN201320105227 U CN 201320105227U CN 203166964 U CN203166964 U CN 203166964U
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- dsp processor
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Abstract
The utility model discloses a DSP-based buss adaptor, comprising a DSP processor, a network communication card, a serial memory, and a RJ-11 interface circuit. Data ports of the DSP processor are respectively connected with a data port of the network communication card, a data port of the serial memory, and the RJ-11 interface circuit. The DSP processor comprises a bus controller, a read-only memory, a data encryptor, a memory, a CRC16 algorithm generator, a buffer, a data memory, and a key memory. With the adoption of the DSP processor equipped with an automatic encryption circuit, data storage and transmission can be more safe and reliable. By employing a USB interface circuit, the bus adaptor is enabled to be advantaged by being high in transmission speed and low in development cost and supporting hot-plug and plug-and-play functions.
Description
Technical field
The utility model relates to a kind of bus adapter, particularly relates to a kind of bus adapter based on DSP.
Background technology
Along with developing rapidly of computer hardware, software engineering and integrated circuit technique, communication network based on field bus technique progressively replaces the distributing industrial control system, becomes a kind of edge fingers most active in computer technology and the application of electronic technology field and makes great progress.The 1-Wire bus of the U.S. U.S. letter company design is to have a kind of of competitiveness in numerous fieldbus.Possessing and can carry out digital communication, big, terse, the plurality of advantages such as precision is high, stable performance, low price of wiring of bus load amount with computer, particularly be fit to very much short-distance and medium-distance communication, is the senior boundary of industrial system design.The realization that l-Wire measures network need combine with the PC main frame, so in the measurement network that the 1-Wire bus is formed, network adapter is absolutely necessary, it is undertaking the vital task of transfer of data between host monitor unit and the network node.Yet existing bus adapter exists circuit complexity, data storage and transmission security poor.
The utility model content
The purpose of this utility model is the bus adapter based on DSP that to provide in order addressing the above problem that a kind of circuit is simple, volume is little, to have data encryption feature.
The utility model is achieved through the following technical solutions:
A kind of bus adapter based on DSP, comprise dsp processor, the network communication card, serial storage and RJ-11 circuit, the FPDP of described dsp processor respectively with the FPDP of described network communication card, the FPDP of serial storage is connected with described RJ-11 circuit, described dsp processor comprises bus control unit, read-only memory, data encryptor, memory, CRC16 algorithm generator, buffer, data storage and secret key memory, the FPDP of described bus control unit is connected with the FPDP of described data encryptor, the FPDP of described data encryptor respectively with the FPDP of described buffer, the FPDP of the FPDP of described CRC16 algorithm generator and the FPDP of described data storage and described secret key memory is connected, the FPDP of described CRC16 algorithm generator and the FPDP of described data storage are connected, the FPDP of described buffer respectively with the FPDP of described data storage, the FPDP of described secret key memory is connected with the FPDP of described read-only memory, and the FPDP of described read-only memory is connected with the FPDP of described bus control unit.
Write data, load initial key to data storage, buffer uses as buffer.Data storage, crypto key memory are arranged in linear address space.Data storage but then needs to know key to read access without limits when data storage and register page or leaf are write data.Key two kinds of methods are installed, the one, data are copied to crypto key memory from buffer; The 2nd, current key and buffer content are through generating new key after the computing.Key can not directly read, and has only the SHA engine can visit it, and computing information is identified sign indicating number MAC.
Further, described bus adapter also comprises usb circuit, and described usb circuit is connected with the FPDP of described dsp processor.Advantages such as described usb circuit bus has high-speed transfer, supports hot plug, plug and play, development cost are low.
The beneficial effects of the utility model are:
Employing has the dsp processor of automatic encrypted circuit, can make data storage and transmission safety and reliability.Adopt usb circuit, advantages such as making the adaptive group of bus utensil that high-speed transfer be arranged, support hot plug, plug and play, development cost are low.
Description of drawings
Fig. 1 is that the utility model is based on the structured flowchart of the bus adapter of DSP;
Fig. 2 is the structured flowchart of the utility model dsp processor.
Embodiment
The utility model is described in further detail below in conjunction with drawings and the specific embodiments:
As shown in Figure 1, the utility model is based on the bus adapter of DSP, comprise dsp processor, the network communication card, serial storage and RJ-11 circuit, the FPDP of described dsp processor respectively with the FPDP of described network communication card, the FPDP of serial storage is connected with described RJ-11 circuit, described dsp processor comprises bus control unit, read-only memory, data encryptor, memory, CRC16 algorithm generator, buffer, data storage and secret key memory, the FPDP of described bus control unit is connected with the FPDP of described data encryptor, the FPDP of described data encryptor respectively with the FPDP of described buffer, the FPDP of the FPDP of described CRC16 algorithm generator and the FPDP of described data storage and described secret key memory is connected, the FPDP of described CRC16 algorithm generator and the FPDP of described data storage are connected, the FPDP of described buffer respectively with the FPDP of described data storage, the FPDP of described secret key memory is connected with the FPDP of described read-only memory, and the FPDP of described read-only memory is connected with the FPDP of described bus control unit.
Write data, load initial key to data storage, buffer uses as buffer.Data storage, crypto key memory are arranged in linear address space.Data storage but then needs to know key to read access without limits when data storage and register page or leaf are write data.Key two kinds of methods are installed, the one, data are copied to crypto key memory from buffer; The 2nd, current key and buffer content are through generating new key after the computing.Key can not directly read.
As shown in Figure 1, described bus adapter also comprises usb circuit, and described usb circuit is connected with the FPDP of described dsp processor.Advantages such as described usb circuit bus has high-speed transfer, supports hot plug, plug and play, development cost are low.
Claims (2)
1. bus adapter based on DSP, it is characterized in that: comprise dsp processor, the network communication card, serial storage and RJ-11 circuit, the FPDP of described dsp processor respectively with the FPDP of described network communication card, the FPDP of serial storage is connected with described RJ-11 circuit, described dsp processor comprises bus control unit, read-only memory, data encryptor, memory, CRC16 algorithm generator, buffer, data storage and secret key memory, the FPDP of described bus control unit is connected with the FPDP of described data encryptor, the FPDP of described data encryptor respectively with the FPDP of described buffer, the FPDP of the FPDP of described CRC16 algorithm generator and the FPDP of described data storage and described secret key memory is connected, the FPDP of described CRC16 algorithm generator and the FPDP of described data storage are connected, the FPDP of described buffer respectively with the FPDP of described data storage, the FPDP of described secret key memory is connected with the FPDP of described read-only memory, and the FPDP of described read-only memory is connected with the FPDP of described bus control unit.
2. the bus adapter based on DSP according to claim 1, it is characterized in that: described bus adapter also comprises usb circuit, described usb circuit is connected with the FPDP of described dsp processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320105227 CN203166964U (en) | 2013-03-08 | 2013-03-08 | DSP-based buss adaptor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320105227 CN203166964U (en) | 2013-03-08 | 2013-03-08 | DSP-based buss adaptor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203166964U true CN203166964U (en) | 2013-08-28 |
Family
ID=49028116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320105227 Expired - Fee Related CN203166964U (en) | 2013-03-08 | 2013-03-08 | DSP-based buss adaptor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203166964U (en) |
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2013
- 2013-03-08 CN CN 201320105227 patent/CN203166964U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130828 Termination date: 20140308 |