CN203165430U - Display device - Google Patents
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- CN203165430U CN203165430U CN 201320009775 CN201320009775U CN203165430U CN 203165430 U CN203165430 U CN 203165430U CN 201320009775 CN201320009775 CN 201320009775 CN 201320009775 U CN201320009775 U CN 201320009775U CN 203165430 U CN203165430 U CN 203165430U
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- 238000012549 training Methods 0.000 claims abstract description 156
- 230000005540 biological transmission Effects 0.000 claims abstract description 77
- 238000012545 processing Methods 0.000 claims abstract description 26
- 238000011084 recovery Methods 0.000 description 5
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- 238000005401 electroluminescence Methods 0.000 description 1
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Abstract
The utility model relates to a display device. The display device comprises a time sequence control circuit, a first data driving circuit, a second data driving circuit and a display panel, wherein the time sequence control circuit comprises a data processing circuit, a first encoder, a second encoder and an embedded clock controller. The first encoder outputs first initial training data and first main body transmission data to the first data driving circuit. The second encoder outputs second initial training data and second main transmission data to the second data driving circuit. The first data driving circuit receives the first main body transmission data after completing clock training according to the first initial training data. The second data driving circuit receives the second main body transmission data after completing the clock training according to the second initial training data. The display device has less electromagnetic interference.
Description
Technical field
The utility model relates to a kind of display device.
Background technology
Existing display device generally includes a plurality of for the functional circuit that drives display panel, and as sequential control circuit, data drive circuit and scan drive circuit, these circuit generally exist in the mode of integrated circuit (IC) chip.Need because driving, need to carry out data transmission between the functional circuit, yet, because the frequency of operation of each functional circuit is fixed and be higher, cause existing in the data transmission procedure bigger electromagnetic interference (EMI).For the circuit framework of embedded clock data point-to-point (Clock Embedded Point to Point) transmission, because frequency of operation is higher, the phenomenon of electromagnetic interference (EMI) is more serious especially.
The utility model content
For solving the problem of the electromagnetic interference (EMI) that the prior art display device exists, be necessary to provide a kind of display device of improving electromagnetic interference (EMI).
A kind of display device, it comprises sequential control circuit, first data drive circuit, second data drive circuit and display panel, this sequential control circuit comprises data processing circuit, first scrambler, second scrambler and embedded clock controller, this data processing circuit is electrically connected this first scrambler respectively, this second scrambler and this embedded clock controller, this embedded clock controller is electrically connected this first scrambler and this second scrambler respectively, this first scrambler also is electrically connected this first data drive circuit, this second scrambler also is electrically connected this second data drive circuit, this first data drive circuit and this second data drive circuit are electrically connected this display panel respectively, the view data that this data processing circuit provides external circuit is handled and is exported first data-signal to the first scrambler and exports second data-signal to this second scrambler, this embedded clock controller produces different first clock signal and the second clock signals of frequency according to a reference clock signal, this first scrambler embeds this first clock signal in this first data-signal and exports the first embedded clock data to this first data drive circuit, this first embedded clock data comprises the first initial training data and first main body transmission data, this first data drive circuit is finished first clock training back with the frequency work of this first clock signal and is received this first main body transmission data according to these first initial training data, this second scrambler embeds this second clock signal in this second data-signal and exports the second embedded clock data to this second data drive circuit, this second embedded clock data comprises the second initial training data and second main body transmission data, and this second data drive circuit is finished second clock training back with the frequency work of this second clock signal and received this second main body transmission data according to these second initial training data.
A kind of display device, it comprises sequential control circuit, first data drive circuit, second data drive circuit and display panel, this sequential control circuit comprises data processing circuit, first scrambler, second scrambler and embedded clock controller, this data processing circuit is electrically connected this first scrambler respectively, this second scrambler and this embedded clock controller, this embedded clock controller is electrically connected this first scrambler and this second scrambler respectively, this first scrambler also is electrically connected this first data drive circuit, this second scrambler also is electrically connected this second data drive circuit, this first data drive circuit and this second data drive circuit are electrically connected this display panel respectively, this data processing circuit is handled outputting data signals to the view data that external circuit provides, this embedded clock controller produces different first clock signal and the second clock signals of frequency according to a reference clock signal, this first scrambler receives first clock signal and the first clock training data and this first clock signal is embedded this first clock training data and exports the first initial training data to this data drive circuit, this first data drive circuit is adjusted into the frequency of this first clock signal correspondence according to these first initial training data with frequency of operation, and then this first data drive circuit receives data-signal with the frequency of this first clock signal correspondence from this sequential control circuit; This second scrambler receives second clock signal and second clock training data and this second clock signal is embedded this second clock training data and exports the second initial training data to this data drive circuit, this second data drive circuit is adjusted into the frequency of this second clock signal correspondence according to these second initial training data with frequency of operation, and then this second data drive circuit receives data-signal with the frequency of this second clock signal correspondence from this sequential control circuit.
Particularly, this first data-signal comprises that the first clock training data and first main body show data, this embedded clock controller is also exported the first clock training and is controlled signal to this first scrambler, this first scrambler embeds this first clock signal under the control of this first clock training control signal and generates these first initial training data in this first clock training data, this first scrambler also embeds this first main body with this first clock signal and shows that generating this first main body in the data transmits data after this first data drive circuit is finished this first clock training, this first data drive circuit obtains this first clock signal to this first initial training data decoding and finishes this first clock training, thereby receives this first main body transmission data according to the frequency of this first clock signal.
Further, this second data-signal comprises that second clock training data and second main body show data, this embedded clock controller is also exported the second clock training and is controlled signal to this second scrambler, this second scrambler embeds this second clock signal under the control of this second clock training control signal and generates these second initial training data in this second clock training data, this second scrambler also embeds this second main body with this second clock signal and shows that generating this second main body in the data transmits data after this second data drive circuit is finished the clock training, this second data drive circuit is to this second initial training data decoding and obtain this second clock signal finishing the training of this second clock, thereby receives this second main body transmission data according to the frequency of this second clock signal.
Further, this first data drive circuit is exported first feedback signal to this embedded clock controller after finishing this first clock training; This second data drive circuit is after finishing this second clock training, export second feedback signal to this embedded clock controller, this embedded clock controller is controlled this scrambler according to this first and second feedback signal and is exported these first main body transmission data and this second main body transmission data.
Preferably, this display panel this first and the driving of this second data drive circuit under display frame, this display panel comprises the normal display time interval that shows every frame picture and the vacant period of adjacent two frame pictures, this first clock training data and this second clock training data are to data that should the vacant period, and these first main body transmission data and this second main body transmission data are to the normal data of display time interval.
In one embodiment, thus the view data that this data processing circuit also provides external circuit handle produce and the output reference clock signal to this embedded clock controller.
Further, in one embodiment, this display device also comprises the 3rd data drive circuit and the 4th data drive circuit, this sequential control circuit also comprises the 3rd scrambler and the 4th scrambler, the 3rd scrambler connects this data processing circuit, this embedded clock controller and the 3rd data drive circuit, the 3rd data-signal and the 4th data-signal are handled and exported to the view data that this data processing circuit also further provides external circuit, the 3rd data-signal is provided to the 3rd scrambler, the 4th data-signal is provided to the 4th scrambler, this embedded clock controller also produces the 3rd clock signal and the 4th clock signal according to this reference clock signal, this is first years old, second, the frequency of the 3rd and the 4th clock signal has nothing in common with each other, the 3rd scrambler also embeds the 3rd clock signal in the 3rd data-signal and exports the 3rd embedded clock data to the 3rd data drive circuit, the 3rd embedded clock data comprises the 3rd initial training data and the 3rd main body transmission data, the 3rd data drive circuit is finished the back frequency with the 3rd clock signal of the 3rd clock training according to the 3rd initial training data and is received the 3rd main body transmission data, the 4th scrambler embeds the 4th clock signal in the 4th data-signal and exports the 4th embedded clock data to the 4th data drive circuit, the 4th embedded clock data comprises the 4th initial training data and the 4th main body transmission data, and then the 4th data drive circuit is finished the 4th clock training back according to the 4th initial training data and received the 4th main body with the frequency of the 4th clock signal and transmit data.
Further, in the above-described embodiments, the 3rd clock training data and the 4th clock training data include data that should the vacant period, the 3rd main body transmission data and the 4th main body transmission data include the normal data of display time interval, and it is the picture data of four viewing areas of this display panel that this first, second, third and the 4th main body is transmitted data.
In addition, the frequency that defines this reference clock signal is f, and the frequency of this first clock signal and this second clock signal is all more than or equal to f*90% but be less than or equal within the scope of f*110%.
Compared with prior art, in the display device of the present utility model, this first data drive circuit is finished the first clock training by the first initial training data are provided, thereby with the frequency work of first clock signal and receive this first main body transmission data, and this second data drive circuit is finished the second clock training by the second initial training data are provided, thereby with the frequency work of second clock signal and receive this second main body transmission data, make that needed these the first main bodys transmission data of two data driving circuits and this second main body transmission data can be with different frequency transmission, improve the electromagnetic interference (EMI) phenomenon that the transmission mode of fixed frequency causes.
Description of drawings
Fig. 1 is the circuit block diagram of the utility model display device one preferred embodiments.
The main element symbol description
First data drive circuit 121
Second data drive circuit 122
The 3rd data drive circuit 123
The 4th data drive circuit 124
First scrambler 114
The 3rd scrambler 116
The 4th scrambler 117
Embedded clock controller 112
Viewing area 131,132,133,134
Following embodiment will further specify the utility model in conjunction with above-mentioned accompanying drawing.
Embodiment
See also Fig. 1, Fig. 1 is the circuit block diagram of the utility model display device 10 1 preferred embodiments.This display device 10 can be liquid crystal indicator, organic electroluminescence display device and method of manufacturing same etc., and it comprises sequential control circuit 11, first data drive circuit 121, second data drive circuit 122, the 3rd data drive circuit 123, the 4th data drive circuit 124, reaches display panel 13.This sequential control circuit 11 comprises data processing circuit 110, first scrambler 114, second scrambler 115, the 3rd scrambler 116, the 4th scrambler 117 and embedded clock controller 112.This display panel 13 can be display panels, it comprise four with these four data driving circuits viewing area 131,132,133,134 one to one.In the present embodiment, first to fourth viewing area constitutes the complete viewing area of this display panel 13.Be appreciated that the quantity of quantity, scrambler of these display device 10 contained data drive circuits and the quantity of correspondingly dividing the viewing area can change as required, are not limited to describe in the present embodiment.
This data processing circuit 110 is electrically connected this first to fourth scrambler 114-117 and this embedded clock controller 112.This embedded clock controller 112 is electrically connected this first scrambler 114, second scrambler 115, the 3rd scrambler 116 and the 4th scrambler 117.This first scrambler 114 also is electrically connected this first data drive circuit 121, this first data drive circuit 121 is electrically connected this display panel 13, be used for outputting drive voltage to this viewing area 131, in addition, this first data drive circuit 121 also is electrically connected this embedded clock controller 112.Signal transmission interface between this sequential control circuit 11 and this first data drive circuit 121 can be the transmission interface (Clock Embedded Point to Point Interface) of embedded clock point-to-point.This sequential control circuit 11 can be an integrated circuit (IC) chip, and this first data drive circuit 121 also can be an integrated circuit (IC) chip.
Further, this second scrambler 115 also is electrically connected this second data drive circuit 122, this second data drive circuit 122 is electrically connected this display panel 13, be used for outputting drive voltage to this viewing area 132, in addition, this second data drive circuit 122 also is electrically connected this embedded clock controller 112.Signal transmission interface between this sequential control circuit 11 and this second data drive circuit 122 also can be the transmission interface of embedded clock point-to-point.This second data drive circuit 122 also can be an integrated circuit (IC) chip.
Further, the 3rd scrambler 116 also is electrically connected the 3rd data drive circuit 123, the 3rd data drive circuit 123 is electrically connected this display panel 13, be used for outputting drive voltage to this viewing area 133, in addition, the 3rd data drive circuit 123 also is electrically connected this embedded clock controller 112.Signal transmission interface between this sequential control circuit 11 and the 3rd data drive circuit 123 also can be the transmission interface of embedded clock point-to-point.The 3rd data drive circuit 123 also can be an integrated circuit (IC) chip.
Further, the 4th scrambler 117 also is electrically connected the 4th data drive circuit 124, the 4th data drive circuit 124 is electrically connected this display panel 13, be used for outputting drive voltage to this viewing area 134, in addition, the 4th data drive circuit 124 also is electrically connected this embedded clock controller 112.Signal transmission interface between this sequential control circuit 11 and the 4th data drive circuit 124 also can be the transmission interface of embedded clock point-to-point.The 4th data drive circuit 124 also can be an integrated circuit (IC) chip.
Wherein, this data processing circuit 110 receives view data that external circuits (as: scale controller, Scale Controller) provide and this view data is handled.Particularly, this data processing circuit 110 can be deciphered this view data and obtain reference clock signal, first data-signal, second data-signal, the 3rd data-signal, the 4th data-signal.And, these data processing circuit 110 these reference clock signals of output are to this embedded clock controller 112, and export this first data-signal to this first scrambler 114, export this second data-signal to this second scrambler 115, export the 3rd data-signal to the 3rd scrambler 116, export the 4th data-signal to the 4th scrambler 117.Wherein, this first data-signal, second data-signal, the 3rd data-signal, the 4th data-signal can be to be output to this first to fourth scrambler 114,115,116,117 simultaneously in time.
This embedded clock controller 112 receives this reference clock signal, and produces first clock signal, second clock signal, the 3rd clock signal and the 4th clock signal according to this reference clock signal.Wherein, the frequency of this first clock signal, this second clock signal, the 3rd clock signal, the 4th clock signal has nothing in common with each other.The frequency that defines this reference clock signal is f, and preferably, this first clock signal, this second clock signal, the 3rd clock signal, the 4th clock signal are all more than or equal to f*90% but be less than or equal within the scope of f*110%.
This embedded clock controller 112 also produces the first clock training (Clock Training) control signal, second clock training control signal, the 3rd clock training control signal, reaches the 4th clock training control signal.And, this first clock signal and the first clock training control signal are provided to this first scrambler 114, this second clock signal and second clock training control signal are provided to this second scrambler 115, the 3rd clock signal and the 3rd clock training control signal are provided to the 3rd scrambler 116, the four clock signals and the 4th clock training control signal is provided to the 4th scrambler 117.
This first scrambler 114 embeds this first data-signal with this first clock signal and obtains the first embedded clock data, and this first embedded clock data is provided to this first data drive circuit 121.Wherein, this first embedded clock data comprises the first initial training data and first main body transmission data.This first data-signal comprises that the first clock training data and first main body show data.Particularly, this first scrambler 114 embeds this first clock training data with this first clock signal and obtains these first initial training data and export this first data drive circuit 121 under the control of this first clock training control signal.This first data drive circuit 121 receives the laggard row decoding of these first initial training data to recover this first clock signal and this first clock training data, wherein, this first data drive circuit 121 can comprise that (Clock Data Recovery, CDR) circuit is finished above-mentioned decoding and recovery for recovering clock signals.
Say that further this first data drive circuit 121 can obtain and adjust its frequency of operation and be the frequency of this first clock signal by the mode of clock training, and this first clock training data is temporary.After this first data drive circuit 121 obtains and adjusts its frequency of operation to be the frequency of this first clock signal (namely finishing first clock training back), this first data drive circuit, 121 outputs, first feedback signal is to this embedded clock controller 112.
This second scrambler 115 embeds this second data-signal with this second clock signal and obtains the second embedded clock data, and this second embedded clock data is provided to this second data drive circuit 122.Wherein, this second embedded clock data comprises the second initial training data and second main body transmission data.This second data-signal comprises that second clock training data and second main body show data.Particularly, this second scrambler 115 embeds this second clock training data with this second clock signal and obtains these second initial training data and export this second data drive circuit 122 under the control of this second clock training control signal.This second data drive circuit 122 receives the laggard row decoding of these second initial training data to recover this second clock signal and this second clock training data, wherein, this second data drive circuit 122 can comprise for the recovering clock signals circuit and finishes above-mentioned decoding and recovery.
Say that further this second data drive circuit 122 can obtain and adjust its frequency of operation and be the frequency of this second clock signal by the mode of clock training, and this second clock training data is temporary.After this second data drive circuit 122 obtains and adjusts its frequency of operation to be the frequency of this second clock signal (namely finishing second clock training back), this second data drive circuit, 122 outputs, second feedback signal is to this embedded clock controller 112.
The 3rd scrambler 116 embeds the 3rd data-signal with the 3rd clock signal and obtains the 3rd embedded clock data, and the 3rd embedded clock data is provided to the 3rd data drive circuit 123.Wherein, the 3rd embedded clock data comprises the 3rd initial training data and the 3rd main body transmission data.The 3rd data-signal comprises that the 3rd clock training data and the 3rd main body show data.Particularly, the 3rd scrambler 116 embeds the 3rd clock training data with the 3rd clock signal and obtains the 3rd initial training data and export the 3rd data drive circuit 123 under the control of the 3rd clock training control signal.The 3rd data drive circuit 123 receives the laggard row decoding of the 3rd initial training data to recover the 3rd clock signal and the 3rd clock training data, wherein, the 3rd data drive circuit 123 can comprise for the recovering clock signals circuit and finishes above-mentioned decoding and recovery.
Say that further the 3rd data drive circuit 123 can obtain and adjust its frequency of operation and be the frequency of this first clock signal by the mode of clock training, and this first clock training data is temporary.After the 3rd data drive circuit 123 obtains and adjusts its frequency of operation to be the frequency of the 3rd clock signal (namely finishing the 3rd clock training back), the 3rd data drive circuit 123 outputs the 3rd feedback signal is to this embedded clock controller 112.
The 4th scrambler 117 embeds the 4th data-signal with the 4th clock signal and obtains the 4th embedded clock data, and the 4th embedded clock data is provided to the 4th data drive circuit 124.Wherein, the 4th embedded clock data comprises the 4th initial training data and the 4th main body transmission data.The 4th data-signal comprises that the 4th clock training data and the 4th main body show data.Particularly, the 4th scrambler 117 embeds the 4th clock training data with the 4th clock signal and obtains the 4th initial training data and export the 4th data drive circuit 124 under the control of the 4th clock training control signal.The 4th data drive circuit 124 receives the laggard row decoding of the 4th initial training data to recover the 4th clock signal and the 4th clock training data, wherein, the 4th data drive circuit 124 can comprise for the recovering clock signals circuit and finishes above-mentioned decoding and recovery.
Say that further the 4th data drive circuit 124 can obtain and adjust its frequency of operation and be the frequency of the 4th clock signal by the mode of clock training, and the 4th clock training data is temporary.After the 4th data drive circuit 124 obtains and adjusts its frequency of operation to be the frequency of the 4th clock signal (namely finishing the 4th clock training back), the 4th data drive circuit 124 outputs the 4th feedback signal is to this embedded clock controller 112.
When this first to fourth feedback signal all provides to this behind embedded clock controller 112, this embedded clock controller 112 stops to export this first clock training according to this first to fourth feedback signal and controls signal to this first scrambler 114 and stop to export the training of this second clock and control signal to this second scrambler 115, but continues this first clock signal of output to this first scrambler 114 and continue this second clock signal of output to this second scrambler 115.This first scrambler 114 embeds this first main body with this first clock signal and shows that generating this first main body in the data transmits data.This second scrambler 115 embeds this second main body with this second clock signal and shows that generating this second main body in the data transmits data.Simultaneously, this embedded clock controller 112 also stops to export the 3rd clock training according to this first to fourth feedback signal and controls signal to the 3rd scrambler 116 and stop to export the 4th clock training and control signal to the 4th scrambler 117, but continuation output the 3rd clock signal to the 3rd scrambler 116 and continuation output the 4th clock signal to the 4th scrambler 117, the three scramblers 116 embeds generation the 3rd main body transmission data in the 3rd main body demonstration data with the 3rd clock signal.The 4th scrambler 117 embeds the 4th main body with the 4th clock signal and shows that generating the 4th main body in the data transmits data.
Further, these first scrambler, 114 these first main bodys of output transfer data to this first data drive circuit 121.And then this first data drive circuit 121 receives this first main body transmission data with the frequency of this first clock signal.These second scrambler, 115 these second main bodys of output transfer data to this second data drive circuit 122.And then this second data drive circuit 122 receives this second main body transmission data with the frequency of this second clock signal.The 3rd scrambler 116 is also exported the 3rd main body and is transferred data to the 3rd data drive circuit 123.And then the 3rd data drive circuit 123 receives the 3rd main body transmission data with the frequency of the 3rd clock signal.The 4th scrambler 117 outputs the 4th main body transfers data to the 4th data drive circuit 124.And then the 4th data drive circuit 124 receives the 4th main body transmission data with the frequency of the 4th clock signal.Wherein, preferably, this first to fourth scrambler 114-117 exports this first to fourth main body transmission data simultaneously, so that this first to fourth data drive circuit 121-124 receives this first to fourth main body transmission data simultaneously.
After this first data drive circuit 121 receives these first main body transmission data, these first main body transmission data are deciphered to recover this first clock signal and this first main body demonstration data.First clock signal of recovering this moment is utilized to detect this first main body and shows whether the transmission time sequence of data is correct, as whether frequency and the phase place of utilizing this first clock signal to detect these first main body demonstration data have skew, when skew, carry out the correction of frequency and phase place.This first main body shows that data are also temporary by this first data drive circuit 121.
After this second data drive circuit 122 receives these second main body transmission data, these second main body transmission data are deciphered to recover this second clock signal and this second main body demonstration data.The second clock signal that recovers this moment is utilized to detect this second main body and shows whether the transmission time sequence of data is correct, as utilize this second main body of this second clock input to show whether frequency and the phase place of data have skew, when skew, carry out the correction of frequency and phase place.This second main body shows that data are also temporary by this second data drive circuit 122.
After the 3rd data drive circuit 123 receives the 3rd main body transmission data, the 3rd main body transmission data are deciphered to recover the 3rd clock signal and the 3rd main body demonstration data.The 3rd clock signal of recovering this moment is utilized to detect the 3rd main body and shows whether the transmission time sequence of data is correct, as whether frequency and the phase place of utilizing the 3rd clock signal to detect the 3rd main body demonstration data have skew, when skew, carry out the correction of frequency and phase place.The 3rd main body shows that data are also temporary by the 3rd data drive circuit 123.
After the 4th data drive circuit 124 receives the 4th main body transmission data, the 4th main body transmission data are deciphered to recover the 4th clock signal and the 4th main body demonstration data.The 4th clock signal of recovering this moment is utilized to detect the 4th main body and shows whether the transmission time sequence of data is correct, as whether frequency and the phase place of utilizing the 4th clock signal to detect the 4th main body demonstration data have skew, when skew, carry out the correction of frequency and phase place.The 4th main body shows that data are also temporary by the 4th data drive circuit 124.
Particularly, this first data drive circuit 121 can show that data are converted to gray scale voltage with the first clock training data and this first main body that obtains, and according to certain sequential this gray scale voltage is applied on the viewing area 131 of this display panel 13.This second data drive circuit 122 can show that data are converted to gray scale voltage with second clock training data and this second main body that obtains, and according to certain sequential this gray scale voltage is applied on the viewing area 132 of this display panel 13.The 3rd data drive circuit 123 can show that data are converted to gray scale voltage with the 3rd clock training data and the 3rd main body that obtains, and according to certain sequential this gray scale voltage is applied on the viewing area 133 of this display panel 13.The 4th data drive circuit 124 can show that data are converted to gray scale voltage with the 4th clock training data and the 4th main body that obtains, and according to certain sequential this gray scale voltage is applied on the viewing area 134 of this display panel 13.Wherein, these four viewing areas 131,132,133,134 are applied in gray scale voltage simultaneously.
Thereby four viewing areas of this display panel 13 all receive gray scale voltage carries out the picture demonstration.Wherein, this display panel 13 comprises the vacant period of (in other words before and after every frame picture) between the normal display time interval and adjacent two frame pictures that shows every frame picture, this the first, second, third and the 4th clock training data is data that should the vacant period, and the first, second, third and the 4th main body in these the first, second, third and the 4th main body transmission data shows that data are the normal data of display time interval.
Compared with prior art, in the utility model display device 10, this first data drive circuit is finished the first clock training by the first initial training data are provided, thereby with the frequency work of first clock signal and receive this first main body transmission data, and this second data drive circuit is finished the second clock training by the second initial training data are provided, thereby with the frequency work of second clock signal and receive this second main body transmission data, make that needed these the first main bodys transmission data of two data driving circuits and this second main body transmission data can be with different frequency transmission, improve the electromagnetic interference (EMI) phenomenon that the transmission mode of fixed frequency causes.
Be appreciated that in the change embodiment of display device shown in Figure 1 10, this display device 10 can comprise first and second data drive circuit 121 and 122, does not comprise the 3rd and the 4th data drive circuit 123 and 124; These sequential control circuit 11 correspondences closely comprise first and second scrambler 114 and 115, do not comprise the 3rd and the 4th scrambler 116 and 117; These display panel 13 correspondences comprise first and second viewing area 131 and 132, do not comprise the 3rd and the 4th viewing area 133 and 134.Wherein, this change embodiment's can the less display device 10 of corresponding surface board size.
In addition, need to prove, in above-mentioned each embodiment, basically, can also decipher timing control signals such as obtaining horizontal-drive signal and vertical synchronizing signal when 110 pairs of these view data of this data processing circuit are handled.This display device 10 may further include the scan drive circuit that is electrically connected between this sequential control circuit and this display panel, and this scan drive circuit receives this timing control signal (as vertical synchronizing signal) and exports a series of scanning voltages to this display panel.Each data drive circuit 121,122,123,124 also receives this timing control signal (as horizontal-drive signal) via corresponding codes device 114,115,116,117, is used for the sequential that this first and the 4th data drive circuit 121,122,123,124 of control is applied to the driving voltage of this display panel 13.This section relates to the basic display principles that content mostly is display device greatly, so the application is not described in detail this.
Claims (10)
1. display device, it comprises sequential control circuit, first data drive circuit, second data drive circuit and display panel, it is characterized in that: this sequential control circuit comprises data processing circuit, first scrambler, second scrambler and embedded clock controller, this data processing circuit is electrically connected this first scrambler respectively, this second scrambler and this embedded clock controller, this embedded clock controller is electrically connected this first scrambler and this second scrambler respectively, this first scrambler also is electrically connected this first data drive circuit, this second scrambler also is electrically connected this second data drive circuit, this first data drive circuit and this second data drive circuit are electrically connected this display panel respectively, the view data that this data processing circuit provides external circuit is handled and is exported first data-signal to the first scrambler and exports second data-signal to this second scrambler, this embedded clock controller produces different first clock signal and the second clock signals of frequency according to a reference clock signal, this first scrambler embeds this first clock signal in this first data-signal and exports the first embedded clock data to this first data drive circuit, this first embedded clock data comprises the first initial training data and first main body transmission data, this first data drive circuit is finished first clock training back with the frequency work of this first clock signal and is received this first main body transmission data according to these first initial training data, this second scrambler embeds this second clock signal in this second data-signal and exports the second embedded clock data to this second data drive circuit, this second embedded clock data comprises the second initial training data and second main body transmission data, and this second data drive circuit is finished second clock training back with the frequency work of this second clock signal and received this second main body transmission data according to these second initial training data.
2. display device as claimed in claim 1, it is characterized in that: this first data-signal comprises that the first clock training data and first main body show data, this embedded clock controller is also exported the first clock training and is controlled signal to this first scrambler, this first scrambler embeds this first clock signal under the control of this first clock training control signal and generates these first initial training data in this first clock training data, this first scrambler also embeds this first main body with this first clock signal and shows that generating this first main body in the data transmits data after this first data drive circuit is finished this first clock training, this first data drive circuit obtains this first clock signal to this first initial training data decoding and finishes this first clock training, thereby receives this first main body transmission data according to the frequency of this first clock signal.
3. display device as claimed in claim 2, it is characterized in that: this second data-signal comprises that second clock training data and second main body show data, this embedded clock controller is also exported the second clock training and is controlled signal to this second scrambler, this second scrambler embeds this second clock signal under the control of this second clock training control signal and generates these second initial training data in this second clock training data, this second scrambler also embeds this second main body with this second clock signal and shows that generating this second main body in the data transmits data after this second data drive circuit is finished the clock training, this second data drive circuit is to this second initial training data decoding and obtain this second clock signal finishing the training of this second clock, thereby receives this second main body transmission data according to the frequency of this second clock signal.
4. display device as claimed in claim 3 is characterized in that: this first data drive circuit is exported first feedback signal to this embedded clock controller after finishing this first clock training; This second data drive circuit is after finishing this second clock training, export second feedback signal to this embedded clock controller, this embedded clock controller is controlled this scrambler according to this first and second feedback signal and is exported these first main body transmission data and this second main body transmission data.
5. display device as claimed in claim 4, it is characterized in that: this display panel this first and the driving of this second data drive circuit under display frame, this display panel comprises the normal display time interval that shows every frame picture and the vacant period of adjacent two frame pictures, this first clock training data and this second clock training data are to data that should the vacant period, and these first main body transmission data and this second main body transmission data are to the normal data of display time interval.
6. display device as claimed in claim 1 is characterized in that: thus the view data that this data processing circuit also provides external circuit handle produce and the output reference clock signal to this embedded clock controller.
7. as any described display device of claim 1 to 6, it is characterized in that: this display device also comprises the 3rd data drive circuit and the 4th data drive circuit, this sequential control circuit also comprises the 3rd scrambler and the 4th scrambler, the 3rd scrambler connects this data processing circuit, this embedded clock controller and the 3rd data drive circuit, the 3rd data-signal and the 4th data-signal are handled and exported to the view data that this data processing circuit also further provides external circuit, the 3rd data-signal is provided to the 3rd scrambler, the 4th data-signal is provided to the 4th scrambler, this embedded clock controller also produces the 3rd clock signal and the 4th clock signal according to this reference clock signal, this is first years old, second, the frequency of the 3rd and the 4th clock signal has nothing in common with each other, the 3rd scrambler also embeds the 3rd clock signal in the 3rd data-signal and exports the 3rd embedded clock data to the 3rd data drive circuit, the 3rd embedded clock data comprises the 3rd initial training data and the 3rd main body transmission data, the 3rd data drive circuit is finished the back frequency with the 3rd clock signal of the 3rd clock training according to the 3rd initial training data and is received the 3rd main body transmission data, the 4th scrambler embeds the 4th clock signal in the 4th data-signal and exports the 4th embedded clock data to the 4th data drive circuit, the 4th embedded clock data comprises the 4th initial training data and the 4th main body transmission data, and then the 4th data drive circuit is finished the 4th clock training back according to the 4th initial training data and received the 4th main body with the frequency of the 4th clock signal and transmit data.
8. display device as claimed in claim 7, it is characterized in that: the 3rd clock training data and the 4th clock training data include data that should the vacant period, the 3rd main body transmission data and the 4th main body transmission data include the normal data of display time interval, and it is the picture data of four viewing areas of this display panel that this first, second, third and the 4th main body is transmitted data.
9. display device as claimed in claim 1, it is characterized in that: the frequency that defines this reference clock signal is f, the frequency of this first clock signal and this second clock signal is all more than or equal to f*90% but be less than or equal within the scope of f*110%.
10. display device, it comprises sequential control circuit, first data drive circuit, second data drive circuit and display panel, it is characterized in that: this sequential control circuit comprises data processing circuit, first scrambler, second scrambler and embedded clock controller, this data processing circuit is electrically connected this first scrambler respectively, this second scrambler and this embedded clock controller, this embedded clock controller is electrically connected this first scrambler and this second scrambler respectively, this first scrambler also is electrically connected this first data drive circuit, this second scrambler also is electrically connected this second data drive circuit, this first data drive circuit and this second data drive circuit are electrically connected this display panel respectively, this data processing circuit is handled outputting data signals to the view data that external circuit provides, this embedded clock controller produces different first clock signal and the second clock signals of frequency according to a reference clock signal, this first scrambler receives first clock signal and the first clock training data and this first clock signal is embedded this first clock training data and exports the first initial training data to this data drive circuit, this first data drive circuit is adjusted into the frequency of this first clock signal correspondence according to these first initial training data with frequency of operation, and then this first data drive circuit receives data-signal with the frequency of this first clock signal correspondence from this sequential control circuit; This second scrambler receives second clock signal and second clock training data and this second clock signal is embedded this second clock training data and exports the second initial training data to this data drive circuit, this second data drive circuit is adjusted into the frequency of this second clock signal correspondence according to these second initial training data with frequency of operation, and then this second data drive circuit receives data-signal with the frequency of this second clock signal correspondence from this sequential control circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW101225346U TWM486096U (en) | 2012-12-27 | 2012-12-27 | Display device |
| TW101225346 | 2012-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203165430U true CN203165430U (en) | 2013-08-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320009775 Expired - Lifetime CN203165430U (en) | 2012-12-27 | 2013-01-09 | Display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN203165430U (en) |
| TW (1) | TWM486096U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103903577B (en) * | 2012-12-27 | 2017-05-24 | 天钰科技股份有限公司 | Display device and driving method thereof, and data processing and output method of time sequence control circuit |
-
2012
- 2012-12-27 TW TW101225346U patent/TWM486096U/en not_active IP Right Cessation
-
2013
- 2013-01-09 CN CN 201320009775 patent/CN203165430U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103903577B (en) * | 2012-12-27 | 2017-05-24 | 天钰科技股份有限公司 | Display device and driving method thereof, and data processing and output method of time sequence control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TWM486096U (en) | 2014-09-11 |
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