CN203163860U - Automatic feed weighing apparatus - Google Patents
Automatic feed weighing apparatus Download PDFInfo
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- CN203163860U CN203163860U CN 201320129021 CN201320129021U CN203163860U CN 203163860 U CN203163860 U CN 203163860U CN 201320129021 CN201320129021 CN 201320129021 CN 201320129021 U CN201320129021 U CN 201320129021U CN 203163860 U CN203163860 U CN 203163860U
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Abstract
The utility model discloses an automatic feed weighing apparatus, which comprises a photoelectric switching circuit, a time delay circuit and an execution circuit. A signal output end of the photoelectric switching circuit is connected with a signal input end of the time delay circuit, and a signal output end of the time delay circuit is connected with a signal input end of the execution circuit. The photoelectric switching circuit comprises a first capacitor, a first resistor, a second resistor, a first diode and an emitter coupling trigger, wherein a first end of the first capacitor is connected with a first end of the first resistor, a cathode of the first diode is connected with the input end of the emitter coupling trigger, and a second end of the first capacitor is respectively connected with the anode of the first diode and a first end of the second resistor. By employing the technical scheme, the automatic feed weighing apparatus has the advantages including small metering error, high production efficiency and strong reliability.
Description
Technical field
The utility model relates to a kind of meausring apparatus, particularly relates to a kind of automatic feed meausring apparatus.
Background technology
In the batching production run, it is most important link that raw material is weighed.Therefore raw material weigh the precision of control and key component that reliability is whole batching control procedure its influenced the height of automaticity and the performance of overall process.The most outstanding shortcoming of like product is exactly that error in dipping is bigger in the market, can't guarantee that the quality of production is to the requirement of material metering error.Mostly the error in dipping of most of product description mark be ± 1%-2% gauging error in the environment for use of reality is big ± and 10% even higher.The meausring apparatus that feed proportioning system adopts is to adopt sensing technology, electronic technology and the integrated electronic scales of computer technology.The positive scale of electronics and Electronic Negative scale are that two kinds of electronic scale are dissimilar.The weighing technique that so-called positive scale is exactly general custom is along with being increased negative scale then with the minimizing that is claimed object weight by the reading of the increase scale of scale object weight, the reading of scale increases.Therefore the indication withdrawal rate also can be referred to as the discharging scale when it was usually used in discharge.What the positive scale type of electronics automatic doser adopted is that material enters the metering of scale body, and the Electronic Negative scale that other proportioning machine adopts to be material leave the metering of scale body.Yan Fa proportioning machine majority is continued to use designing a model of " promote material loading, batching certainly falling " at home, all adopts positive scale metering on measuring principle.In whole production technology, it is the most important to prepare burden.This just has higher requirement to weighing precision, and there are shortcomings such as the big and measuring error of power consumption is big in existing automatic feed weighing device.
The utility model content
The purpose of this utility model is the automatic feed meausring apparatus that a kind of simple to operate, low in energy consumption, stable performance is provided in order to address the above problem.
The utility model is achieved through the following technical solutions:
A kind of automatic feed meausring apparatus, comprise photoelectric switching circuit, delay circuit and executive circuit, the signal output part of described photoelectric switching circuit is connected with the signal input part of described delay circuit, the signal output part of described delay circuit is connected with the signal input part of described executive circuit, described photoelectric switching circuit comprises first electric capacity, first resistance, second resistance, first diode and emitter-coupled trigger, first end of described first electric capacity respectively with first end of described first resistance, the negative pole of first diode is connected with the input end of described emitter-coupled trigger, two ends of described first electric capacity are connected with the positive pole of described first diode and first end of described second resistance respectively, second end of described second resistance is connected with the discharge end of described emitter-coupled trigger, second end of described first resistance is connected with the power input of described emitter-coupled trigger, the earth terminal ground connection of described emitter-coupled trigger, the output terminal of described emitter-coupled trigger is connected with the input end of described delay circuit; Described executive circuit comprises the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, first relay, second relay, transistor seconds, the 3rd transistor, the 4th transistor, the 3rd diode, the 4th diode, pilot lamp and second phase inverter, first end of described the 7th resistance is connected with the output terminal of described delay circuit and the input end of described second phase inverter respectively, second end of described the 7th resistance is connected with the base stage of described transistor seconds, the collector of described transistor seconds is connected with first end of described first relay and the positive pole of described the 3rd diode respectively, second end of described first relay is connected with the negative pole of described the 3rd diode, the grounded emitter of described transistor seconds, the output terminal of described second phase inverter is connected with first end of described the 8th resistance, second end of described the 8th resistance is connected with the described the 3rd transistorized base stage, the described the 3rd transistorized collector respectively with the described the 4th transistorized collector, first end of second relay, the positive pole of the 4th diode connects, second end of described second relay is connected with first end of described pilot lamp and first end of described the tenth resistance respectively, second end of described pilot lamp is connected with the negative pole of second end of described the tenth resistance and described the 4th diode, the described the 3rd transistorized emitter is connected with the described the 4th transistorized base stage with first end of described the 9th resistance respectively, and second end of described the 9th resistance is connected back ground connection with the described the 4th transistorized emitter.
Further, described delay circuit comprises the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, second electric capacity, the 3rd electric capacity, second diode, the first transistor and first phase inverter, first end of described the 3rd resistance all is connected with the output terminal of described emitter-coupled trigger with the first input end of described first phase inverter, second end of described the 3rd resistance is connected with first end of described the 4th resistance, second end of described the 4th resistance respectively with first end of described the 5th resistance, first end of second electric capacity is connected with the negative pole of described second diode, second end of described the 5th resistance respectively with second end of described second electric capacity, first end of the 3rd electric capacity and the emitter of described the first transistor are connected back ground connection, the positive pole of described second diode is connected with second end of described the 3rd electric capacity and first end of described the 6th resistance respectively, second end of described the 6th resistance is connected with the base stage of described the first transistor, and the collector of described the first transistor is connected with second input end of described first phase inverter.
The beneficial effects of the utility model are:
The utility model adopts technique scheme, has advantages such as error in dipping is little, production high-level efficiency, good reliability.
Description of drawings
Fig. 1 is the circuit diagram of the utility model automatic feed meausring apparatus.
Embodiment
The utility model is described in further detail below in conjunction with drawings and the specific embodiments:
As shown in Figure 1, the utility model automatic feed meausring apparatus, comprise photoelectric switching circuit, delay circuit and executive circuit, the signal output part of described photoelectric switching circuit is connected with the signal input part of described delay circuit, the signal output part of described delay circuit is connected with the signal input part of described executive circuit, described photoelectric switching circuit comprises first capacitor C 1, first resistance R 1, second resistance R 2, the first diode VD1 and emitter-coupled trigger IC, first end of described first capacitor C 1 respectively with first end of described first resistance R 1, the negative pole of the first diode VD1 is connected with the input end of described emitter-coupled trigger IC, two ends of described first capacitor C 1 are connected with the positive pole of the described first diode VD1 and first end of described second resistance R 2 respectively, second end of described second resistance R 2 is connected with the discharge end of described emitter-coupled trigger IC, second end of described first resistance R 1 is connected with the power input of described emitter-coupled trigger IC, the earth terminal ground connection of described emitter-coupled trigger IC, the output terminal of described emitter-coupled trigger IC is connected with the input end of described delay circuit; Described executive circuit comprises the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, first relay K 1, second relay K 2, transistor seconds VT2, the 3rd transistor VT3, the 4th transistor VT4, the 3rd diode VD3, the 4th diode VD4, pilot lamp H and the second phase inverter M2, first end of described the 7th resistance R 7 is connected with the output terminal of described delay circuit and the input end of the described second phase inverter M2 respectively, second end of described the 7th resistance R 7 is connected with the base stage of described transistor seconds VT2, the collector of described transistor seconds VT2 is connected with first end of described first relay K 1 and the positive pole of described the 3rd diode VD3 respectively, second end of described first relay K 1 is connected with the negative pole of described the 3rd diode VD3, the grounded emitter of described transistor seconds VT2, the output terminal of the described second phase inverter M2 is connected with first end of described the 8th resistance R 8, second end of described the 8th resistance R 8 is connected with the base stage of described the 3rd transistor VT3, the collector of described the 3rd transistor VT3 respectively with the collector of described the 4th transistor VT4, first end of second relay K 2, the positive pole of the 4th diode VD4 connects, second end of described second relay K 2 is connected with first end of described pilot lamp H and first end of described the tenth resistance R 10 respectively, second end of described pilot lamp H is connected with second end of described the tenth resistance R 10 and the negative pole of described the 4th diode VD4, the emitter of described the 3rd transistor VT3 is connected with first end of described the 9th resistance R 9 and the base stage of described the 4th transistor VT4 respectively, and second end of described the 9th resistance R 9 is connected back ground connection with the emitter of described the 4th transistor VT4.
Described delay circuit comprises the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, second capacitor C 2, the 3rd capacitor C 3, the second diode VD2, the first transistor VT1 and the first phase inverter M1, first end of described the 3rd resistance R 3 all is connected with the output terminal of described emitter-coupled trigger IC with the first input end of the described first phase inverter M1, second end of described the 3rd resistance R 3 is connected with first end of described the 4th resistance R 4, second end of described the 4th resistance R 4 respectively with first end of described the 5th resistance R 5, first end of second capacitor C 2 is connected with the negative pole of the described second diode VD2, second end of described the 5th resistance R 5 respectively with second end of described second capacitor C 2, first end of the 3rd capacitor C 3 is connected back ground connection with the emitter of described the first transistor VT1, the positive pole of the described second diode VD2 is connected with second end of described the 3rd capacitor C 3 and first end of described the 6th resistance R 6 respectively, second end of described the 6th resistance R 6 is connected with the base stage of described the first transistor VT1, and the collector of described the first transistor VT1 is connected with second input end of the described first phase inverter M1.
Claims (2)
1. automatic feed meausring apparatus, it is characterized in that: comprise photoelectric switching circuit, delay circuit and executive circuit, the signal output part of described photoelectric switching circuit is connected with the signal input part of described delay circuit, the signal output part of described delay circuit is connected with the signal input part of described executive circuit, described photoelectric switching circuit comprises first electric capacity, first resistance, second resistance, first diode and emitter-coupled trigger, first end of described first electric capacity respectively with first end of described first resistance, the negative pole of first diode is connected with the input end of described emitter-coupled trigger, two ends of described first electric capacity are connected with the positive pole of described first diode and first end of described second resistance respectively, second end of described second resistance is connected with the discharge end of described emitter-coupled trigger, second end of described first resistance is connected with the power input of described emitter-coupled trigger, the earth terminal ground connection of described emitter-coupled trigger, the output terminal of described emitter-coupled trigger is connected with the input end of described delay circuit; Described executive circuit comprises the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, first relay, second relay, transistor seconds, the 3rd transistor, the 4th transistor, the 3rd diode, the 4th diode, pilot lamp and second phase inverter, first end of described the 7th resistance is connected with the output terminal of described delay circuit and the input end of described second phase inverter respectively, second end of described the 7th resistance is connected with the base stage of described transistor seconds, the collector of described transistor seconds is connected with first end of described first relay and the positive pole of described the 3rd diode respectively, second end of described first relay is connected with the negative pole of described the 3rd diode, the grounded emitter of described transistor seconds, the output terminal of described second phase inverter is connected with first end of described the 8th resistance, second end of described the 8th resistance is connected with the described the 3rd transistorized base stage, the described the 3rd transistorized collector respectively with the described the 4th transistorized collector, first end of second relay, the positive pole of the 4th diode connects, second end of described second relay is connected with first end of described pilot lamp and first end of described the tenth resistance respectively, second end of described pilot lamp is connected with second end of described the tenth resistance and the negative pole of described the 4th diode respectively, the described the 3rd transistorized emitter is connected with the described the 4th transistorized base stage with first end of described the 9th resistance respectively, and second end of described the 9th resistance is connected back ground connection with the described the 4th transistorized emitter.
2. automatic feed meausring apparatus according to claim 1, it is characterized in that: described delay circuit comprises the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, second electric capacity, the 3rd electric capacity, second diode, the first transistor and first phase inverter, first end of described the 3rd resistance all is connected with the output terminal of described emitter-coupled trigger with the first input end of described first phase inverter, second end of described the 3rd resistance is connected with first end of described the 4th resistance, second end of described the 4th resistance respectively with first end of described the 5th resistance, first end of second electric capacity is connected with the negative pole of described second diode, second end of described the 5th resistance respectively with second end of described second electric capacity, first end of the 3rd electric capacity and the emitter of described the first transistor are connected back ground connection, the positive pole of described second diode is connected with second end of described the 3rd electric capacity and first end of described the 6th resistance respectively, second end of described the 6th resistance is connected with the base stage of described the first transistor, and the collector of described the first transistor is connected with second input end of described first phase inverter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320129021 CN203163860U (en) | 2013-03-21 | 2013-03-21 | Automatic feed weighing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320129021 CN203163860U (en) | 2013-03-21 | 2013-03-21 | Automatic feed weighing apparatus |
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| Publication Number | Publication Date |
|---|---|
| CN203163860U true CN203163860U (en) | 2013-08-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320129021 Expired - Fee Related CN203163860U (en) | 2013-03-21 | 2013-03-21 | Automatic feed weighing apparatus |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104061991A (en) * | 2013-03-21 | 2014-09-24 | 成都瑞途电子有限公司 | Automatic feedstock weighing device |
| CN104655250A (en) * | 2015-02-25 | 2015-05-27 | 成都瑞途电子有限公司 | Extruding feeding type batching scale provided with multiple feeding channels |
-
2013
- 2013-03-21 CN CN 201320129021 patent/CN203163860U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104061991A (en) * | 2013-03-21 | 2014-09-24 | 成都瑞途电子有限公司 | Automatic feedstock weighing device |
| CN104655250A (en) * | 2015-02-25 | 2015-05-27 | 成都瑞途电子有限公司 | Extruding feeding type batching scale provided with multiple feeding channels |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130828 Termination date: 20140321 |