CN203135941U - RJ45 interface having clock synchronization system - Google Patents
RJ45 interface having clock synchronization system Download PDFInfo
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- CN203135941U CN203135941U CN 201320035000 CN201320035000U CN203135941U CN 203135941 U CN203135941 U CN 203135941U CN 201320035000 CN201320035000 CN 201320035000 CN 201320035000 U CN201320035000 U CN 201320035000U CN 203135941 U CN203135941 U CN 203135941U
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- pair feeder
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Abstract
The utility model belongs to the data transmission device technology field, relates to an RJ45 interface and especially relates to the RJ45 interface having a clock synchronization system. The RJ45 interface having the clock synchronization system comprises an interface body (1) and eight twisted pair wires (2) arranged on the interface body (1), wherein a first twisted pair wire (21), a second twisted pair wire (22), a third twisted pair wire (23) and a sixth twisted pair wire (26) are twisted pair wires used for transmitting Ethernet signals, a seventh twisted pair wire (27) and an eight twisted pair wire (28) are a clock sending interface and a clock receiving interface and are respectively connected with a clock extraction circuit. Free pins in the RJ45 interface are utilized to send and receive clock signals, quantity of interfaces and wires on a panel is reduced, user operation is simplified, cost is reduced, moreover, a clock synchronization function can be further realized, so the clock sending interface and the clock receiving interface are not needed to arrange additionally. The RJ45 interface having the clock synchronization system has excellent application prospects in the data transmission device technology field.
Description
Technical field
The utility model belongs to the data transmission device technical field, relates to a kind of RJ45 interface, relates in particular to a kind of RJ45 interface with clock system.
Background technology
RJ45 is a common name, refers to the 1. standardization by IEC (60) 603-7, uses modular jack or plug by 8 positions (8 pin) of international connector standard definition.The quick ethernet technology of most widely used 10M/100M self adaptation in the consumption market at present, physical connection is based on twisted-pair feeder and RJ45 interface, and wherein twisted-pair feeder connects the 2. line termination mode of standard code of ANSI/TIA/EIA-568-B of following.
3. EIA-485 (claims RS-485 or RS485 again) is to be under the jurisdiction of the osi model physical layer, and electrical characteristic is defined as 2 lines, half-duplex, the standard of multi-point.It provides data communication rates at a high speed.EIA-485 uses twisted-pair feeder to carry out the transmission of high voltage differential balance-dividing, and it can grow Distance Transmission.
Wherein, 1. IEC (60) 603-7 is ISO/IEC 11801(International Standards titled Generic Cabling for Customer Premises Cabling " international comprehensive wiring standard ") in, the normative reference of connection hardware.ISO/IEC 11801 is by ISO(International Standards Organization) with IEC(International Electrotechnical Commission) JTC1/SC 25 of joint committee (Joint Technical Committee) that forms writes.RJ-45 also is ISO 8877 specified standard connectors.
2. ANSI/TIA/EIA-568-B namely: Commercial Building Telecommunications Wiring Standard " commercial building communication wires standard ".
3. TIA/EIA 485-A 2003 is Electrical Characteristics of Generators and Receivers for Use in Balanced Digital Multipoint Systems " electrical characteristic of transmitting-receiving node in the balance numeral multipoint system ".
The RJ45 interface is generally used for transfer of data, in order to transmit audio data stream at two equipment rooms by Ethernet, if sending the clock frequency of using, two equipment audio data streams have big difference, then the slow side of clock can only select initiatively discarded part divided data in the running, otherwise can cause its data buffering area to overflow.So, for the consideration that keeps data integrity, need transmit the clock frequency of 8000HZ at two equipment rooms.In the prior art, clock need be set separately send and receiving interface, can take location resource limited on the panel like this.
Have 8 pins in the RJ45 interface, all only used 4 identical pins when using several termination modes of ANSI/TIA/EIA-568-B regulation to transmit the quick Ethernet of 10M/100M self adaptation.
Summary of the invention
The purpose of this utility model is to overcome RJ45 interface of the prior art clock transmission and receiving interface need be set separately, take location resource limited on the panel, and have the defective that 8 pins do not take full advantage of in the RJ45 interface, a kind of RJ45 interface with clock system is provided, utilized the pin that does not have in the RJ45 interface to use to send and the receive clock signal, the quantity of interface and wiring on the minimizing panel, simplify user's operation, reduce cost, and can realize the function that clock is synchronous, do not need to arrange in addition clock and send and receiving interface.
In order to solve the problems of the technologies described above, the utility model is solved by following technical proposals:
A kind of RJ45 interface with clock system, comprise interface body, interface body is provided with eight twisted-pair feeders, be respectively first twisted-pair feeder, second twisted-pair feeder, the 3rd twisted-pair feeder, the 4th twisted-pair feeder, the 5th twisted-pair feeder, the 6th twisted-pair feeder, the 7th twisted-pair feeder and the 8th twisted-pair feeder, first twisted-pair feeder, second twisted-pair feeder, the 3rd twisted-pair feeder and the 6th twisted-pair feeder are the twisted-pair feeder of transmission ethernet signal, and the 7th twisted-pair feeder and the 8th twisted-pair feeder are that clock sends and receiving interface.
As preferably, the 7th twisted-pair feeder all is connected with clock extracting circuit with the 8th twisted-pair feeder.
The utility model provides a kind of RJ45 interface with clock system, utilized the pin that does not have in the RJ45 interface to use to send and the receive clock signal, the quantity of interface and wiring on the minimizing panel, simplify user's operation, reduce cost, and can realize the function that clock is synchronous, do not need to arrange in addition clock and send and receiving interface.In the data transmission device technical field, good prospects for application is arranged.
Description of drawings
Fig. 1 is a kind of structural representation with RJ45 interface of clock system described in the utility model.
Fig. 2 is annexation schematic diagram among the utility model embodiment.
Embodiment
Describe in further detail below in conjunction with accompanying drawing and the utility model of embodiment.
Embodiment
A kind of RJ45 interface with clock system, shown in Fig. 1 to 2, comprise interface body 1, interface body 1 is provided with eight twisted-pair feeders 2, be respectively first twisted-pair feeder 21, second twisted-pair feeder 22, the 3rd twisted-pair feeder 23, the 4th twisted-pair feeder 24, the 5th twisted-pair feeder 25, the 6th twisted-pair feeder 26, the 7th twisted-pair feeder 27 and the 8th twisted-pair feeder 28, first twisted-pair feeder 21, second twisted-pair feeder 22, the 3rd twisted-pair feeder 23 and the 6th twisted-pair feeder 26 are the twisted-pair feeder of transmission ethernet signal, and the 7th twisted-pair feeder 27 and the 8th twisted-pair feeder 28 send and receiving interface for clock.
The 7th twisted-pair feeder 27 all is connected with clock extracting circuit with the 8th twisted-pair feeder 28.
During use, all only use first twisted-pair feeder 21, second twisted-pair feeder 22, the 3rd twisted-pair feeder 23 and the 6th twisted-pair feeder 26 in the connection mode that ANSI/TIA/EIA-568-B uses, used the 7th twisted-pair feeder 27 and the 8th twisted-pair feeder 28 transmission clock frequencies.Clock signal adopts the EIA-485 standard, and this standard belongs to differential signal, and antijamming capability is strong, but transmitting range is long.Because transmitted frequency is lower, the EIA-485 antijamming capability is strong, so the interior original ethernet communication of RJ45 interface and initiate clock transfer system do not constitute interference mutually.Following or other occasions can further be used the 4th twisted- pair feeder 24 and 25 liang of core transmission clocks of the 5th twisted-pair feeder or other low speed and anti-energy interference signals according to demand.
As shown in Figure 2, two equipment connect by the 10/100M crossover network cables that meet the ANSI/TIA/EIA-568-B standard, first twisted-pair feeder 21, second twisted-pair feeder 22, the 3rd twisted-pair feeder 23 and the 6th twisted-pair feeder 26 these 4 cores are used for ethernet communication in its center line, the 7th twisted- pair feeder 27 and 28 liang of cores of the 8th twisted-pair feeder are used for using the EIA-485 standard to send the A machine to the clock signal of B machine, and ethernet signal is given different signal processing circuits respectively with the EIA-485 signal and communicated and clock extracting circuit behind connector.
In a word, the above only is preferred embodiment of the present utility model, and all equalizations of doing according to the utility model claim change and modify, and all should belong to the covering scope of the utility model patent.
Claims (2)
1. RJ45 interface with clock system, comprise interface body (1), interface body (1) is provided with eight twisted-pair feeders (2), be respectively first twisted-pair feeder (21), second twisted-pair feeder (22), the 3rd twisted-pair feeder (23), the 4th twisted-pair feeder (24), the 5th twisted-pair feeder (25), the 6th twisted-pair feeder (26), the 7th twisted-pair feeder (27) and the 8th twisted-pair feeder (28), first twisted-pair feeder (21), second twisted-pair feeder (22), the 3rd twisted-pair feeder (23) and the 6th twisted-pair feeder (26) are the twisted-pair feeder of transmission ethernet signal, it is characterized in that: the 7th twisted-pair feeder (27) and the 8th twisted-pair feeder (28) send and receiving interface for clock.
2. a kind of RJ45 interface with clock system according to claim 1, it is characterized in that: the 7th twisted-pair feeder (27) all is connected with clock extracting circuit with the 8th twisted-pair feeder (28).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320035000 CN203135941U (en) | 2013-01-21 | 2013-01-21 | RJ45 interface having clock synchronization system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320035000 CN203135941U (en) | 2013-01-21 | 2013-01-21 | RJ45 interface having clock synchronization system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203135941U true CN203135941U (en) | 2013-08-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320035000 Expired - Lifetime CN203135941U (en) | 2013-01-21 | 2013-01-21 | RJ45 interface having clock synchronization system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203135941U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107968777A (en) * | 2017-10-31 | 2018-04-27 | 清远恒成智道信息科技有限公司 | Network Security Monitor System |
-
2013
- 2013-01-21 CN CN 201320035000 patent/CN203135941U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107968777A (en) * | 2017-10-31 | 2018-04-27 | 清远恒成智道信息科技有限公司 | Network Security Monitor System |
| CN107968777B (en) * | 2017-10-31 | 2020-09-11 | 清远恒成智道信息科技有限公司 | Network security monitoring system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130814 |