CN203118006U - Ultrahigh-frequency RFID (radio frequency identification) reader - Google Patents
Ultrahigh-frequency RFID (radio frequency identification) reader Download PDFInfo
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- CN203118006U CN203118006U CN 201320137890 CN201320137890U CN203118006U CN 203118006 U CN203118006 U CN 203118006U CN 201320137890 CN201320137890 CN 201320137890 CN 201320137890 U CN201320137890 U CN 201320137890U CN 203118006 U CN203118006 U CN 203118006U
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Abstract
The utility model discloses an ultrahigh-frequency RFID (radio frequency identification) reader which comprises a radio frequency front end circuit and a central processor. The radio frequency front end circuit comprises a radio frequency signal transceiving circuit, a radio frequency signal receiving circuit, a radio frequency signal transmitting circuit and a frequency synthesizer. The radio frequency signal transceiving circuit comprises a transceiving antenna, an antenna switch and a circulator. The radio frequency signal transmitting circuit comprises a DAC (digital/analog convertor) circuit, a frequency mixer and a front end pre-amplifying circuit. The radio frequency signal receiving circuit comprises an ADC (analog/digital convertor) circuit, a frequency mixer and a low noise amplifying circuit. The ultrahigh-frequency RFID reader is simple in structure; and a base-band signal modulation/demodulation circuit is integrated into the central processor in a software and radio manner, so that the radio frequency front end circuit structure in the RFID reader is simplified, interference resisting capability of the reader is improved, and stability is enhanced.
Description
Technical field
The utility model relates to the reader technology field based on REID, relates in particular to a kind of ultrahigh frequency RFID reader.
Background technology
RFID reader, i.e. REID.RFID (Radio Frequency Identification, radio-frequency (RF) identification) technology is a kind of automatic identification technology that begins to rise the nineties in 20th century, it is that a kind of radiofrequency signal of utilizing is closed the transmission of (alternating magnetic field or electromagnetic field) realization non-contact type information by the space lotus root, and the information of passing through to transmit reaches the technology of automatic identifying purpose.Non-visual transmission, transmission speed are fast because this technology has, penetrability more by force, stronger anti-adverse environment ability and advantage such as reusable and extremely numerous industries and professional person's concern.Make a general survey of domestic and international rfid system, its basic comprising is RFID tag, radio-frequency identification reader and application layer software; Wherein the function of radio-frequency identification reader is to receive the command information of application layer, startup radio-frequency module wherein is with control antenna work, finish and the communicating by letter of radio-frequency (RF) tag, simultaneously the label information that recognizes is transferred to application layer for customer analysis and processing by communication interface.
Super high frequency radio frequency recognition technology (UHF RFID) is the intelligent identification technology that has using value and development prospect, and its working frequency range is 860-960MHz, and it is far away to have a decipherment distance, transmission speed is fast, bandwidth, advantage such as antenna size is little is the emphasis of the exploitation of RFID technical research both at home and abroad at present.Though UHF RFID has broadband properties, the label of 915MHz frequency is used widely at present, EPC Class 1 generation 2 standards are RFID standards of being set up cooperatively by North America UCC product Unified coding tissue and European EAN product standard tissue, its standard RFID label communication modulation system be ASK or PSK pattern, coded system is PIE, FM0 or Miller, message transmission rate is respectively 26.7-128kbps/PIE, 40-640kbps/FM0,40kbps/Miller, communication mode is half-duplex mode, and anti-collision algorithm adopts Slotted Aloha algorithm.EPC Class 1 generation 2 standards are an open standard, and reader need satisfy this standard.
The radio-frequency (RF) front-end circuit of traditional UHF RFID reader adopts digital baseband signal modulation and intermediate frequency filtering circuit, so just causes radio-frequency (RF) front-end circuit structure more complicated, and antijamming capability reduces, thereby influences the stability of RFID reader.
The utility model content
At the prior art above shortcomings, the purpose of this utility model just is to provide a kind of ultrahigh frequency RFID reader, can effectively solve radio-frequency (RF) front-end circuit structure more complicated in the existing RFID reader, and antijamming capability reduces, the problem of poor stability.
To achieve these goals, the technical solution adopted in the utility model is such: a kind of ultrahigh frequency RFID reader, comprise radio-frequency (RF) front-end circuit and central processing unit, it is characterized in that: described radio-frequency (RF) front-end circuit comprises radiofrequency signal transmission circuit, radiofrequency signal receiving circuit, emission of radio frequency signals circuit and frequency synthesizer;
Described radiofrequency signal transmission circuit comprises dual-mode antenna, antenna change-over switch and circulator; Described emission of radio frequency signals circuit comprises DAC circuit, frequency mixer and preposition pre-arcing road; Described radiofrequency signal receiving circuit comprises adc circuit, frequency mixer and low-noise amplification circuit;
Described circulator links to each other with low-noise amplification circuit with preposition pre-arcing road simultaneously; Low-noise amplification circuit links to each other with the radio frequency reception channel of central processing unit behind frequency mixer and adc circuit, and the radio-frequency transmissions passage of central processing unit links to each other with preposition pre-arcing road behind DAC circuit and frequency mixer; Described frequency synthesizer links to each other with frequency mixer in the emission of radio frequency signals circuit with the radiofrequency signal receiving circuit simultaneously behind discharge circuit.
The principle of work of radiofrequency signal receiving circuit is that the radiofrequency signal that will receive is carried out down-converted earlier, produced the local oscillation signal of 875MHz by frequency synthesizer, pass through amplifier then, enter the frequency mixer in the radiofrequency signal receiving circuit, carry out down coversion, obtain the intermediate-freuqncy signal of 40Mhz after the radiofrequency signal process frequency conversion with 915MHz, be sent to adc circuit through behind the simple filtering circuit then, wherein adc circuit comprises the ADC conversion chip, this ADC conversion chip adopts the AD9214 chip of analog company, its sampling clock is 80MHz, and sampling resolution is 10bit, then the digital signal after the AD conversion is input among the FPGA.
The principle of work of emission of radio frequency signals circuit is that the modulation of baseband signal is finished in the FPGA internal system, then it is converted to the 40MHz intermediate-freuqncy signal, the digital medium-frequency signal that FPGA is produced sends to the DAC circuit, described DAC circuit comprises the DAC chip, this DAC conversion chip adopts the AD9762 chip of analog company, the change over clock frequency is 125MHz, the conversion figure place is 12bit, carry out mixing through the local oscillation signal 875MHz that in frequency mixer, produces with frequency synthesizer behind the simple filtering circuit, and then pass the signal on the antenna after putting in advance through preposition.According to EPC Class 1 generation 2 standards, reader is operated in the half duplex communication pattern, and antenna change-over switch needs to be controlled by FPGA so, comes the control signal emission to receive according to reiving/transmitting state.
Further, described central processing unit adopts fpga chip.During concrete enforcement, adopt the XC6SLX16-2CSG324 fpga chip of XILINX company as the acp chip of digital baseband modulation, it has 14579 Logic Cells unit, the 136Kbit internal storage unit, consider from aspects such as programmable logic resource, data buffer memory, IP arithmetic elements all can satisfy the demands in 32 DSP48A1 algorithm process unit, this chip.
Further, described fpga chip has CPU, radio frequency reception channel and the radio-frequency transmissions passage of embedding; Described radio frequency reception channel comprises DDC circuit, cic filter, forming filter, FM0/Miller decoder module and the CRC16 verification module that links to each other successively, described CRC16 verification module links to each other with embedded type CPU, and described DDC circuit is used for from the adc circuit incoming radio frequency signal; Described radio-frequency transmissions passage comprises CRC5/16 verification module, PIE coding module, forming filter, UDC circuit and the bandpass filter that links to each other successively, embedded type CPU links to each other with CRC5/16 verification module, and after bandpass filter radiofrequency signal is sent to adc circuit.
Radio frequency reception channel is sent to data in the fpga chip after the ADC conversion, and the data after the ADC conversion are the 40MHz intermediate-freuqncy signal, the DDC circuit carries out a Digital Down Convert (DDC) again to the 40MHz digital medium-frequency signal that collects, be digital baseband signal through after the Digital Down Convert, carry out cic filter filtering then, then filtered signal being formed filtering handles, carry out the FM0/Miller decoding again, through allowing the interior CPU of FPGA sheet obtain related data after the CRC16 checking treatment.CPU will send to the data of label in the FPGA sheet, at first carry out the CRC5/16 coding checkout, then carry out the PIE coding, these coded programs are available HDL language or IP kernel realization all, using forming filter to carry out waveform filtering then is shaped, because the signal of this moment also is baseband signal, therefore also need to adopt Digital Up Convert circuit (UDC) that baseband signal is modulated to the digital intermediate frequency section of 40MHz, finally by crossing bandpass filter digital medium-frequency signal is carried out sending to outside DAC circuit after the filtering.
Compared with prior art, advantage of the present utility model is: simple in structure, utilize software and wireless mode to be integrated in the central processing unit baseband signal modulation-demodulation circuit, thereby simplified the radio-frequency (RF) front-end circuit structure in the RFID reader, and the antijamming capability of reader is reduced, and stability is better; Central processing unit adopts fpga chip, and is with low cost, further improve stability, and programmability is stronger, is more convenient for software is integrated in the chip, by software function replacement circuit module, thereby makes stability better, and circuit structure is simpler.
Description of drawings
Fig. 1 is circuit structure block diagram of the present utility model;
Fig. 2 is the structured flowchart of fpga chip in the utility model.
Embodiment
The utility model is described in further detail below in conjunction with drawings and Examples.
Embodiment: referring to Fig. 1 and Fig. 2, a kind of ultrahigh frequency RFID reader comprises radio-frequency (RF) front-end circuit and central processing unit, and described radio-frequency (RF) front-end circuit comprises radiofrequency signal transmission circuit, radiofrequency signal receiving circuit, emission of radio frequency signals circuit and frequency synthesizer.
Described radiofrequency signal transmission circuit comprises dual-mode antenna, antenna change-over switch and circulator; Described emission of radio frequency signals circuit comprises DAC circuit (D/A converting circuit), frequency mixer and preposition pre-arcing road (PA); Described radiofrequency signal receiving circuit comprises adc circuit (analog to digital conversion circuit), frequency mixer and low-noise amplification circuit (LNA).
Described circulator links to each other with low-noise amplification circuit with preposition pre-arcing road simultaneously; Low-noise amplification circuit links to each other with the radio frequency reception channel of central processing unit behind frequency mixer and adc circuit, and the radio-frequency transmissions passage of central processing unit links to each other with preposition pre-arcing road behind DAC circuit and frequency mixer; Described frequency synthesizer links to each other with frequency mixer in the emission of radio frequency signals circuit with the radiofrequency signal receiving circuit simultaneously behind discharge circuit.
The principle of work of radiofrequency signal receiving circuit is that the radiofrequency signal that will receive is carried out down-converted earlier, produced the local oscillation signal of 875MHz by frequency synthesizer, pass through amplifier then, enter the frequency mixer in the radiofrequency signal receiving circuit, carry out down coversion, obtain the intermediate-freuqncy signal of 40Mhz after the radiofrequency signal process frequency conversion with 915MHz, be sent to adc circuit through behind the simple filtering circuit then, wherein adc circuit comprises the ADC conversion chip, this ADC conversion chip adopts the AD9214 chip of analog company, its sampling clock is 80MHz, and sampling resolution is 10bit, then the digital signal after the AD conversion is input among the FPGA.
The principle of work of emission of radio frequency signals circuit is that the modulation of baseband signal is finished in the FPGA internal system, then it is converted to the 40MHz intermediate-freuqncy signal, the digital medium-frequency signal that FPGA is produced sends to the DAC circuit, described DAC circuit comprises the DAC chip, this DAC conversion chip adopts the AD9762 chip of analog company, its change over clock frequency is 125MHz, the conversion figure place is 12bit, carry out mixing through the local oscillation signal 875MHz that in frequency mixer, produces with frequency synthesizer behind the simple filtering circuit, and then pass the signal on the antenna after putting in advance through preposition.According to EPC Class 1 generation 2 standards, reader is operated in the half duplex communication pattern, and antenna change-over switch needs to be controlled by FPGA so, comes the control signal emission to receive according to reiving/transmitting state.
Described central processing unit adopts fpga chip.During concrete enforcement, adopt the XC6SLX16-2CSG324 fpga chip of XILINX company as the acp chip of digital baseband modulation, it has 14579 Logic Cells unit, the 136Kbit internal storage unit, consider from aspects such as programmable logic resource, data buffer memory, IP arithmetic elements all can satisfy the demands in 32 DSP48A1 algorithm process unit, this chip.
Described fpga chip has CPU, radio frequency reception channel and the radio-frequency transmissions passage of embedding; Described radio frequency reception channel comprises DDC circuit, cic filter, forming filter, FM0/Miller decoder module and the CRC16 verification module that links to each other successively, described CRC16 verification module links to each other with embedded type CPU, and described DDC circuit is used for from the adc circuit incoming radio frequency signal; Described radio-frequency transmissions passage comprises CRC5/16 verification module, PIE coding module, forming filter, UDC circuit and the bandpass filter that links to each other successively, embedded type CPU links to each other with CRC5/16 verification module, and after bandpass filter radiofrequency signal is sent to adc circuit.
Radio frequency reception channel is sent to data in the fpga chip after the ADC conversion, and the data after the ADC conversion are the 40MHz intermediate-freuqncy signal, Digital Up Convert circuit (DDC circuit) carries out a Digital Down Convert again to the 40MHz digital medium-frequency signal that collects, be digital baseband signal through after the Digital Down Convert, carry out cic filter filtering then, then filtered signal being formed filtering handles, carry out the FM0/Miller decoding again, through allowing the interior CPU of FPGA sheet obtain related data after the CRC16 checking treatment.CPU will send to the data of label in the FPGA sheet, at first carry out the CRC5/16 coding checkout, then carry out the PIE coding, these coded programs are available HDL language or IP kernel realization all, using forming filter to carry out waveform filtering then is shaped, because the signal of this moment also is baseband signal, therefore also need to adopt Digital Up Convert circuit (UDC circuit) that baseband signal is modulated to the digital intermediate frequency section of 40MHz, finally by crossing bandpass filter digital medium-frequency signal is carried out sending to outside DAC circuit after the filtering.
Need to prove at last, above embodiment is only in order to the technical solution of the utility model to be described but not the restriction technologies scheme, those of ordinary skill in the art is to be understood that, those are made amendment to the technical solution of the utility model or are equal to replacement, and do not break away from aim and the scope of the technical program, all should be encompassed in the middle of the claim scope of the present utility model.
Claims (3)
1. a ultrahigh frequency RFID reader comprises radio-frequency (RF) front-end circuit and central processing unit, it is characterized in that: described radio-frequency (RF) front-end circuit comprises radiofrequency signal transmission circuit, radiofrequency signal receiving circuit, emission of radio frequency signals circuit and frequency synthesizer;
Described radiofrequency signal transmission circuit comprises dual-mode antenna, antenna change-over switch and circulator; Described emission of radio frequency signals circuit comprises DAC circuit, frequency mixer and preposition pre-arcing road; Described radiofrequency signal receiving circuit comprises adc circuit, frequency mixer and low-noise amplification circuit;
Described circulator links to each other with low-noise amplification circuit with preposition pre-arcing road simultaneously; Low-noise amplification circuit links to each other with the radio frequency reception channel of central processing unit behind frequency mixer and adc circuit, and the radio-frequency transmissions passage of central processing unit links to each other with preposition pre-arcing road behind DAC circuit and frequency mixer; Described frequency synthesizer links to each other with frequency mixer in the emission of radio frequency signals circuit with the radiofrequency signal receiving circuit simultaneously behind discharge circuit.
2. a kind of ultrahigh frequency RFID reader according to claim 1 is characterized in that: described central processing unit employing fpga chip.
3. a kind of ultrahigh frequency RFID reader according to claim 2 is characterized in that: described fpga chip has CPU, radio frequency reception channel and the radio-frequency transmissions passage of embedding; Described radio frequency reception channel comprises DDC circuit, cic filter, forming filter, FM0/Miller decoder module and the CRC16 verification module that links to each other successively, described CRC16 verification module links to each other with embedded type CPU, and described DDC circuit is used for from the adc circuit incoming radio frequency signal; Described radio-frequency transmissions passage comprises CRC5/16 verification module, PIE coding module, forming filter, UDC circuit and the bandpass filter that links to each other successively, embedded type CPU links to each other with CRC5/16 verification module, and after bandpass filter radiofrequency signal is sent to adc circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320137890 CN203118006U (en) | 2013-03-25 | 2013-03-25 | Ultrahigh-frequency RFID (radio frequency identification) reader |
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| CN 201320137890 CN203118006U (en) | 2013-03-25 | 2013-03-25 | Ultrahigh-frequency RFID (radio frequency identification) reader |
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| CN203118006U true CN203118006U (en) | 2013-08-07 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104636695A (en) * | 2015-01-14 | 2015-05-20 | 无锡威盛信息技术有限公司 | RFID (radio frequency identification) reader system |
| CN105631380A (en) * | 2015-12-22 | 2016-06-01 | 上海爱信诺航芯电子科技有限公司 | Magnetic stripe card data decoding circuit and decoding method thereof |
| CN106127091A (en) * | 2016-06-30 | 2016-11-16 | 天津工业大学 | A kind of intelligent UHFRFID reader based on DSP |
| CN106372553A (en) * | 2016-08-30 | 2017-02-01 | 成都九洲电子信息系统股份有限公司 | Pipeline matrix algorithm based on GJB radio frequency identification technology |
| CN106919880A (en) * | 2015-12-28 | 2017-07-04 | 北京聚利科技股份有限公司 | Radiofrequency signal audiomonitor |
| CN108809362A (en) * | 2018-07-17 | 2018-11-13 | 中国船舶重工集团公司第七〇九研究所 | A kind of wide bandwidth SAW reader emitter and its method |
| CN110414287A (en) * | 2019-07-26 | 2019-11-05 | 浙江大华技术股份有限公司 | A kind of modulation depth method of adjustment and device |
| CN112733979A (en) * | 2020-12-25 | 2021-04-30 | 重庆电子工程职业学院 | Safety protection device of RFID read-write equipment |
-
2013
- 2013-03-25 CN CN 201320137890 patent/CN203118006U/en not_active Expired - Fee Related
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104636695A (en) * | 2015-01-14 | 2015-05-20 | 无锡威盛信息技术有限公司 | RFID (radio frequency identification) reader system |
| CN104636695B (en) * | 2015-01-14 | 2018-03-13 | 无锡威盛信息技术有限公司 | RFID Reader systems |
| CN105631380A (en) * | 2015-12-22 | 2016-06-01 | 上海爱信诺航芯电子科技有限公司 | Magnetic stripe card data decoding circuit and decoding method thereof |
| CN106919880A (en) * | 2015-12-28 | 2017-07-04 | 北京聚利科技股份有限公司 | Radiofrequency signal audiomonitor |
| CN106127091A (en) * | 2016-06-30 | 2016-11-16 | 天津工业大学 | A kind of intelligent UHFRFID reader based on DSP |
| CN106372553A (en) * | 2016-08-30 | 2017-02-01 | 成都九洲电子信息系统股份有限公司 | Pipeline matrix algorithm based on GJB radio frequency identification technology |
| CN106372553B (en) * | 2016-08-30 | 2019-03-01 | 成都九洲电子信息系统股份有限公司 | Flowing water matrix matching technique based on GJB Radio Frequency Identification Technology |
| CN108809362A (en) * | 2018-07-17 | 2018-11-13 | 中国船舶重工集团公司第七〇九研究所 | A kind of wide bandwidth SAW reader emitter and its method |
| CN110414287A (en) * | 2019-07-26 | 2019-11-05 | 浙江大华技术股份有限公司 | A kind of modulation depth method of adjustment and device |
| CN112733979A (en) * | 2020-12-25 | 2021-04-30 | 重庆电子工程职业学院 | Safety protection device of RFID read-write equipment |
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| GR01 | Patent grant | ||
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130807 Termination date: 20140325 |