CN203117829U - Under-voltage locking circuit of BICMOS circuit structure - Google Patents

Abstract

The utility model discloses an under-voltage locking circuit of a BICMOS circuit structure. The under-voltage locking circuit comprises a voltage sampling circuit, a voltage comparing circuit, an output driving circuit and a delaying feedback circuit, wherein the voltage sampling circuit samples applied voltage; the voltage comparing circuit compares the sampled voltage and reference voltage produced by a reference circuit; the output driving circuit outputs and drives the voltage output by the voltage comparing circuit; and the delaying feedback circuit conducts delay feedback on voltage signals output by the output driving circuit to produce voltage delaying return difference characteristics. The under-voltage locking circuit can better improve reliability and stability of the system.

Description

A kind of undervoltage lockout circuit of BICMOS line construction

Technical field

The utility model relates to integrated circuit technique, refers more particularly to undervoltage lockout circuit.

Background technology

Traditional undervoltage lockout circuit turn threshold can change along with variation of temperature, thereby causes system's instability; Traditional undervoltage lockout circuit does not have the hysteresis function simultaneously, can cause the system repeatedly on-off phenomenon like this.

Summary of the invention

The utility model is intended to solve the deficiencies in the prior art, provides a kind of stability very high undervoltage lockout circuit.

Undervoltage lockout circuit comprises voltage sampling circuit, voltage comparator circuit, output driving circuit and sluggish feedback circuit:

Described voltage sampling circuit is that added voltage is sampled;

Described voltage comparator circuit is that the reference voltage that the voltage of described sampling and reference circuit produce is compared;

Described output driving circuit is that the voltage of described voltage comparator circuit output is exported and driven;

Described sluggish feedback circuit is that the voltage signal that described output driving circuit is exported is carried out the sluggishness feedback, produces the sluggish return difference characteristic of voltage.

Described voltage sampling circuit comprises first resistance, second resistance, the 3rd resistance and NMOS pipe:

One termination power of described first resistance, an end of described second resistance of another termination;

One end of described first resistance of one termination of described second resistance, an end of described the 3rd resistance of another termination;

One end of described second resistance of one termination of described the 3rd resistance, the drain electrode of the described NMOS pipe of another termination;

The grid of a described NMOS pipe connects the output terminal of described output driving circuit, and drain electrode connects an end of described the 3rd resistance, source ground.

Described voltage comparator circuit comprises the 4th resistance, the 5th resistance, the 6th resistance, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, PMOS pipe, NPN pipe and the 2nd NPN pipe:

One termination power of described the 4th resistance, the collector of the described NPN pipe of another termination;

One termination power of described the 5th resistance, the collector of described the 2nd NPN pipe of another termination and the grid of a described PMOS pipe;

The emitter of described the 2nd NPN pipe of one termination of described the 6th resistance, the drain electrode of described the 2nd NMOS pipe of another termination;

The grid of described the 2nd NMOS pipe connects the output terminal of described first phase inverter, and drain electrode connects an end of described the 6th resistance, source ground;

The grid of described the 3rd NMOS pipe connects power supply, and drain electrode connects the drain electrode of a described PMOS pipe, and source electrode connects the drain electrode of described the 4th NMOS pipe;

The grid of described the 4th NMOS pipe connects power supply, and drain electrode connects the source electrode of described the 3rd NMOS pipe, source ground;

The grid of a described PMOS pipe connects an end of described the 5th resistance, and drain electrode connects the drain electrode of described the 3rd NMOS pipe, and source electrode connects power supply;

The base stage of a described NPN pipe connects an end of described second resistance and an end of described the 3rd resistance, and collector connects an end of described the 4th resistance, and emitter connects the base stage of described the 2nd NPN pipe;

The base stage of described the 2nd NPN pipe connects the emitter of a described NPN pipe, and collector connects an end of described the 5th resistance and the grid of a described PMOS pipe.

Described output driving circuit comprises the 5th NMOS pipe, the 6th NMOS pipe and the 3rd NPN pipe:

The grid of described the 5th NMOS pipe connects an end of described first resistance and an end of described second resistance, and drain electrode connects power supply, and source electrode connects the collector of described the 3rd NPN pipe;

The grid of described the 6th NMOS pipe connects the drain electrode of source electrode and described the 4th NMOS pipe of described the 3rd NMOS pipe, and drain electrode connects the emitter of described the 3rd NPN pipe and the output terminal of described output driving circuit, source ground;

The base stage of described the 3rd NPN pipe connects the base stage of emitter and described the 2nd NPN pipe of a described NPN pipe, and collector connects the source electrode of described the 5th NMOS pipe, and emitter connects the drain electrode of described the 6th NMOS pipe.

Described sluggish feedback circuit comprises first phase inverter, NMOS pipe and the 2nd NMOS pipe:

The output terminal of the described output driving circuit of input termination of described first phase inverter, the grid of described the 2nd NMOS pipe of output termination;

The grid of a described NMOS pipe connects the output terminal of described output driving circuit, and drain electrode connects an end of described the 3rd resistance, source ground;

The grid of described the 2nd NMOS pipe connects the output terminal of described first phase inverter, and drain electrode connects an end of described the 6th resistance, source ground.

The undervoltage lockout circuit that utilizes the utility model to provide can improve the reliability and stability of system better.

Description of drawings

Fig. 1 is the circuit diagram of undervoltage lockout circuit of the present utility model.

Embodiment

Below in conjunction with accompanying drawing the utility model content is further specified.

Undervoltage lockout circuit as shown in Figure 1, comprises voltage sampling circuit, voltage comparator circuit, output driving circuit and sluggish feedback circuit:

Described voltage sampling circuit is that added voltage is sampled;

Described voltage comparator circuit is that the reference voltage that the voltage of described sampling and reference circuit produce is compared;

Described output driving circuit is that the voltage of described voltage comparator circuit output is exported and driven;

Described sluggish feedback circuit is that the voltage signal that described output driving circuit is exported is carried out the sluggishness feedback, produces the sluggish return difference characteristic of voltage.

Described voltage sampling circuit comprises first resistance 101, second resistance 102, the 3rd resistance 103 and NMOS pipe 104:

One termination power VCC of described first resistance 101, an end of described second resistance 102 of another termination;

One end of described first resistance 101 of one termination of described second resistance 102, an end of described the 3rd resistance 103 of another termination;

One end of described second resistance 102 of one termination of described the 3rd resistance 103, the drain electrode of the described NMOS pipe 104 of another termination;

The grid of described NMOS pipe 104 connects the output terminal of described output driving circuit, and drain electrode connects an end of described the 3rd resistance 103, source ground.

Described voltage comparator circuit comprises the 4th resistance 105, the 5th resistance 106, the 6th resistance 110, the 2nd NMOS pipe the 111, the 3rd NMOS pipe the 113, the 4th NMOS pipe the 114, the one PMOS pipe the 112, the one NPN pipe the 107 and the 2nd NPN pipe 108:

One termination power VCC of described the 4th resistance 105, the collector of the described NPN pipe 107 of another termination;

One termination power VCC of described the 5th resistance 106, the collector of described the 2nd NPN pipe 108 of another termination and the grid of described PMOS pipe 112;

The emitter of described the 2nd NPN pipe 108 of one termination of described the 6th resistance 110, the drain electrode of described the 2nd NMOS pipe 111 of another termination;

The grid of described the 2nd NMOS pipe 111 connects the output terminal of described first phase inverter 109, and drain electrode connects an end of described the 6th resistance 110, source ground;

The grid of described the 3rd NMOS pipe 113 meets power supply VCC, and drain electrode connects the drain electrode of described PMOS pipe 112, and source electrode connects the drain electrode of described the 4th NMOS pipe 114;

The grid of described the 4th NMOS pipe 114 meets power supply VCC, and drain electrode connects the source electrode of described the 3rd NMOS pipe 113, source ground;

The grid of described PMOS pipe 112 connects an end of described the 5th resistance 106, and drain electrode connects the drain electrode of described the 3rd NMOS pipe 113, and source electrode meets power supply VCC;

The base stage of described NPN pipe 107 connects an end of described second resistance 102 and an end of described the 3rd resistance 103, and collector connects an end of described the 4th resistance 105, and emitter connects the base stage of described the 2nd NPN pipe 108;

The base stage of described the 2nd NPN pipe 108 connects the emitter of described NPN pipe 107, and collector connects an end of described the 5th resistance 106 and the grid of described PMOS pipe 112.

Described output driving circuit comprises the 5th NMOS pipe the 115, the 6th NMOS pipe the 117 and the 3rd NPN pipe 116:

The grid of described the 5th NMOS pipe 115 connects an end of described first resistance 101 and an end of described second resistance 102, and drain electrode meets power supply VCC, and source electrode connects the collector of described the 3rd NPN pipe 116;

The grid of described the 6th NMOS pipe 117 connects the drain electrode of source electrode and described the 4th NMOS pipe 114 of described the 3rd NMOS pipe 113, and drain electrode connects the emitter of described the 3rd NPN pipe 116 and the output terminal of described output driving circuit, source ground;

The base stage of described the 3rd NPN pipe 116 connects the base stage of emitter and described the 2nd NPN pipe 108 of described NPN pipe 107, and collector connects the source electrode of described the 5th NMOS pipe 115, and emitter connects the drain electrode of described the 6th NMOS pipe 117.

Described sluggish feedback circuit comprises first phase inverter 109, NMOS pipe the 104 and the 2nd NMOS pipe 111:

The output terminal of the described output driving circuit of input termination of described first phase inverter 109, the grid of described the 2nd NMOS pipe 111 of output termination;

The grid of described NMOS pipe 104 connects the output terminal of described output driving circuit, and drain electrode connects an end of described the 3rd resistance 103, source ground;

The grid of described the 2nd NMOS pipe 111 connects the output terminal of described first phase inverter 109, and drain electrode connects an end of described the 6th resistance 110, source ground.

The utility model discloses a kind of undervoltage lockout circuit of BICMOS line construction, and describe embodiment of the present utility model and effect with reference to the accompanying drawings.What should be understood that is: above-described embodiment is just to explanation of the present utility model, rather than to restriction of the present utility model, any utility model that does not exceed in the utility model connotation scope is created, and all falls within the utility model protection domain.

Claims (5)

1. undervoltage lockout circuit is characterized in that comprising voltage sampling circuit, voltage comparator circuit, output driving circuit and sluggish feedback circuit:

Described voltage sampling circuit is that added voltage is sampled;

Described voltage comparator circuit is that the reference voltage that the voltage of described sampling and reference circuit produce is compared;

Described output driving circuit is that the voltage of described voltage comparator circuit output is exported and driven;

Described sluggish feedback circuit is that the voltage signal that described output driving circuit is exported is carried out the sluggishness feedback, produces the sluggish return difference characteristic of voltage.

2. undervoltage lockout circuit as claimed in claim 1 is characterized in that described voltage sampling circuit comprises first resistance, second resistance, the 3rd resistance and NMOS pipe:

One termination power of described first resistance, an end of described second resistance of another termination;

One end of described first resistance of one termination of described second resistance, an end of described the 3rd resistance of another termination;

One end of described second resistance of one termination of described the 3rd resistance, the drain electrode of the described NMOS pipe of another termination;

The grid of a described NMOS pipe connects the output terminal of described output driving circuit, and drain electrode connects an end of described the 3rd resistance, source ground.

3. undervoltage lockout circuit as claimed in claim 1 is characterized in that described voltage comparator circuit comprises the 4th resistance, the 5th resistance, the 6th resistance, the 2nd NMOS pipe, the 3rd NMOS pipe, the 4th NMOS pipe, PMOS pipe, NPN pipe and the 2nd NPN pipe:

One termination power of described the 4th resistance, the collector of the described NPN pipe of another termination;

One termination power of described the 5th resistance, the collector of described the 2nd NPN pipe of another termination and the grid of a described PMOS pipe;

The emitter of described the 2nd NPN pipe of one termination of described the 6th resistance, the drain electrode of described the 2nd NMOS pipe of another termination;

The grid of described the 2nd NMOS pipe connects the output terminal of described first phase inverter, and drain electrode connects an end of described the 6th resistance, source ground;

The grid of described the 3rd NMOS pipe connects power supply, and drain electrode connects the drain electrode of a described PMOS pipe, and source electrode connects the drain electrode of described the 4th NMOS pipe;

The grid of described the 4th NMOS pipe connects power supply, and drain electrode connects the source electrode of described the 3rd NMOS pipe, source ground;

The grid of a described PMOS pipe connects an end of described the 5th resistance, and drain electrode connects the drain electrode of described the 3rd NMOS pipe, and source electrode connects power supply;

The base stage of a described NPN pipe connects an end of described second resistance and an end of described the 3rd resistance, and collector connects an end of described the 4th resistance, and emitter connects the base stage of described the 2nd NPN pipe;

The base stage of described the 2nd NPN pipe connects the emitter of a described NPN pipe, and collector connects an end of described the 5th resistance and the grid of a described PMOS pipe.

4. undervoltage lockout circuit as claimed in claim 1 is characterized in that described output driving circuit comprises the 5th NMOS pipe, the 6th NMOS pipe and the 3rd NPN pipe:

The grid of described the 5th NMOS pipe connects an end of described first resistance and an end of described second resistance, and drain electrode connects power supply, and source electrode connects the collector of described the 3rd NPN pipe;

The grid of described the 6th NMOS pipe connects the drain electrode of source electrode and described the 4th NMOS pipe of described the 3rd NMOS pipe, and drain electrode connects the emitter of described the 3rd NPN pipe and the output terminal of described output driving circuit, source ground;

The base stage of described the 3rd NPN pipe connects the base stage of emitter and described the 2nd NPN pipe of a described NPN pipe, and collector connects the source electrode of described the 5th NMOS pipe, and emitter connects the drain electrode of described the 6th NMOS pipe.

5. undervoltage lockout circuit as claimed in claim 1 is characterized in that described sluggish feedback circuit comprises first phase inverter, NMOS pipe and the 2nd NMOS pipe:

The output terminal of the described output driving circuit of input termination of described first phase inverter, the grid of described the 2nd NMOS pipe of output termination;

The grid of a described NMOS pipe connects the output terminal of described output driving circuit, and drain electrode connects an end of described the 3rd resistance, source ground;

The grid of described the 2nd NMOS pipe connects the output terminal of described first phase inverter, and drain electrode connects an end of described the 6th resistance, source ground.

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