CN203102069U - Double-circuit main board supporting AMD bridge chips SR5650 and SP5100 - Google Patents
Double-circuit main board supporting AMD bridge chips SR5650 and SP5100 Download PDFInfo
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- CN203102069U CN203102069U CN 201220248535 CN201220248535U CN203102069U CN 203102069 U CN203102069 U CN 203102069U CN 201220248535 CN201220248535 CN 201220248535 CN 201220248535 U CN201220248535 U CN 201220248535U CN 203102069 U CN203102069 U CN 203102069U
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Abstract
The utility model relates to a double-circuit main board supporting AMD bridge chips SR5650 and SP5100. The double-circuit main board comprises a north bridge chip, a south bridge chip, a variable gain amplifier (VGA) interface, a peripheral component interface express (PCIE) interface, a first Loongson central processing unit (CPU), a second Loongson CPU, and memory slots. The north bridge chip is respectively connected with the south bridge chip and the first Loongson CPU. The south bridge chip is connected with a VGA device through the VGA interface. The first Loongson CPU is connected with the second Loongson CPU. The first Loongson CPU comprises a DDR2 memory controller or a DDR3 memory controller, and the second Loongson CPU comprises a DDR2 memory controller or a DDR3 memory controller. The memory controllers are connected with the memory slots. Both the first Loongson CPU and the second Loongson CPU are equipped with CPU radiators. According to the double-circuit main board, the Loongson CPUs can be well applied to practical situations, and the north bridge chip and the south bridge chip are used for being well matched with the Loongson CPUs. The double-circuit main board is simple in structure and high in stability and reliability.
Description
Technical field
The utility model relates to a kind of mainboard, is specifically related to the two-way mainboard of a kind of AMD of support bridge sheet SR5650 and SP5100.
Background technology
The seen in the market mainboard that all is based on the X86 framework, what that is to say that CPU selects for use is to follow the INTEL of X86 framework or AMD, and the bridge sheet also all is the chip with the CPU of X86 collocation, CPU for Godson, he is based on the MIPS framework, does not have a ingenious and its collocation in the market and forms a mainboard.
The difficult situation of Chinese high-performance server field centreless has been broken in the appearance of No. 3 serial CPU of Godson, China IT industry band on a new height.But the problem that next faces a sternness is exactly the industrialization problem of CPU, if solve the problem of bad industrialization, it can not practicality be the CPU of conceptual that Godson CPU is still one, can only stop under lab.Because the time that No. 3 serial CPU of Godson emerge is short, various supporting application schemes have to be designed and create.
The utility model content
At the deficiencies in the prior art, the utility model proposes the two-way mainboard of a kind of AMD of support bridge sheet SR5650 and SP5100, can well apply to Godson CPU in the reality, with AMD chipsets SR5650 north bridge chips and AMD chipsets SP5100 South Bridge chip well and the supporting use of Godson CPU, simple in structure, stability and reliability are all higher.
A kind of AMD of support bridge sheet SR5650 that the utility model provides and the two-way mainboard of SP5100, its improvements are that described two-way mainboard comprises AMD chipsets SR5650 north bridge chips, AMD chipsets SP5100 South Bridge chip, VGA interface, PCIE interface, the first Godson CPU, second Godson CPU and the memory bank;
Described AMD chipsets SR5650 north bridge chips is connected with the described first Godson CPU with described AMD chipsets SP5100 South Bridge chip respectively; Described AMD chipsets SP5100 South Bridge chip is connected with VGA equipment by described VGA interface; The described first Godson CPU is connected with the second Godson CPU; The described first Godson CPU comprises DDR2 Memory Controller Hub or DDR3 Memory Controller Hub; The described Godson second Godson CPU comprises DDR2 Memory Controller Hub or DDR3 Memory Controller Hub; Described Memory Controller Hub is connected with described memory bank; The described first Godson CPU and the second Godson CPU all are furnished with cpu heat.Each CPU can maximum continuous 4 memory slots.
Wherein, described Godson CPU0 uses the DDR2/DDR3 Memory Controller Hub directly to be connected with described memory bank.
Wherein, described Godson CPU1 uses the DDR2/DDR3 Memory Controller Hub directly to be connected with described memory bank.
Wherein, described AMD chipsets SR5650 north bridge chips has the passage of 26 PCIE, 4 are used as the A_Link bus and are connected with described AMD chipsets SP5100 South Bridge chip in the described PCIE passage, and all the other 22 PCIE passages are connected with PCIE peripherals by described PCIE interface.
Wherein, described AMD chipsets SP5100 South Bridge chip has 6 SATA interfaces, 14 USB interface and 1 PCIbus interface.
Wherein, described AMD chipsets SP5100 South Bridge chip is connected with described VGA equipment by described PCI bus interface.
Wherein, described AMD chipsets SR5650 north bridge chips is connected with the HT bus controller by the HT bus.
Wherein, be to adopt HT bus to carry out interconnected between the described first Godson CPU and the second Godson CPU.
Wherein, the described first Godson CPU or the second Godson CPU are the CPU of 4 core 3A, 8 core 3B or 8 cores/16 core 3C.
Wherein, described peripheral hardware comprises sound card, video card and external memory storage.
Compared with the prior art, the beneficial effects of the utility model are:
The utility model can well apply to Godson CPU in the reality, and is with AMD chipsets SR5650 north bridge chips and AMD chipsets SP5100 South Bridge chip well and the supporting use of Godson CPU simple in structure, stable and reliability is all higher.
The utility model is a dual-cpu structure, and it can scalability, and good stability.
Description of drawings
The two-way mainboard structure figure that Fig. 1 provides for the utility model based on SR5650 and SP5100.
Embodiment
Below in conjunction with accompanying drawing embodiment of the present utility model is described in further detail.
The support AMD bridge sheet SR5650 of present embodiment and the two-way mainboard structure figure of SP5100 as shown in Figure 1, the two-way mainboard comprises that AMD chipsets SR5650 north bridge chips, AMD chipsets SP5100 South Bridge chip, VGA interface, PCIE interface, the first Godson CPU(are Godson CPU0), the second Godson CPU(is Godson CPU1) and memory bank; Described AMD chipsets SR5650 north bridge chips is connected with described Godson CPU0 with described AMD chipsets SP5100 South Bridge chip respectively; Described AMD chipsets SP5100 South Bridge chip is connected with VGA equipment by described VGA interface; Described Godson CPU0 is connected with Godson CPU1; Described Godson CPU0 comprises DDR2 Memory Controller Hub or DDR3 Memory Controller Hub; Described Godson CPU1 comprises DDR2 Memory Controller Hub or DDR3 Memory Controller Hub; Described Godson CPU0 and Godson CPU1 all are furnished with cpu heat.Each CPU 4 memory slots that can maximum link to each other, a CPU has 2 Memory Controller Hub, and each controller connects 2 memory slots, so amount to 4, configurable 8 memory slots of two Godson CPU of present embodiment.
Described Godson CPU0 uses DDR2 or DDR3 Memory Controller Hub directly to be connected with described memory bank 0; Described Godson CPU1 uses DDR2 or DDR3 Memory Controller Hub directly to be connected with described memory bank 1.
Described AMD chipsets SR5650 north bridge chips has the passage of 26 PCIE, 4 are used as the A_Link bus and are connected with described AMD chipsets SP5100 South Bridge chip in the described PCIE passage, and all the other 22 PCIE passages are connected with PCIE peripherals by described PCIE interface.Described AMD chipsets SR5650 north bridge chips is connected with described HT bus controller by described HT bus.
Described AMD chipsets SP5100 South Bridge chip has 6 SATA interfaces, 14 USB interface and 1 PCI bus interface.Described AMD chipsets SP5100 South Bridge chip is connected with described VGA equipment by described PCI bus interface.
Be to adopt HT bus to carry out interconnected between described Godson CPU0 and the Godson CPU1.Wherein Godson CPU0 or Godson CPU1 are the CPU of 4 core 3A, 8 core 3B or 8 nuclears/16 core 3C.
Should be noted that at last: above embodiment only is not intended to limit in order to the explanation the technical solution of the utility model, although the utility model is had been described in detail with reference to the foregoing description, those of ordinary skill in the field are to be understood that: still can make amendment or be equal to replacement embodiment of the present utility model, and do not break away from any modification of the utility model spirit and scope or be equal to replacement, it all should be encompassed in the middle of the claim scope of the present utility model.
Claims (9)
1. two-way mainboard of supporting AMD bridge sheet SR5650 and SP5100, it is characterized in that described two-way mainboard comprises AMD chipsets SR5650 north bridge chips, AMD chipsets SP5100 South Bridge chip, VGA interface, PCIE interface, the first Godson CPU, second Godson CPU and the memory bank;
Described AMD chipsets SR5650 north bridge chips is connected with the described first Godson CPU with described AMD chipsets SP5100 South Bridge chip respectively; Described AMD chipsets SP5100 South Bridge chip is connected with VGA equipment by described VGA interface; The described first Godson CPU is connected with the second Godson CPU; The described first Godson CPU and the second Godson CPU include Memory Controller Hub; Described Memory Controller Hub is connected with described memory bank; The described first Godson CPU and the second Godson CPU all are furnished with cpu heat.
2. two-way mainboard as claimed in claim 1 is characterized in that, the described first Godson CPU uses the DDR2/DDR3 Memory Controller Hub directly to be connected with described memory bank.
3. two-way mainboard as claimed in claim 1 is characterized in that, the described second Godson CPU uses the DDR2/DDR3 Memory Controller Hub directly to be connected with described memory bank.
4. two-way mainboard as claimed in claim 1, it is characterized in that, described AMD chipsets SR5650 north bridge chips has the passage of 26 PCIE, 4 are used as the A_Link bus and are connected with described AMD chipsets SP5100 South Bridge chip in the described PCIE passage, and all the other 22 PCIE passages are connected with PCIE peripherals by described PCIE interface.
5. two-way mainboard as claimed in claim 1 is characterized in that, described AMD chipsets SP5100 South Bridge chip has 6 SATA interfaces, 14 USB interface and 1 PCI bus interface.
6. two-way mainboard as claimed in claim 1 is characterized in that, described AMD chipsets SP5100 South Bridge chip is connected with described VGA equipment by described PCI bus interface.
7. two-way mainboard as claimed in claim 1 is characterized in that, described AMD chipsets SR5650 north bridge chips is connected with the HT bus controller by the HT bus.
8. two-way mainboard as claimed in claim 1 is characterized in that, between the described first Godson CPU and the second Godson CPU is to adopt HT bus to carry out interconnected.
9. two-way mainboard as claimed in claim 1 is characterized in that, the described first Godson CPU or the second Godson CPU are the CPU of 4 core 3A, 8 core 3B or 8 cores/16 core 3C.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220248535 CN203102069U (en) | 2012-05-30 | 2012-05-30 | Double-circuit main board supporting AMD bridge chips SR5650 and SP5100 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220248535 CN203102069U (en) | 2012-05-30 | 2012-05-30 | Double-circuit main board supporting AMD bridge chips SR5650 and SP5100 |
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| Publication Number | Publication Date |
|---|---|
| CN203102069U true CN203102069U (en) | 2013-07-31 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220248535 Expired - Lifetime CN203102069U (en) | 2012-05-30 | 2012-05-30 | Double-circuit main board supporting AMD bridge chips SR5650 and SP5100 |
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| CN (1) | CN203102069U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103823521A (en) * | 2014-03-18 | 2014-05-28 | 曙光信息产业股份有限公司 | Fake Twins Loongson mainboard |
-
2012
- 2012-05-30 CN CN 201220248535 patent/CN203102069U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103823521A (en) * | 2014-03-18 | 2014-05-28 | 曙光信息产业股份有限公司 | Fake Twins Loongson mainboard |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130731 |