CN203085131U - Shifting register, grid electrode drive circuit and display device - Google Patents
Shifting register, grid electrode drive circuit and display device Download PDFInfo
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- CN203085131U CN203085131U CN 201320103369 CN201320103369U CN203085131U CN 203085131 U CN203085131 U CN 203085131U CN 201320103369 CN201320103369 CN 201320103369 CN 201320103369 U CN201320103369 U CN 201320103369U CN 203085131 U CN203085131 U CN 203085131U
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Abstract
The utility model discloses a shifting register, a grid electrode drive circuit and a display device. The shifting register comprises a shifting register module, a repairing module, and a first attachable link and a second attachable link, which are arranged between the two modules and used for conducting or disconnecting the output ends and the input ends of the two modules; the shifting register module is used for outputting a clock signal inputted through a first clock signal input end from the respective output end according to an excitation signal received by a respective excitation signal input end; and the repairing module is used for delaying the excitation signal received by the excitation signal input end for half circle and outputting the delayed excitation signal from the output end when the shifting register module has a malfunction. The shifting register comprises the repairing module which can substitute the shifting register module, so that when the shifting register module has the malfunction, the work of the subsequent shifting register is not influenced.
Description
Technical field
The utility model relates to technical field of flat panel display, relates in particular to a kind of shift register, gate driver circuit and display device.
Background technology
Flat-panel monitor is because of its ultra-thin energy-conservation development rapidly.To use shift register in most flat-panel monitors, at present, by the capable driving of array base palte (Gate on Array, GOA) shift register of technology realization not only can be integrated on the grid-driving integrated circuit, can also reduce the production process of one display panel, therefore, save cost, so in recent years, the GOA technology was widely used in the flat-panel monitor manufacturing process.
The problem of utilizing the GOA technology to exist at present is, the formation shift register of GOA depends on the output signal of upper level shift register, with the output signal of upper level shift register input signal as shift register at the corresponding levels, if the upper level shift register is because of breaking down or invalid its output signal of making occurs unusually, to cause the follow-up shift register can not normal output signal, also be about to cause whole GOA circuit misoperation to occur, even can't work.
And in the actual production processing procedure, because whole thin film transistor (TFT) (Thin Film Transistor, TFT) yield of backboard is difficult to reach 100%, therefore among the GOA TFT of shift register defective to occur be possible fully, this will cause shift register to break down, and then just might cause the paralysis of whole GOA circuit.
The utility model content
The utility model embodiment provides a kind of shift register, gate driver circuit and display device, causes the problem that can't work owing to a shift register breaks down in order to solve existing GOA circuit.
The concrete technical scheme that the utility model embodiment provides is as follows:
A kind of shift register, described shift register comprises: output terminal, pumping signal input end and first clock signal input terminal, first can connect link, second can connect link and shift register module and reparation module; Described shift register module comprises output terminal, pumping signal input end and is used to receive first clock signal input terminal of clock signal of first clock signal input terminal input of shift register; Described reparation module comprises output terminal and pumping signal input end; Wherein:
Described first can connect link be arranged at shift register pumping signal input end, shift register module the pumping signal input end and repair between the pumping signal input end of module, be used for when shift register module breaks down, disconnect being connected of pumping signal input end of the pumping signal input end of shift register module and shift register, and being connected of pumping signal input end of the pumping signal input end of module and shift register repaired in conducting;
Described second can connect link be arranged at shift register output terminal, shift register module output terminal and repair between the output terminal of module, be used for when shift register module breaks down, being connected of output terminal of the output terminal of module and shift register repaired in conducting;
Described shift register module is used for the pumping signal of basis from the pumping signal input end reception of self, and the clock signal that will receive from first clock signal input terminal of self is from the output terminal output of self;
Described reparation module is used for when shift register module breaks down, after the pumping signal that will receive from the pumping signal input end of self is carried out the delay of half clock period, from the output terminal output of self.
A kind of gate driver circuit comprises a plurality of above-mentioned shift registers of stating;
Except that first shift register and last shift register, the output terminal of all the other each shift registers is connected with the reset signal input end of the upper level shift register that is adjacent and the pumping signal input end of the next stage shift register that is adjacent respectively, and gate driver circuit is sequentially exported the signal of the output terminal output of shift registers at different levels;
The output terminal of first shift register is connected with the pumping signal input end of second shift register, and the output terminal of last shift register is connected with the reset signal input end of a last shift register that is adjacent;
The pumping signal input end incoming frame start signal of first shift register.
A kind of display device, described display device comprises above-mentioned gate driver circuit.
In embodiment of the present utility model, since shift register comprise have the pumping signal that the pumping signal input end from self is received and carry out the delay of half clock period after, from the reparation module of output terminal output function of self, and at shift register module that shift register and its comprise with repair and be provided with first between the module and can be connected to link and be connected and link with second, make that the shift register module of the realization shift function in shift register is invalid or when breaking down, can utilize first and second conducting and the break functions that can connect link to realize utilizing the reparation module to replace shift register module, make in the GOA circuit shift register break down or when invalid, utilize the reparation module in this shift register still can normally carry out work, do not influence the work of follow-up shift register.
Description of drawings
Fig. 1 is the structural representation of the shift register among the utility model embodiment one;
Fig. 2 is the circuit diagram of the reparation module among the utility model embodiment two;
Fig. 3 is the structural representation of the shift register module among the utility model embodiment two;
Fig. 4 is the electrical block diagram of the shift register module among the utility model embodiment two;
Fig. 5 is the circuit diagram of the shift register among the utility model embodiment two;
Fig. 6 is the scanning sequence figure of the shift register among the utility model embodiment two;
Fig. 7 is the structural representation of the gate driver circuit among the utility model embodiment three;
Fig. 8 is the synoptic diagram that the shift register module in the shift register among the utility model embodiment four is substituted by the reparation module in this shift register.
Embodiment
Below in conjunction with Figure of description, the embodiment of a kind of shift register, gate driver circuit and the display device that the utility model embodiment is provided describes.
Embodiment one
As shown in Figure 1, be a kind of shift register 10 among the utility model embodiment one, described shift register 10 comprises: first can connect link L1, second can connect link L2, pumping signal input end P
100, output terminal P
101With the first clock signal input terminal (not shown in figure 1), and shift register module 21 and reparation module 22; Described shift register module 21 comprises pumping signal input end P
210, output terminal P
211The first clock signal input terminal (not shown in figure 1) with the clock signal of first clock signal input terminal input that is used to receive shift register 10; Described reparation module 22 comprises pumping signal input end P
220With output terminal P
221Wherein:
Described first can connect the pumping signal input end P that link L1 is arranged at shift register 10
100, shift register module 21 pumping signal input end P
210With the pumping signal input end P that repairs module 22
220Between, be used for when shift register module 21 breaks down, disconnect the pumping signal input end P of shift register module 21
220Pumping signal input end P with shift register 10
100Connection, and the pumping signal input end P of module 22 is repaired in conducting
220Pumping signal input end P with shift register 10
100Connection;
Described second can connect the output terminal P that link L2 is arranged at shift register 10
101, shift register module output terminal P
211With the output terminal P that repairs module
221Between, being used for when shift register module 21 breaks down, the output terminal of module 22 and the output terminal P of shift register 10 are repaired in conducting
101Connection;
Described shift register module 21 is used for according to the pumping signal input end P from self
210The pumping signal that receives will be from self the clock signal of first clock signal input terminal input from self output terminal P
211Output;
Described reparation module 22 is used for when shift register module 21 breaks down, will be from the pumping signal input end P of self
220After the pumping signal that receives is carried out the delay of half clock period, from the output terminal P of self
221Output.
Because pumping signal and clock signal are the pulse signal of half clock period, so the pumping signal of half clock period of time-delay of reparation module output is identical to the driving action that grid line plays with clock signal to the driving action that grid line plays, therefore, when above-mentioned shift register module 21 breaks down, can substitute with above-mentioned reparation module 22.
Need to prove that above-mentioned shift register module 21 can be arbitrary existing shift register, and when shift register module does not break down, common, P
100And P
210Be conducting, P
101And P
211Be conducting, and P
100And P
220Disconnect P
101And P
221Disconnect, so in Fig. 1, when expression first can connect link L1, connected P with solid line
100And P
210, connected P with the solid line of the circle that has opening
100And P
220Same, when expression first can connect link L2, connected P with solid line
101And P
211, connected P with the solid line of the circle that has opening
101And P
221
In the scheme of the utility model embodiment one, since shift register comprised reparation module and first can connect the link can be connected link with second, this reparation module has the function of exporting after will self pumping signal of input postponing half clock period, therefore, can substitute the shift register module that breaks down and finish shift function, so just make when shift register module breaks down, utilize described first can connect link and externally realize the function that is shifted with second function that can be connected link.
The physical circuit of realizing reparation module 22 functions is not limited among the utility model embodiment one, arbitrary have the circuit that the pumping signal that receives is carried out exporting after the delay of half clock period and all can, can also be the clock signal that has according to first clock signal input terminal input of self, the pumping signal that receives be carried out the circuit of the function exported after the delay of half clock period.
Scheme below by two couples of the utility model embodiment one of embodiment is further detailed.
Embodiment two
On the basis of the utility model embodiment one, a kind of shift register is provided among the utility model embodiment two, to realizing in this shift register that the circuit of repairing functions of modules carries out concrete qualification, the circuit diagram of the reparation module 22 of this shift register comprises as shown in Figure 2: first capacitor C 1 and the 5th transistor M5;
Described first capacitor C 1, the one end links to each other other end ground connection with the pumping signal input end of repairing module;
Described the 5th transistor M5, its grid links to each other with first clock signal input terminal, and first limit links to each other with the pumping signal input end of repairing module, and second limit links to each other with the output terminal of repairing module.Understandable, for example, first clock signal input terminal that is connected with the grid of described the 5th transistor M5 can be first clock signal input terminal of shift register 10 or first clock signal input terminal of shift register module 21, it can also be first clock signal input terminal of self, only need the grid control control signal that the pumping signal that the 5th transistor M5 receives carries out exporting after the delay of half clock period is got final product, do not do qualification at this.
The principle of work of the reparation module that is made of above-mentioned first capacitor C 1 and the 5th transistor M5 is as follows:
Receive pumping signal when (half clock period) at this pumping signal input end of repairing module, first clock signal input terminal is imported the signal of first level, the signal of this first level makes transistor M5 close, and then pumping signal is charged to capacitor C 1, in half clock period after pumping signal receives, first clock signal input terminal is imported the signal of second level, the signal of this second level makes transistor M5 open, and then capacitor C 1 discharge exports the pumping signal of storage to the output terminal of reparation module.
Further, described shift register 10 also comprises the reset signal input end, described shift register module 21 also comprises the reset signal input end that is used to receive reset signal, the reset signal input end of described shift register 10 links to each other with the reset signal input end of described shift register module 21, the structural representation of described shift register module 21 as shown in Figure 3, comprise: load module 31, last drawing-die piece 32 and reseting module 33, wherein:
Load module 31 is used for receiving pumping signal from the pumping signal input end of shift register module 21, and draws control signal to drawing in the node PU output between load module and the last drawing-die piece;
Last drawing-die piece 32, be used for according on draw node PU on draw control signal, the signal of first clock signal input terminal input is offered the output terminal of shift register module 21;
Reseting module 33 is used for the reset signal of basis from the reset signal input end reception of shift register module 21, upwards draws the output terminal of node and shift register module that supply voltage is provided.
Below to a kind of exemplary illustration that carries out in the physical circuit with above-mentioned load module 31, last drawing-die piece 32 and reseting module 33.
As shown in Figure 4, for having above-mentioned load module 31, going up the circuit diagram of the shift register module of drawing-die piece 32 and reseting module 33, wherein:
Described load module 31 comprises: the first transistor M1;
Described the first transistor M1, its first limit jointly links to each other with the pumping signal input end of shift register module with grid, its second limit with on draw node to link to each other.
The described drawing-die piece 32 of going up comprises: the transistor seconds M2 and second capacitor C 2;
Described transistor seconds M2, its grid with on draw node to link to each other, first limit links to each other with first clock signal output terminal, the output terminal of second limit and shift register module links to each other;
Described second capacitor C 2, the one end with on draw node to link to each other, the output terminal of the other end and shift register module links to each other.
More excellent, the ratio of the electric capacity of described first capacitor C 1 and second capacitor C 2 is more than or equal to 5:1, when a plurality of shift register concatenation are used, this ratio can make C1 in the shift register at the corresponding levels to the charging of second capacitor C 2 in the shift register module in its next stage shift register (being similar to electric charge reallocation between electric capacity), make the current potential on second capacitor C 2 of next stage shift register still keep the higher voltage value, thereby, realize the operate as normal of described next stage shift register by the bootstrap effect of the C2 in the described next stage shift register.
More excellent, described shift register also comprises the second clock signal input part, described shift register module also comprises the second clock signal input part of the clock signal of the second clock signal input part input that is used to receive shift register, and described reseting module 33 comprises: the 3rd transistor M3 and the 4th transistor M4;
Described the 3rd transistor M3, the reset signal input end of its grid and shift register module links to each other, first limit with on draw node to link to each other, second limit links to each other with supply voltage;
Described the 4th transistor M4, its grid links to each other with the second clock signal input part, and the output terminal of first limit and shift register module links to each other, and second limit links to each other with supply voltage.
The circuit diagram of the shift register of the utility model embodiment two that is made of above-mentioned Fig. 3 and Fig. 4 as shown in Figure 5.
In shift register shown in Figure 5, first can connect link is used for when shift register module does not break down, being connected of the pumping signal input end of conducting shift register module and the pumping signal input end of shift register, and being connected of pumping signal input end of the pumping signal input end of module and shift register repaired in conducting; Second can connect link is used for when shift register module does not break down, and the output terminal of conducting shift register module is connected with the output terminal of shift register, and being connected of output terminal of the output terminal of module and shift register repaired in conducting.
Among the utility model embodiment, first limit in each transistor and the connected mode of second limit can be exchanged, therefore, transistorized first limit of being mentioned among the utility model embodiment can also can be transistorized source electrode for transistor drain, second limit can also can be transistorized source electrode for transistor drain, and, first limit in above-mentioned five transistors does not need to be simultaneously source electrode or drain electrode, second limit does not need to be simultaneously drain electrode or source electrode, promptly any t in first to the 5th transistor transistorized first limit is drain electrode, second limit is a source electrode, any 5-t in above-mentioned five transistors transistorized first limit is source electrode, second limit is drain electrode, wherein, and 0≤t≤5.
In order to further specify the principle of work of the utility model embodiment two, be example with shift register shown in Figure 5 below, and in conjunction with scanning sequence shown in Figure 6 respectively when not breaking down and when breaking down the principle of work of shift register shown in Figure 5 describe.
As shown in Figure 6, the scanning sequence synoptic diagram of the shift register that provides for the utility model embodiment two, wherein:
CLK is first clock signal of input shift register S/R (n);
CLKB is the second clock signal of input shift register S/R (n);
G(n-1) being the signal of the output terminal output of shift register S/R (n) upper level shift register S/R (n-1), as the input signal of shift register S/R at the corresponding levels (n), also is pumping signal;
G(n+1) be the signal of the output terminal output of shift register S/R (n) next stage shift register S/R (n+1), as the reset signal of shift register S/R at the corresponding levels (n);
VSS is the supply voltage of input shift register S/R (n), and it is a low level signal;
G(n) be the signal of the output terminal output of shift register S/R (n);
1, when shift register module does not break down, the scanning sequence process of this shift register S/R (n) can be divided into following five stages (one among Fig. 6, two, three, four, the 5th represents time period in described five stages):
Phase one: the preceding semiperiod of first clock period, the output terminal G(n-1 of shift register S/R (n) reception S/R (n-1)) high level signal, so transistor M1 opens, first capacitor C 1 and 2 chargings of second capacitor C, on draw node PU electromotive force to uprise, M2 opens, G(n) low level signal of output CLK; CLK is a low level signal, so M5 closes; G(n+1) be low level signal, so M3 closes; CLKB is a high level signal, so M4 opens, G(n) output supply voltage VSS is therefore, at this stage G(n) be low level signal.
Subordinate phase: in the later half cycle of first clock period, the pumping signal of input shift register S/R (n) is the low level signal of low level signal (also being G(n-1) in this stage), so M1 closes; The reset signal of input shift register S/R (n) is the low level signal of low level signal (also being G(n+1) in this stage), so transistor M3 closes; On draw node PU still to keep high potential, so transistor seconds M2 stays open, the high level signal of first clock signal clk is exported from M2, also be G(n) be high level signal, because at this stage first clock signal clk is high level signal, so M5 opens 1 discharge of first capacitor C, at this moment, the discharge of first capacitor C 1 is to G(n) output high level signal play humidification.
Phase III: the preceding semiperiod of second clock period, the pumping signal of input shift register S/R (n) is the low level signal of low level signal (also being G(n-1) in this stage), so M1 closes; The reset signal of input S/R (n) is that high level signal (also being the signal G(n+1 of the output terminal output of S/R (n+1)) is a high level signal in this stage), so transistor M3 opens; Second clock signal CLKB is a high level signal, so transistor M4 opens, supply voltage VSS exports to by M3 and draws node PU, and supply voltage VSS exports output terminal to by M4, so the signal G(n of S/R (n) output) be low level signal, 2 discharges of second capacitor C, on draw node PU point electromotive force to reduce, and then M2 closes, at this moment, the first clock signal clk output low level signal is so M5 closes.
The quadravalence section: in the later half cycle of second clock period, only first clock signal is a high level signal, and the signal of all the other input S/R (n) is low level signal, and this moment, M5 opened, the signal G(n of S/R (n) output) be low level signal.
Five-stage: the preceding semiperiod of the 3rd clock period, only the second clock signal is a high level signal, and the signal of all the other input S/R (n) is low level signal, and this moment, M4 opened, the signal G(n of S/R (n) output) be low level signal.
Afterwards, repeat quadravalence section and five-stage successively, receive the signal G(n-1 of the output terminal output of S/R (n-1) until shift register S/R (n)) begin to re-execute the phase one again for behind the high level signal.
By above-mentioned analysis as can be known, when the shift register shown in Fig. 5 does not break down at its shift register module that comprises, can not need to disconnect being connected of pumping signal input end of the pumping signal input end of repairing module and shift register, and being connected of output terminal that does not need to disconnect the output terminal of repairing module and shift register, and the reparation module of this moment plays synergism to shift register module in the output of subordinate phase.Certainly, also can disconnect being connected of pumping signal input end of the pumping signal input end of repairing module and shift register, and being connected of output terminal that disconnects the output terminal of repairing module and shift register, repair module and do not work this moment.
2, when shift register module breaks down, disconnect the pumping signal input end of shift register module and being connected of the pumping signal input end of repairing module, in practical operation, when shift register module breaks down, can utilize the laser preparing technology to cut off being connected of input end of the input end of shift register module and shift register, also promptly disconnect the input end of shift register and being connected of M1, but at shift register shown in Figure 5, for the output terminal of shift register module and can disconnecting being connected of output terminal of reparation module, can not disconnect yet, below in conjunction with Fig. 5 and Fig. 6 respectively to the output terminal that do not disconnect shift register module and describe being connected of output terminal of repairing module with the principle of work that is connected shift register at this moment of the output terminal of repairing module with the output terminal that disconnects shift register module.
When (1) shift register module in shift register breaks down, disconnect the pumping signal input end of shift register module and being connected of the pumping signal input end of repairing module, under the output terminal that disconnects shift register module and the situation about being connected of the output terminal of reparation module, the course of work of shift register is divided two stages, phase one is the electric capacity charging stage, and subordinate phase is the signal output stage.
Phase one: the preceding semiperiod of first clock period, S/R (n-1) exports high level signal, and first clock signal clk is a low level signal, 1 charging of first capacitor C, the 5th transistor M5 closes, the signal G(n of the output terminal output of shift register) be low level signal.
Subordinate phase: the later half cycle of first clock period, S/R (n-1) output low level signal, first clock signal clk is a high level signal, transistor M5 opens, first capacitor C 1 exports the electric signal of storage the output terminal of shift register to by M5, so the signal G(n that the output terminal of shift register is exported) be high level signal.
When (2) shift register module in shift register breaks down, disconnect the pumping signal input end of shift register module and being connected of the pumping signal input end of repairing module, under the situation about being connected of the output terminal that does not disconnect shift register module and the output terminal of repairing module, the course of work of shift register is divided following four-stage.
Phase one: the preceding semiperiod of first clock period, the G(n-1 of S/R (n-1) output) be high level signal, first clock signal clk is a low level signal, 1 charging of first capacitor C, the 5th transistor M5 closes, the signal G(n of shift register output terminal output) be low level signal, and be low level signal the reset signal G(n+1 of S/R this moment (n+1) output), so M3 closes, second clock signal CLKB is a high level signal, so M4 opens, this moment, supply voltage VSS made the signal G(n of shift register output terminal output simultaneously by M4) be low level signal.
Subordinate phase: the later half cycle of first clock period, the G(n-1 of S/R (n-1) output) be low level signal, first clock signal clk is a high level signal, the 5th transistor M5 opens, first capacitor C 1 exports the electric signal of storage to by M5 the output terminal of shift register, so be high level signal the signal G(n of the output terminal of shift register output), and be low level signal the reset signal G(n+1 of S/R this moment (n+1) output), so M3 closes, second clock signal CLKB is a low level signal, event M4 closes, not the signal G(n that output terminal is exported) exert an influence.
Phase III: the preceding semiperiod of second clock period, the G(n-1 of S/R (n-1) output) be low level signal, first clock signal clk is a low level signal, transistor M5 closes, the reset signal G(n+1 of S/R this moment (n+1) output) be high level signal, second clock signal CLKB is a high level signal, so M3 opens, M4 opens, this moment, supply voltage VSS made the signal G(n of the output terminal output of shift register simultaneously by M4) be low level signal, also not to the signal G(n of output terminal output) exert an influence for low level signal.
Quadravalence section: the later half cycle of second clock period, the G(n-1 of S/R (n-1) output) be low level signal, first clock signal clk is a high level signal, the 5th transistor M5 opens, the reset signal G(n+1 of S/R this moment (n+1) output) be low level signal, second clock signal CLKB is a low level signal, so M3 closes, M4 closes, also not to the signal G(n of output terminal output) exert an influence for low level signal.
The above-mentioned analysis of the course of work by two pairs of shift registers of the utility model embodiment as can be known, when the shift register among the utility model embodiment two has realized that the shift register module that comprises breaks down within it, utilize and repair the function that module replaces shift register module, and then guarantee that this shift register module that breaks down does not influence the work of its next stage shift register.
Below by embodiment three, the gate driver circuit that is made of a plurality of above-mentioned shift registers is described.
Embodiment three
The utility model embodiment three provides a kind of gate driver circuit, its structural representation as shown in Figure 7, described gate driver circuit comprises a plurality of as arbitrary described shift register among the embodiment three, wherein:
Except that first shift register and last shift register, the reset signal input end of the output terminal of all the other each shift registers and the upper level shift register that is adjacent is connected with the pumping signal input end of the next stage shift register that is adjacent, and gate driver circuit is sequentially exported the signal of the output terminal output of shift registers at different levels;
The output terminal of first shift register is connected with the pumping signal input end of second shift register, and the output terminal of last shift register is connected with the reset signal input end of a last shift register that is adjacent;
The pumping signal input end incoming frame start signal of first shift register;
First clock signal input terminal of odd number shift register is imported first clock signal, second clock signal input part input second clock signal;
First clock signal input terminal input second clock signal of even number shift register, the second clock signal input part is imported first clock signal;
Supply voltage VSS imports shift registers at different levels by supply voltage VSS input end;
First clock signal clk, second clock signal CLKB and VSS are the signals that guarantees the shift register operate as normal, and described CLK is opposite with the CLKB phase place.
Embodiment four
The utility model embodiment four provides a kind of restorative procedure to the gate driver circuit described in the embodiment three, and described method comprises:
When the arbitrary shift register module in gate driver circuit breaks down, being connected of the pumping signal input end of the shift register under the pumping signal input end that disconnects this shift register module that breaks down and this shift register module that breaks down, and being connected of the pumping signal input end of the pumping signal input end of the reparation module of the described shift register of conducting and described shift register;
Being connected of the output terminal of the reparation module of the described shift register of conducting and the output terminal of described shift register.
With the structural representation of gate driver circuit shown in Figure 8 for instance, suppose that the 2nd shift register S/R (2) in the gate driver circuit breaks down or invalid, and other shift registers all do not break down or when invalid, then can cut off being connected of pumping signal input end (indicating with solid rectangle among Fig. 8) of the pumping signal input end InPut of shift register module of shift register S/R (2) and the reparation module of shift register S/R (n), and being connected of the pumping signal input end of the pumping signal input end of the reparation module of the described shift register of conducting and described shift register (indicating to add solid rim in the open circle among Fig. 8); Being connected of the output terminal of the reparation module of the described shift register of conducting and the output terminal of described shift register (indicating to add solid rim in the open circle among Fig. 8).
If the shift register in the above-mentioned gate driver circuit is a shift register shown in Figure 5, then the shift register under the pumping signal input end that can cut off this shift register module that breaks down by the laser repairing technology and the shift register module that this breaks down gets final product being connected of pumping signal input end.
Embodiment five
The utility model embodiment five provides a kind of display device, and described display device comprises the gate driver circuit described in the embodiment four.
Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these are revised and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these changes and modification interior.
Claims (10)
1. a shift register is characterized in that, described shift register comprises: output terminal, pumping signal input end and first clock signal input terminal, and first can connect link, second can connect link and shift register module and reparation module; Described shift register module comprises output terminal, pumping signal input end and is used to receive first clock signal input terminal of clock signal of first clock signal input terminal input of shift register; Described reparation module comprises output terminal and pumping signal input end; Wherein:
Described first can connect link be arranged at shift register pumping signal input end, shift register module the pumping signal input end and repair between the pumping signal input end of module, be used for when shift register module breaks down, disconnect being connected of pumping signal input end of the pumping signal input end of shift register module and shift register, and being connected of pumping signal input end of the pumping signal input end of module and shift register repaired in conducting;
Described second can connect link be arranged at shift register output terminal, shift register module output terminal and repair between the output terminal of module, be used for when shift register module breaks down, being connected of output terminal of the output terminal of module and shift register repaired in conducting;
Described shift register module is used for the pumping signal of basis from the pumping signal input end reception of self, and the clock signal that will receive from first clock signal input terminal of self is from the output terminal output of self;
Described reparation module is used for when shift register module breaks down, after the pumping signal that will receive from the pumping signal input end of self is carried out the delay of half clock period, from the output terminal output of self.
2. shift register as claimed in claim 1 is characterized in that, described reparation module comprises: first electric capacity and the 5th transistor;
Described first electric capacity, the one end links to each other other end ground connection with the pumping signal input end of repairing module;
Described the 5th transistor, its grid links to each other with first clock signal input terminal, and first limit links to each other with the pumping signal input end of repairing module, and second limit links to each other with the output terminal of repairing module.
3. shift register as claimed in claim 2, it is characterized in that, described shift register also comprises the reset signal input end, described shift register module also comprises the reset signal input end, the reset signal input end of described shift register links to each other with the reset signal input end of described shift register module, and described shift register module comprises:
Load module is used for receiving pumping signal from the pumping signal input end of shift register module, and draws control signal to drawing in the node output between load module and the last drawing-die piece;
Last drawing-die piece, be used for according on draw node on draw control signal, the signal of first clock signal input terminal input is offered the output terminal of shift register module;
Reseting module is used for the reset signal of basis from the reset signal input end reception of shift register module, upwards draws the output terminal of node and shift register module that supply voltage is provided.
4. shift register as claimed in claim 3 is characterized in that, described load module comprises:
The first transistor, its first limit jointly links to each other with the pumping signal input end of shift register module with grid, its second limit with on draw node to link to each other.
5. shift register as claimed in claim 4 is characterized in that, the described drawing-die piece of going up comprises: the transistor seconds and second electric capacity;
Described transistor seconds, its grid with on draw node to link to each other, first limit links to each other with first clock signal input terminal, the output terminal of second limit and shift register module links to each other;
Described second electric capacity, the one end with on draw node to link to each other, the output terminal of the other end and shift register module links to each other.
6. shift register as claimed in claim 5, it is characterized in that, described shift register also comprises the second clock signal input part, described shift register module also comprises the second clock signal input part of the clock signal of the second clock signal input part input that is used to receive shift register, and described reseting module comprises: the 3rd transistor and the 4th transistor;
Described the 3rd transistor, the reset signal input end of its grid and shift register module links to each other, first limit with on draw node to link to each other, second limit links to each other with supply voltage;
Described the 4th transistor, the second clock signal input part of its grid and shift register module links to each other, and the output terminal of first limit and shift register module links to each other, and second limit links to each other with supply voltage.
7. shift register as claimed in claim 6, it is characterized in that, described first can connect link is used for when shift register module does not break down, being connected of the pumping signal input end of conducting shift register module and the pumping signal input end of shift register, and being connected of pumping signal input end of the pumping signal input end of module and shift register repaired in conducting;
Described second can connect link is used for when shift register module does not break down, and the output terminal of conducting shift register module is connected with the output terminal of shift register, and being connected of output terminal of the output terminal of module and shift register repaired in conducting.
8. shift register as claimed in claim 5 is characterized in that, the ratio of the electric capacity of described first electric capacity and second electric capacity is more than or equal to 5:1.
9. a gate driver circuit is characterized in that, comprises a plurality of as shift register as described in the arbitrary claim of claim 1-8;
Except that first shift register and last shift register, the output terminal of all the other each shift registers is connected with the reset signal input end of the upper level shift register that is adjacent and the pumping signal input end of the next stage shift register that is adjacent respectively, and gate driver circuit is sequentially exported the signal of the output terminal output of shift registers at different levels;
The output terminal of first shift register is connected with the pumping signal input end of second shift register, and the output terminal of last shift register is connected with the reset signal input end of a last shift register that is adjacent;
The pumping signal input end incoming frame start signal of first shift register.
10. a display device is characterized in that, described display device comprises the described gate driver circuit of claim 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320103369 CN203085131U (en) | 2013-03-07 | 2013-03-07 | Shifting register, grid electrode drive circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320103369 CN203085131U (en) | 2013-03-07 | 2013-03-07 | Shifting register, grid electrode drive circuit and display device |
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| CN203085131U true CN203085131U (en) | 2013-07-24 |
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| CN 201320103369 Expired - Fee Related CN203085131U (en) | 2013-03-07 | 2013-03-07 | Shifting register, grid electrode drive circuit and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014134877A1 (en) * | 2013-03-07 | 2014-09-12 | 京东方科技集团股份有限公司 | Shift register, gate electrode drive circuit and repairing method thereof, and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014134877A1 (en) * | 2013-03-07 | 2014-09-12 | 京东方科技集团股份有限公司 | Shift register, gate electrode drive circuit and repairing method thereof, and display device |
| CN103198782B (en) * | 2013-03-07 | 2016-02-10 | 京东方科技集团股份有限公司 | Shift register, gate driver circuit and restorative procedure thereof and display device |
| US9384686B2 (en) | 2013-03-07 | 2016-07-05 | Boe Technology Group Co., Ltd | Shift register, gate driving circuit and repairing method therefor, and display device |
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