CN203057108U - Power tube driving device with driving pulse regulation function - Google Patents
Power tube driving device with driving pulse regulation function Download PDFInfo
- Publication number
- CN203057108U CN203057108U CN 201320020341 CN201320020341U CN203057108U CN 203057108 U CN203057108 U CN 203057108U CN 201320020341 CN201320020341 CN 201320020341 CN 201320020341 U CN201320020341 U CN 201320020341U CN 203057108 U CN203057108 U CN 203057108U
- Authority
- CN
- China
- Prior art keywords
- input
- output
- type flip
- flip flop
- processing module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Images
Landscapes
- Inverter Devices (AREA)
Abstract
The utility model is applicable to the technical field of signal processing and provides a power tube driving device with a driving pulse regulation function. The power tube driving device with the driving pulse regulation function comprises a minimum turn-on time processing module, a maximum turn-on time processing module, a minimum turn-off time processing module and a turn-on time deviation processing module, thus the high level and the low level of each cycle in the driving pulse signal of a power tube are optimized, thus the widths of the high level and the low level of each cycle are kept in the reasonable range, so as to effectively reduce the power consumption of the power tube and ensure the safe and reliable operation of the power tube, and moreover whether the system is working normally or not is judged according to the width difference of the high levels of the two adjacent cycles, and when the width difference of the high levels exceeds the turn-on time deviation threshold, the system is judged to be normal, and simultaneously a driving circuit is controlled to turn off the power tube, thus the driving control safety of the power tube is improved.
Description
Technical field
The utility model belongs to the signal process field, relates in particular to a kind of power tube drive unit that possesses the driving pulse regulatory function.
Background technology
At present, along with power tube is widely used in every field, also more and more higher for the requirement of its drive circuit.The drive circuit commonly used that prior art provides all is to adopt discrete device to form, its complex structure, and cost height and circuit volume are big; In addition, prior art also provides a kind of integrated circuit (IC) chip, though solved the bulky problem of circuit, but its high-low level time to driving pulse does not often deal with or handles comprehensively inadequately, will make power tube too small, situation such as ON time is long, the ON time of adjacent periods is inconsistent of switch gap time in being subjected to the process of driving pulse control, occur like this, and then the power consumption that causes power tube becomes big and caloric value increases, even power tube is burnt out.
The utility model content
The purpose of this utility model is to provide a kind of power tube drive unit that possesses the driving pulse regulatory function, the problem that is intended to solve existing in prior technology cost height, power consumption is big, caloric value is high and causes power tube to burn out easily.
The utility model is achieved in that a kind of power tube drive unit that possesses the driving pulse regulatory function, comprises drive circuit, and described drive circuit connects the grid of power tube to control the break-make of described power tube, and described power tube drive unit also comprises:
Minimum ON time processing module, maximum ON time processing module, minimum turn-off time processing module and ON time deviation processing module;
The input of described minimum ON time processing module inserts drive pulse signal, described minimum ON time processing module receives described drive pulse signal, whether less than minimum ON time at interval to judge the high level width of described drive pulse signal, be, it then is described minimum ON time interval with described high level width adjustment,, then normally do not export described drive pulse signal;
The input of described maximum ON time processing module connects the output of described minimum ON time processing module, described maximum ON time processing module judges that whether the high level width of the drive pulse signal that described minimum ON time processing module is exported is greater than maximum ON time interval, be, then the high level width adjustment of the drive pulse signal that described minimum ON time module is exported is described maximum ON time interval,, then will normally not export the drive pulse signal of described minimum ON time module output;
The input of described minimum turn-off time processing module connects the output of described maximum ON time processing module, described minimum turn-off time processing module judges that whether the low level width of the drive pulse signal that described maximum ON time processing module is exported is less than the minimum turn-off time interval, be, then the high level of subsequent cycle in the drive pulse signal of described maximum ON time processing module output is adjusted into low level and is not less than the described minimum turn-off time interval until described low level width, not, then normally export the drive pulse signal of described maximum ON time processing module output;
The input of described ON time deviation processing module connects the output of described minimum turn-off time processing module, described ON time deviation processing module judges that whether the high level width difference in adjacent two cycles is greater than the ON time deviation threshold in the drive pulse signal of described minimum turn-off time processing module output, be, then output low level is controlled described drive circuit switch-off power pipe,, then normally do not export the drive pulse signal of described minimum turn-off time processing module output to described drive circuit.
The utility model comprises described minimum ON time processing module by employing, described maximum ON time processing module, the power tube drive unit that possesses the driving pulse regulatory function of described minimum turn-off time processing module and described ON time deviation processing module, simple in structure, cost is low, can be optimized processing to high level and the low level in each cycle in the drive pulse signal of power tube, the high-low level width in each cycle is remained in the rational interval, thereby reduce the power consumption of power tube effectively, the work that the guaranteed output pipe is safe and reliable, and can judge whether system is working properly according to the high level width difference of two adjacent periods, and decision-making system is unusual when described high level width difference surpasses the ON time deviation threshold, control drive circuit switch-off power pipe simultaneously, improve the driving control fail safe to power tube, thereby solved existing in prior technology cost height, power consumption is big, caloric value height and the problem that causes power tube to burn out easily.
Description of drawings
Fig. 1 is the modular structure figure of the power tube drive unit that possesses the driving pulse regulatory function that provides of the utility model embodiment;
Fig. 2 is the exemplary circuit structure chart of the power tube drive unit that possesses the driving pulse regulatory function that provides of the utility model embodiment;
Fig. 3 is the oscillogram of each related road drive pulse signal of the power tube drive unit that possesses the driving pulse regulatory function that provides of the utility model embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
The utility model embodiment comprises minimum ON time processing module by employing, maximum ON time processing module, the power tube drive unit that possesses the driving pulse regulatory function of minimum turn-off time processing module and ON time deviation processing module, simple in structure, cost is low, can be optimized processing to high level and the low level in each cycle in the drive pulse signal of power tube, the high-low level width in each cycle is remained in the rational interval, thereby reduce the power consumption of power tube effectively, the work that the guaranteed output pipe is safe and reliable, and can judge whether system is working properly according to the high level width difference of two adjacent periods, and decision-making system is unusual when high level width difference surpasses the ON time deviation threshold, control drive circuit switch-off power pipe simultaneously, improved the driving control fail safe to power tube.
Fig. 1 shows the modular structure of the power tube drive unit that possesses the driving pulse regulatory function that the utility model embodiment provides, and for convenience of explanation, only shows the part relevant with the utility model embodiment, and details are as follows:
The power tube drive unit that possesses the driving pulse regulatory function comprises drive circuit 100, and drive circuit 100 connects the grid of power tube M with the break-make of control power tube M; Drive circuit 100 is power tube drive circuit commonly used, so its internal structure does not repeat them here.
The power tube drive unit also comprises:
Minimum ON time processing module 200, maximum ON time processing module 300, minimum turn-off time processing module 400 and ON time deviation processing module 500.
The input of minimum ON time processing module 200 inserts drive pulse signal, minimum ON time processing module 200 receives this drive pulse signal, whether less than minimum ON time at interval to judge the high level width of this drive pulse signal, be, it then is minimum ON time interval with the high level width adjustment,, then normally do not export drive pulse signal;
The input of maximum ON time processing module 300 connects the output of minimum ON time processing module 200, maximum ON time processing module 300 judges that whether the high level width of the drive pulse signal that minimum ON time processing module 200 is exported is greater than maximum ON time interval, be, then the high level width adjustment of the drive pulse signal that minimum ON time module 200 is exported is maximum ON time interval,, then will normally not export the drive pulse signal of minimum ON time module output;
The input of minimum turn-off time processing module 400 connects the output of maximum ON time processing module 300, minimum turn-off time processing module 400 judges that whether the low level width of the drive pulse signal that maximum ON time processing module 300 is exported is less than the minimum turn-off time interval, be, then the high level of subsequent cycle in the drive pulse signal of maximum ON time processing module 300 outputs is adjusted into low level and is not less than the minimum turn-off time interval until low level width, not, then normally export the drive pulse signal of maximum ON time processing module 300 outputs;
The input of ON time deviation processing module 500 connects the output of minimum turn-off time processing module 400, ON time deviation processing module 500 judges that whether the high level width difference in adjacent two cycles is greater than the ON time deviation threshold in the drive pulse signal of minimum turn-off time processing module 400 output, be, then output low level is controlled drive circuit 100 switch-off power pipe M,, then normally do not export the drive pulse signal of minimum turn-off time processing module 400 outputs to drive circuit 100.
Fig. 2 shows the exemplary circuit structure of the power tube drive unit that possesses the driving pulse regulatory function that the utility model embodiment provides, and for convenience of explanation, only shows the part relevant with the utility model embodiment, and details are as follows:
As the utility model one preferred embodiment, minimum ON time processing module 200 comprises:
D type flip flop U1, d type flip flop U2, inverter U3, with door U4, an inverter U5, with a door U6, current source I1, PMOS pipe Q1, NMOS pipe Q2, capacitor C 1, comparator U7 and first reference voltage source 201;
The common contact of the input of the trigger end CP of d type flip flop U1 and the trigger end CP of d type flip flop U2 and inverter U3 is the input of minimum ON time processing module 200, the input of the input D of d type flip flop U1 and the input D of d type flip flop U2 and current source I1 all inserts high level, the inverted reset end RST of d type flip flop U2 and negative output terminal Q/ sky connect, the positive output end Q sky of d type flip flop U1 connects, be connected to the negative output terminal Q/ of d type flip flop U1 altogether with the grid of the grid of the first input end 1 of door U4 and PMOS pipe Q1 and NMOS pipe Q2, the output that is connected described inverter U3 with second input 2 of door U4, the input of inverter U5 and output be connected respectively with the output 3 of door U4 and with the first input end 1 of door U6, the positive output end Q that is connected d type flip flop U2 with second input 2 of door U6, with the output 3 of door U6 be the output of minimum ON time processing module 200, the source electrode of PMOS pipe Q1 connects the output of current source I1, the drain electrode of the drain electrode of PMOS pipe Q1 and NMOS pipe Q2 and first end of capacitor C 1 are connected to the inverting input of comparator U7 altogether, the source electrode of NMOS pipe Q2 and second end of capacitor C 1 are connected to ground altogether, and the in-phase input end of comparator U7 and output are connected the inverted reset end RST of first reference voltage source 201 and d type flip flop U1 respectively.
As the utility model one preferred embodiment, maximum ON time processing module 300 comprises:
Inverter U8, PMOS pipe Q3, NMOS manage Q4, current source I2, capacitor C 2, second reference voltage source 301, comparator U9, rest-set flip-flop U10, inverter U11 reaches and a door U12;
The second input S of the input of inverter U8 and rest-set flip-flop U10 and with the common contact of second input 2 of door U12 be the input of maximum ON time processing module 300, the grid of the grid of PMOS pipe Q3 and NMOS pipe Q4 is connected to the output of inverter U8 altogether, the source electrode of PMOS pipe Q3 connects the output of current source I2, the input of current source I2 inserts high level, the drain electrode of the drain electrode of PMOS pipe Q3 and NMOS pipe Q4 and first end of capacitor C 2 are connected to the inverting input of comparator U9 altogether, the source electrode of second end of capacitor C 2 and NMOS pipe Q4 is connected to ground altogether, the in-phase input end of comparator U9 and output are connected the first input end R of second reference voltage source 301 and rest-set flip-flop U10 respectively, the negative output terminal Q/ sky of rest-set flip-flop U10 connects, the input of inverter U11 and output be connected respectively rest-set flip-flop U10 positive output end Q and with the first input end 1 of door U12, with the output 3 of door U12 be the output of maximum ON time processing module 300.
As the utility model one preferred embodiment, minimum turn-off time processing module 400 comprises:
Current source I3, PMOS pipe Q5, NMOS pipe Q6, capacitor C 3, the 3rd reference voltage source 401, comparator U13, rest-set flip-flop U14, inverter U15, inverter U16, inverter U17 and d type flip flop U18;
The input D of the input of current source I3 and d type flip flop U18 all inserts high level, the source electrode of PMOS pipe Q5 connects the output of current source I3, the grid of the grid of PMOS pipe Q5 and NMOS pipe Q6, the common contact of the first input end R of rest-set flip-flop U14 and the input of inverter U16 is the input of minimum turn-off time processing module 400, the drain electrode of the drain electrode of PMOS pipe Q5 and NMOS pipe Q6 and first end of capacitor C 3 are connected to the inverting input of comparator U13 altogether, the source electrode of second end of capacitor C 3 and NMOS pipe Q6 is connected to ground altogether, the in-phase input end of comparator U13 and output are connected the second input S of the 3rd reference voltage source 401 and rest-set flip-flop U14 respectively, the positive output end Q sky of rest-set flip-flop U14 connects, the input of inverter U15 is connected the negative output terminal Q/ of rest-set flip-flop U14 and the inverted reset end RST of d type flip flop U18 respectively with output, the input of inverter U17 is connected with the output of inverter U16 and the trigger end CP of d type flip flop U18 respectively with output, the positive output end Q of d type flip flop U18 is the output of minimum turn-off time processing module 400, and the negative output terminal Q/ sky of d type flip flop U18 connects.
As the utility model one preferred embodiment, ON time deviation processing module 500 comprises:
D type flip flop U19, d type flip flop U20, d type flip flop U21, inverter U22, three end NAND gate U23, three end NOR gate U24, inverter U25, NOR gate U26, NAND gate U27, current source I4, PMOS manages Q7, NMOS manages Q8, capacitor C 4, the 4th reference voltage source 501, comparator U28, inverter U29, inverter U30, three end NOR gate U31, three end NOR gate U32, inverter U33, d type flip flop U34, inverter U35, d type flip flop U36, d type flip flop U37, inverter U38, NAND gate U39, NOR gate U40, current source I5, PMOS manages Q9, NMOS manages Q10, current source I6, capacitor C 5, current source I7, PMOS manages Q11, NMOS manages Q12, current source I8, capacitor C 6, NMOS manages Q13, NMOS manages Q14, amplifier U41, the 5th reference voltage source 502, NMOS manages Q15, NMOS manages Q16, the 6th reference voltage source 503, the 7th reference voltage source 504, comparator U42, comparator U43, NAND gate U44, d type flip flop U45 and NAND gate U46;
The trigger end CP of d type flip flop U19 and the trigger end CP of d type flip flop U20, the trigger end CP of d type flip flop U21, the input of inverter U22, the first input end of three end NAND gate U23, the input of inverter U29, the grid of PMOS pipe Q7, the common contact of the grid of NMOS pipe Q8 and second input 2 of NAND gate U46 is the input of ON time deviation processing module 500, the input D of d type flip flop U19 and the input of current source I4, the input of current source I5, the input of current source I6, the input of current source I7, the input of current source I8, the input D of d type flip flop U36, the input D of d type flip flop U37 and the input D of d type flip flop U45 all insert high level, the inverted reset end RST of d type flip flop U19 and negative output terminal Q/ sky connect, the input D of d type flip flop U20 connects the positive output end Q of d type flip flop U19, the inverted reset end RST of d type flip flop U20 and negative output terminal Q/ sky connect, the input D of d type flip flop U21 connects negative output terminal Q/, the positive output end Q while of d type flip flop U21 and second input 2 of three end NAND gate U23, second input 2 of three end NOR gate U24, the first input end 1 of the input of inverter U30 and three end NOR gate U31 is connected, the first input end 1 of the output termination three end NOR gate U24 of inverter U22,3 whiles of the 3rd input of three end NAND gate U23 and the 3rd input 3 of three end NOR gate U24, second input 2 of three end NOR gate U32, the trigger end CP of the output of inverter U35 and d type flip flop U36 is connected, the input of inverter U25 connects the positive output end Q of d type flip flop U20 simultaneously, second input 2 of NAND gate U27 and the first input end 1 of NAND gate U39, second input 2 of the first input end 1 of NOR gate U26 and NOR gate U40 is connected to the output of inverter U25 altogether, the grid of second input 2 of NOR gate U26 and PMOS pipe Q11 is connected to the output 4 of three end NAND gate U23 altogether, the grid of the first input end 1 of NOR gate U27 and NMOS pipe Q12 is connected to the output 4 of three end NOR gate U24 altogether, the output 3 of NOR gate U26 is connected the grid of NMOS pipe Q10 and the grid of PMOS pipe Q9 respectively with the output 3 of NOR gate U27, the output of current source I4 connects the source electrode of PMOS pipe Q7, the drain electrode of the drain electrode of PMOS pipe Q7 and NMOS pipe Q8 and first end of capacitor C 4 are connected to the inverting input of comparator U28 altogether, the source electrode of NMOS pipe Q8 and second end of capacitor C 4 are connected to ground altogether, the in-phase input end of comparator U28 connects the 4th reference voltage source 501, the output of comparator U28 is connected with second input 2 of three end NOR gate U31 and the first input end 1 of three end NOR gate U32 simultaneously, the grid of the input of inverter U33 and NMOS pipe Q13 is connected to the output 4 of three end NOR gate U31 altogether, the inverted reset end RST of the output termination d type flip flop U36 of inverter U33, the trigger end CP of d type flip flop U34 connects the output of inverter U29, the input D of d type flip flop U34 connects negative input end Q/, the inverted reset end RST sky of d type flip flop U34 connects, the input while of inverter U35 and the positive output end Q of d type flip flop U34, the 3rd input 3 of three end NOR gate U31 and the trigger end CP of d type flip flop U37 are connected, the positive output end Q of d type flip flop U36 is connected the grid of NMOS pipe Q15 and the grid of NMOS pipe Q16 respectively with the positive output end Q of d type flip flop U37, the equal sky of negative output terminal Q/ of the negative output terminal Q/ of d type flip flop U36 and d type flip flop U37 connects, the inverted reset end RST of d type flip flop U37 connects the output 3 of NOR gate U40, the input of inverter U38 is connected the output 4 of three end NOR gate U32 and second input 2 of NAND gate U39 respectively with output, the grid of the first input end 1 of NOR gate U40 and NMOS pipe Q14 is connected to the output 3 of NAND gate U39 altogether, the output of current source I5 connects the source electrode of PMOS pipe Q9, the drain electrode of the drain electrode of PMOS pipe Q9 and NMOS pipe Q10, the source electrode of first end of capacitor C 5 and NMOS pipe Q16 is connected to the source electrode of NMOS pipe Q14 altogether, the input of current source I6 connects the source electrode of NMOS pipe Q10, second end of the output of current source I6 and capacitor C 5 is connected to ground altogether, the output of current source I7 connects the source electrode of PMOS pipe Q11, the drain electrode of the drain electrode of PMOS pipe Q11 and NMOS pipe Q12, the source electrode of first end of capacitor C 6 and NMOS pipe Q15 is connected to the source electrode of NMOS pipe Q13 altogether, the input of current source I8 connects the source electrode of NMOS pipe Q12, second end of the output of current source I8 and capacitor C 6 is connected to ground altogether, the drain electrode of the drain electrode of NMOS pipe Q13 and NMOS pipe Q14 is connected to the inverting input of amplifier U41 altogether, the in-phase input end of amplifier U41 connects the 5th reference voltage source 502, the output of amplifier U41 is connected with inverting input, the drain electrode of Q16 is managed in the drain electrode of NMOS pipe Q15 simultaneously with NMOS, the in-phase input end of the inverting input of comparator U42 and comparator U43 connects, the inverting input of the in-phase input end of comparator U42 and comparator U43 is connected the 6th reference voltage source 503 and the 7th reference voltage source 504 respectively, the output of the output of comparator U42 and comparator U43 is connected first input end 1 and second input 2 of NAND gate U44 respectively, the output 3 of NAND gate U44 connects the trigger end CP of d type flip flop U45, the inverted reset end RST of d type flip flop U45 and the equal sky of positive output end Q connect, the first input end 1 of NAND gate U46 connects the negative output terminal Q/ of d type flip flop U45, and the output 3 of NAND gate U46 is the output of ON time deviation processing module 500.
In the utility model embodiment, first reference voltage source 201, second reference voltage source 301, the 3rd reference voltage source 401 and 501 output reference voltages of the 4th reference voltage source are identical, and the 5th reference voltage source 502, the 6th reference voltage source 503 and the 7th reference voltage source 504 are exported different reference voltages respectively.First reference voltage source 201, second reference voltage source 301, the 3rd reference voltage source 401, the 4th reference voltage source 501, the 5th reference voltage source 502, the 6th reference voltage source 503 and the 7th reference voltage source 504 all are reference voltage generating circuits of using always.
Below in conjunction with instantiation the above-mentioned power tube drive unit that possesses the driving pulse regulatory function is described further:
Suppose the waveform of the drive pulse signal A that minimum ON time processing module 200 receives as shown in Figure 3, drive pulse signal A imports the input of minimum ON time processing module 200 from left to right, period 3 T3 among the drive pulse signal A, exist the high level width less than minimum ON time interval T on_min among period 4 T4 and the period 5 T5, then minimum ON time processing module 200 is with period 3 T3, high level width adjustment among period 4 T4 and the period 5 T5 is to export drive pulse signal B behind the Ton_min to maximum ON time processing module 300; Maximum ON time processing module 300 through judgement determine drive pulse signal B second round T2 the high level width greater than maximum ON time interval T on_max, then be Ton_max and export drive pulse signal C to minimum turn-off time processing module 400 with the high level width adjustment that is about to T2 second round; Minimum turn-off time processing module 400 judges that the low level width of the period 4 T4 among the drive pulse signal C is less than minimum turn-off time interval Toff_min, then the high level among the period 5 T5 is adjusted into low level, and output driving pulse pulse signal D is to ON time deviation processing module 500; The difference of the high level width of the period 5 T5 ' among the ON time deviation processing module 500 judgement drive pulse signal D and the high level width of period 4 T4 ' is greater than ON time deviation threshold Ton_os, it is unusual to show that then system occurs, need will all become low level (shown in the drive pulse signal E among Fig. 3) with control drive circuit 100 switch-off power pipe M since period 5 T5 ' among the drive pulse signal D, thereby improve the driving fail safe to power tube M.
The utility model embodiment comprises minimum ON time processing module by employing, maximum ON time processing module, the power tube drive unit that possesses the driving pulse regulatory function of minimum turn-off time processing module and ON time deviation processing module, simple in structure, cost is low, can be optimized processing to high level and the low level in each cycle in the drive pulse signal of power tube, the high-low level width in each cycle is remained in the rational interval, thereby reduce the power consumption of power tube effectively, the work that the guaranteed output pipe is safe and reliable, and can judge whether system is working properly according to the high level width difference of two adjacent periods, and decision-making system is unusual when high level width difference surpasses the ON time deviation threshold, control drive circuit switch-off power pipe simultaneously, improve the driving control fail safe to power tube, thereby solved existing in prior technology cost height, power consumption is big, caloric value height and the problem that causes power tube to burn out easily.
The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (5)
1. a power tube drive unit that possesses the driving pulse regulatory function comprises drive circuit, and described drive circuit connects the grid of power tube to control the break-make of described power tube, it is characterized in that described power tube drive unit also comprises:
Minimum ON time processing module, maximum ON time processing module, minimum turn-off time processing module and ON time deviation processing module;
The input of described minimum ON time processing module inserts drive pulse signal, described minimum ON time processing module receives described drive pulse signal, whether less than minimum ON time at interval to judge the high level width of described drive pulse signal, be, it then is described minimum ON time interval with described high level width adjustment,, then normally do not export described drive pulse signal;
The input of described maximum ON time processing module connects the output of described minimum ON time processing module, described maximum ON time processing module judges that whether the high level width of the drive pulse signal that described minimum ON time processing module is exported is greater than maximum ON time interval, be, then the high level width adjustment of the drive pulse signal that described minimum ON time module is exported is described maximum ON time interval,, then will normally not export the drive pulse signal of described minimum ON time module output;
The input of described minimum turn-off time processing module connects the output of described maximum ON time processing module, described minimum turn-off time processing module judges that whether the low level width of the drive pulse signal that described maximum ON time processing module is exported is less than the minimum turn-off time interval, be, then the high level of subsequent cycle in the drive pulse signal of described maximum ON time processing module output is adjusted into low level and is not less than the described minimum turn-off time interval until described low level width, not, then normally export the drive pulse signal of described maximum ON time processing module output;
The input of described ON time deviation processing module connects the output of described minimum turn-off time processing module, described ON time deviation processing module judges that whether the high level width difference in adjacent two cycles is greater than the ON time deviation threshold in the drive pulse signal of described minimum turn-off time processing module output, be, then output low level is controlled described drive circuit switch-off power pipe,, then normally do not export the drive pulse signal of described minimum turn-off time processing module output to described drive circuit.
2. power tube drive unit as claimed in claim 1 is characterized in that, described minimum ON time processing module comprises:
D type flip flop U1, d type flip flop U2, inverter U3, with door U4, an inverter U5, with a door U6, current source I1, PMOS pipe Q1, NMOS pipe Q2, capacitor C 1, comparator U7 and first reference voltage source;
The common contact of the input of the trigger end of the trigger end of described d type flip flop U1 and described d type flip flop U2 and described inverter U3 is the input of described minimum ON time processing module, the input of the input of the input of described d type flip flop U1 and described d type flip flop U2 and described current source I1 all inserts high level, inverted reset end and the negative output terminal sky of described d type flip flop U2 connect, the positive output end sky of described d type flip flop U1 connects, the grid that first input end and described PMOS described and door U4 manage Q1 and the grid of described NMOS pipe Q2 are connected to the negative output terminal of described d type flip flop U1 altogether, described second input with door U4 is connected the output of described inverter U3, the input of described inverter U5 is connected output and first input end described and door U6 described and door U4 respectively with output, described second input with door U6 is connected the positive output end of described d type flip flop U2, described output with door U6 is the output of described minimum ON time processing module, the source electrode of described PMOS pipe Q1 connects the output of described current source I1, the drain electrode of the drain electrode of described PMOS pipe Q1 and described NMOS pipe Q2 and first end of described capacitor C 1 are connected to the inverting input of described comparator U7 altogether, the source electrode of described NMOS pipe Q2 and second end of described capacitor C 1 are connected to ground altogether, and the in-phase input end of described comparator U7 and output are connected the inverted reset end of described first reference voltage source and described d type flip flop U1 respectively.
3. power tube drive unit as claimed in claim 1 is characterized in that, described maximum ON time processing module comprises:
Inverter U8, PMOS pipe Q3, NMOS manage Q4, current source I2, capacitor C 2, second reference voltage source, comparator U9, rest-set flip-flop U10, inverter U11 reaches and a door U12;
The common contact of second input of second input of the input of described inverter U8 and described rest-set flip-flop U10 and described and door U12 is the input of described maximum ON time processing module, the grid of the grid of described PMOS pipe Q3 and described NMOS pipe Q4 is connected to the output of described inverter U8 altogether, the source electrode of described PMOS pipe Q3 connects the output of described current source I2, the input of described current source I2 inserts high level, the drain electrode of the drain electrode of described PMOS pipe Q3 and described NMOS pipe Q4 and first end of described capacitor C 2 are connected to the inverting input of described comparator U9 altogether, the source electrode of second end of described capacitor C 2 and described NMOS pipe Q4 is connected to ground altogether, the in-phase input end of described comparator U9 and output are connected the first input end of described second reference voltage source and described rest-set flip-flop U10 respectively, the negative output terminal sky of described rest-set flip-flop U10 connects, the input of described inverter U11 and output are connected positive output end and the first input end described and door U12 of described rest-set flip-flop U10 respectively, and described output with door U12 is the output of described maximum ON time processing module.
4. power tube drive unit as claimed in claim 1 is characterized in that, described minimum turn-off time processing module comprises:
Current source I3, PMOS pipe Q5, NMOS pipe Q6, capacitor C 3, the 3rd reference voltage source, comparator U13, rest-set flip-flop U14, inverter U15, inverter U16, inverter U17 and d type flip flop U18;
The input of the input of described current source I3 and described d type flip flop U18 all inserts high level, the source electrode of described PMOS pipe Q5 connects the output of described current source I3, the grid of the grid of described PMOS pipe Q5 and described NMOS pipe Q6, the common contact of the input of the first input end of described rest-set flip-flop U14 and described inverter U16 is the input of described minimum turn-off time processing module, the drain electrode of the drain electrode of described PMOS pipe Q5 and described NMOS pipe Q6 and first end of described capacitor C 3 are connected to the inverting input of comparator U13 altogether, the source electrode of second end of described capacitor C 3 and described NMOS pipe Q6 is connected to ground altogether, the in-phase input end of described comparator U13 and output are connected second input of described the 3rd reference voltage source and described rest-set flip-flop U14 respectively, the positive output end sky of described rest-set flip-flop U14 connects, the input of described inverter U15 is connected the negative output terminal of described rest-set flip-flop U14 and the inverted reset end of described d type flip flop U18 respectively with output, the input of described inverter U17 is connected with the output of described inverter U16 and the trigger end of described d type flip flop U18 respectively with output, the positive output end of described d type flip flop U18 is the output of described minimum turn-off time processing module, and the negative output terminal sky of described d type flip flop U18 connects.
5. power tube drive unit as claimed in claim 1 is characterized in that, described ON time deviation processing module comprises:
D type flip flop U19, d type flip flop U20, d type flip flop U21, inverter U22, three end NAND gate U23, three end NOR gate U24, inverter U25, NOR gate U26, NAND gate U27, current source I4, PMOS manages Q7, NMOS manages Q8, capacitor C 4, the 4th reference voltage source, comparator U28, inverter U29, inverter U30, three end NOR gate U31, three end NOR gate U32, inverter U33, d type flip flop U34, inverter U35, d type flip flop U36, d type flip flop U37, inverter U38, NAND gate U39, NOR gate U40, current source I5, PMOS manages Q9, NMOS manages Q10, current source I6, capacitor C 5, current source I7, PMOS manages Q11, NMOS manages Q12, current source I8, capacitor C 6, NMOS manages Q13, NMOS manages Q14, amplifier U41, the 5th reference voltage source, NMOS manages Q15, NMOS manages Q16, the 6th reference voltage source, the 7th reference voltage source, comparator U42, comparator U43, NAND gate U44, d type flip flop U45 and NAND gate U46;
The trigger end of the trigger end of described d type flip flop U19 and described d type flip flop U20, the trigger end of described d type flip flop U21, the input of described inverter U22, the first input end of described three end NAND gate U23, the input of described inverter U29, the grid of described PMOS pipe Q7, the common contact of the grid of described NMOS pipe Q8 and second input of described NAND gate U46 is the input of described ON time deviation processing module, the input of the input of described d type flip flop U19 and described current source I4, the input of described current source I5, the input of described current source I6, the input of described current source I7, the input of described current source I8, the input of described d type flip flop U36, the input of the input of described d type flip flop U37 and described d type flip flop U45 all inserts high level, inverted reset end and the negative output terminal sky of described d type flip flop U19 connect, the input of described d type flip flop U20 connects the positive output end of described d type flip flop U19, inverted reset end and the negative output terminal sky of described d type flip flop U20 connect, the input of described d type flip flop U21 connects negative output terminal, the positive output end while of described d type flip flop U21 and second input of described three end NAND gate U23, second input of described three end NOR gate U24, the first input end of the input of described inverter U30 and described three end NOR gate U31 is connected, the first input end of the described three end NOR gate U24 of the output termination of described inverter U22, the 3rd input while of described three end NAND gate U23 and the 3rd input of described three end NOR gate U24, second input of described three end NOR gate U32, the trigger end of the output of described inverter U35 and described d type flip flop U36 is connected, the input of described inverter U25 connects the positive output end of described d type flip flop U20 simultaneously, second input of described NAND gate U27 and the first input end of described NAND gate U39, second input of the first input end of described NOR gate U26 and described NOR gate U40 is connected to the output of described inverter U25 altogether, the grid of second input of described NOR gate U26 and described PMOS pipe Q11 is connected to the output of described three end NAND gate U23 altogether, the grid of the first input end of described NOR gate U27 and described NMOS pipe Q12 is connected to the output of described three end NOR gate U24 altogether, the output of described NOR gate U26 is connected the grid of described NMOS pipe Q10 and the grid of described PMOS pipe Q9 respectively with the output of described NOR gate U27, the output of described current source I4 connects the source electrode of described PMOS pipe Q7, the drain electrode of the drain electrode of described PMOS pipe Q7 and described NMOS pipe Q8 and first end of described capacitor C 4 are connected to the inverting input of described comparator U28 altogether, the source electrode of described NMOS pipe Q8 and second end of described capacitor C 4 are connected to ground altogether, the in-phase input end of described comparator U28 connects described the 4th reference voltage source, the output of described comparator U28 is connected with second input of described three end NOR gate U31 and the first input end of described three end NOR gate U32 simultaneously, the grid of the input of described inverter U33 and described NMOS pipe Q13 is connected to the output of described three end NOR gate U31 altogether, the inverted reset end of the described d type flip flop U36 of output termination of described inverter U33, the trigger end of described d type flip flop U34 connects the output of described inverter U29, the input of described d type flip flop U34 connects negative input end, the inverted reset end sky of described d type flip flop U34 connects, the input while of described inverter U35 and the positive output end of described d type flip flop U34, the 3rd input of described three end NOR gate U31 and the trigger end of described d type flip flop U37 are connected, the positive output end of described d type flip flop U36 is connected the grid of described NMOS pipe Q15 and the grid of described NMOS pipe Q16 respectively with the positive output end of described d type flip flop U37, the equal sky of the negative output terminal of the negative output terminal of described d type flip flop U36 and described d type flip flop U37 connects, the inverted reset end of described d type flip flop U37 connects the output of described NOR gate U40, the input of described inverter U38 is connected the output of described three end NOR gate U32 and second input of described NAND gate U39 respectively with output, the grid of the first input end of described NOR gate U40 and described NMOS pipe Q14 is connected to the output of described NAND gate U39 altogether, the output of described current source I5 connects the source electrode of described PMOS pipe Q9, the drain electrode of the drain electrode of described PMOS pipe Q9 and described NMOS pipe Q10, the source electrode of first end of described capacitor C 5 and described NMOS pipe Q16 is connected to the source electrode of described NMOS pipe Q14 altogether, the input of described current source I6 connects the source electrode of described NMOS pipe Q10, second end of the output of described current source I6 and described capacitor C 5 is connected to ground altogether, the output of described current source I7 connects the source electrode of described PMOS pipe Q11, the drain electrode of the drain electrode of described PMOS pipe Q11 and described NMOS pipe Q12, the source electrode of first end of described capacitor C 6 and described NMOS pipe Q15 is connected to the source electrode of described NMOS pipe Q13 altogether, the input of described current source I8 connects the source electrode of described NMOS pipe Q12, second end of the output of described current source I8 and described capacitor C 6 is connected to ground altogether, the drain electrode of the drain electrode of described NMOS pipe Q13 and described NMOS pipe Q14 is connected to the inverting input of described amplifier U41 altogether, the in-phase input end of described amplifier U41 connects described the 5th reference voltage source, the output of described amplifier U41 is connected with described inverting input, the drain electrode of Q16 is managed in the drain electrode of described NMOS pipe Q15 simultaneously with described NMOS, the in-phase input end of the inverting input of described comparator U42 and described comparator U43 connects, the inverting input of the in-phase input end of described comparator U42 and described comparator U43 is connected described the 6th reference voltage source and described the 7th reference voltage source respectively, the output of the output of described comparator U42 and described comparator U43 is connected first input end and second input of described NAND gate U44 respectively, the output of described NAND gate U44 connects the trigger end of described d type flip flop U45, the inverted reset end of described d type flip flop U45 and the equal sky of positive output end connect, the first input end of described NAND gate U46 connects the negative output terminal of described d type flip flop U45, and the output of described NAND gate U46 is the output of described ON time deviation processing module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320020341 CN203057108U (en) | 2013-01-15 | 2013-01-15 | Power tube driving device with driving pulse regulation function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320020341 CN203057108U (en) | 2013-01-15 | 2013-01-15 | Power tube driving device with driving pulse regulation function |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203057108U true CN203057108U (en) | 2013-07-10 |
Family
ID=48740023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320020341 Withdrawn - After Issue CN203057108U (en) | 2013-01-15 | 2013-01-15 | Power tube driving device with driving pulse regulation function |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203057108U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103107799A (en) * | 2013-01-15 | 2013-05-15 | 深圳市明微电子股份有限公司 | Power tube driving device with drive pulse regulating function |
| CN105680707A (en) * | 2016-03-30 | 2016-06-15 | 无锡市芯茂微电子有限公司 | Synchronous rectification chip protection method of isolated type synchronous rectification control circuit and synchronous rectification chip |
-
2013
- 2013-01-15 CN CN 201320020341 patent/CN203057108U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103107799A (en) * | 2013-01-15 | 2013-05-15 | 深圳市明微电子股份有限公司 | Power tube driving device with drive pulse regulating function |
| CN103107799B (en) * | 2013-01-15 | 2015-10-21 | 深圳市明微电子股份有限公司 | A kind of power tube drive unit possessing driving pulse regulatory function |
| CN105680707A (en) * | 2016-03-30 | 2016-06-15 | 无锡市芯茂微电子有限公司 | Synchronous rectification chip protection method of isolated type synchronous rectification control circuit and synchronous rectification chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103107799B (en) | A kind of power tube drive unit possessing driving pulse regulatory function | |
| CN102879611B (en) | Circuit for detecting breakage or short circuiting of speed sensor circuit | |
| CN203057108U (en) | Power tube driving device with driving pulse regulation function | |
| CN105119233B (en) | A kind of protection circuit | |
| CN104849609A (en) | Device for detecting power battery voltage sampling line sequence of electric car | |
| CN105552851A (en) | PWM pulse blocking method and device for three-level inverter | |
| CN101958638A (en) | Novel method for implementing current interruption protection of direct-current converter valve thyristor | |
| CN103207339A (en) | Method and device for determining over-current of inverter | |
| CN202190442U (en) | Chopping dimming device | |
| CN204349439U (en) | The anti-straight-through drive circuit of magnetic latching relay of a kind of Intelligent capacitor | |
| CN102305642A (en) | Detection circuit and detection method for output signal of pressure sensor | |
| CN104111689B (en) | A kind of Intelligent Power Module | |
| CN103475206B (en) | A kind of start-up circuit of PWM chip of wide-voltage auxiliary power source | |
| CN202633927U (en) | Surge current inhibition circuit and LED (light-emitting diode) dimming system thereof | |
| CN202495757U (en) | Impulse current limiting circuit and corresponding chopping dimming system thereof | |
| CN106655803A (en) | Intelligent half-bridge sine wave voltage conversion circuit based on Vienna PFC | |
| CN106208818B (en) | A kind of mutual exclusion driving circuit of motor H bridge | |
| CN102611090B (en) | Capacitor pulse electric discharge device, capacitor fling-cut switch | |
| CN105634382B (en) | A kind of load motor protection circuit, fan and air-conditioning | |
| CN202978239U (en) | IGBT straight-through overcurrent protection circuit | |
| CN204088194U (en) | A kind of Safety output control circuit | |
| CN204044945U (en) | The detection that a kind of welding wire is finished and warning device | |
| CN204166321U (en) | For the input circuit pulse-detecting circuit of safety feature | |
| CN203504137U (en) | Induction cooker with surge protection | |
| CN205105181U (en) | Circuit system for PWM pulse shaping |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20130710 Effective date of abandoning: 20151021 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |