CN104111689B - A kind of Intelligent Power Module - Google Patents

A kind of Intelligent Power Module Download PDF

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Publication number
CN104111689B
CN104111689B CN201310370916.1A CN201310370916A CN104111689B CN 104111689 B CN104111689 B CN 104111689B CN 201310370916 A CN201310370916 A CN 201310370916A CN 104111689 B CN104111689 B CN 104111689B
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China
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input
gate
phase
output terminal
brachium pontis
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CN201310370916.1A
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Chinese (zh)
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CN104111689A (en
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冯宇翔
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广东美的制冷设备有限公司
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Abstract

The invention belongs to power drive control field, provide a kind of Intelligent Power Module.The present invention comprises high pressure DMOS pipe DM1 by adopting in Intelligent Power Module, high pressure DMOS pipe DM2, high pressure DMOS pipe DM3, U phase adjusting module, V phase adjusting module, W phase adjusting module, U phase voltage sampling module, the HVIC chip of V phase voltage sampling module and W phase voltage sampling module, HVIC chip can be made when brachium pontis signal end is low level (low level time is greater than high level time) on three of HVIC chip to charge to filter capacitor and the external storage capacitor of Intelligent Power Module, duration of charging is increased considerably, thus Intelligent Power Module is correspondingly increased the duration of charging of filter capacitor and storage capacitor when starting, and reduce the thermal value of IGBT pipe when electrifying startup, extend the life-span of IGBT pipe and the life-span of Intelligent Power Module, improve the safety in utilization of Intelligent Power Module.

Description

A kind of Intelligent Power Module

Technical field

The invention belongs to power drive control field, particularly relate to a kind of Intelligent Power Module.

Background technology

Intelligent Power Module (IPM, Intelligent Power Module) is a kind of power drive series products in conjunction with Power Electronic Technique and integrated circuit technique.Intelligent Power Module integrates device for power switching and high-voltage driving circuit, and is built-in with superpotential, excess current and the failure detector circuit such as overheated.The state detection signal of system by receiving the control signal of MCU and driving subsequent conditioning circuit work, is fed back to MCU again by Intelligent Power Module on the one hand on the other hand.Compared with traditional discrete scheme, Intelligent Power Module wins increasing market with its advantage such as high integration, high reliability, being particularly suitable for the frequency converter of drive motor and various inverter, is the desired power level electron device for frequency control, metallurgical machinery, electric propulsion, servo driving and frequency-conversion domestic electric appliances.

As shown in Figure 1, it is electric for exporting U phase electricity, V phase electricity and W phase for the circuit structure of existing Intelligent Power Module.Wherein:

HVIC (High Voltage Integrated Circuit, high voltage integrated circuit) the power end VCC of chip 101 to power anode VDD as the low-pressure area of Intelligent Power Module, the voltage at VDD place is generally 15V, HVIC chip 101 first on brachium pontis signal end HIN1, second on brachium pontis signal end HIN2 and the 3rd brachium pontis signal end HIN3 respectively as brachium pontis input end WHIN in brachium pontis input end VHIN in brachium pontis input end UHIN, V phase in the U phase of Intelligent Power Module and W phase, first time brachium pontis signal end LIN1, second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3 of HVIC chip 101 is respectively as brachium pontis input end VLIN and the lower brachium pontis input end WLIN of W phase under lower brachium pontis input end ULIN, V phase of U phase of Intelligent Power Module, at this, Intelligent Power Module first on brachium pontis signal end HIN1, second on brachium pontis signal end HIN2, the 3rd voltage range of the input signal of brachium pontis signal end HIN3, first time brachium pontis signal end LIN1, second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3 be 0 ~ 5V, the earth terminal GND of HVIC chip 101 to power negative terminal COM as the low-pressure area of Intelligent Power Module, first power supply anode VB1 of HVIC chip 101 to power anode UVB as the U phase higher-pressure region of Intelligent Power Module, first higher-pressure region control end HO1 of HVIC chip 101 is connected with the grid of IGBT pipe Q1, first power supply negative terminal VS1 end of HVIC chip 101 and the source electrode of described IGBT pipe Q1, the anode of fast recovery diode D1, the drain electrode of IGBT pipe D4 and the negative electrode of fast recovery diode D4 are connected, and to power negative terminal UVS as the U phase higher-pressure region of Intelligent Power Module, the U phase higher-pressure region that filter capacitor C1 the is connected to Intelligent Power Module anode UVB that powers powers between negative terminal UVS with U phase higher-pressure region, second power supply anode VB2 of HVIC chip 101 to power anode VVB as the V phase higher-pressure region of Intelligent Power Module, second higher-pressure region control end HO2 of HVIC chip 101 is connected with the grid of IGBT pipe Q2, the source electrode of the second power supply negative terminal VS2 and IGBT pipe Q2 of HVIC chip 101, the anode of fast recovery diode D2, the drain electrode of IGBT pipe Q5 and the negative electrode of fast recovery diode D5 are connected, and to power negative terminal VVS as the V phase higher-pressure region of Intelligent Power Module, the V phase higher-pressure region that filter capacitor C2 the is connected to Intelligent Power Module anode VVB that powers powers between negative terminal VVS with V phase higher-pressure region, 3rd power supply anode VB3 of HVIC chip 101 to power anode WVB as the W phase higher-pressure region of Intelligent Power Module, the third high nip control end HO3 of HVIC chip 101 is connected with the grid of IGBT pipe Q3, the source electrode of the 3rd power supply negative terminal VS3 and IGBT pipe Q3 of HVIC chip 101, the anode of fast recovery diode D3, the drain electrode of IGBT pipe Q6 and the negative electrode of fast recovery diode D6 are connected, and to power negative terminal WVS as the W phase higher-pressure region of Intelligent Power Module, the W phase higher-pressure region that filter capacitor C3 the is connected to Intelligent Power Module anode WVB that powers powers between negative terminal WVS with W phase higher-pressure region, first low-pressure area control end LO1, the second low-pressure area control end LO2 of HVIC chip 101 and the 3rd low-pressure area control end LO3 are connected with the grid of the grid of described IGBT pipe Q4, the grid of IGBT pipe Q5 and IGBT pipe Q6 respectively, the source electrode of IGBT pipe Q4 is connected with the anode of fast recovery diode D4, and as the U phase low reference voltage end UN of Intelligent Power Module, the source electrode of IGBT pipe Q5 is connected with the anode of fast recovery diode D5, and as the V phase low reference voltage end VN of Intelligent Power Module, the source electrode of IGBT pipe Q6 is connected with the anode of fast recovery diode D6, and as the W phase low reference voltage end WN of Intelligent Power Module, the drain electrode of the drain electrode of IGBT pipe Q1, the negative electrode of fast recovery diode D1, IGBT pipe Q2, the negative electrode of fast recovery diode D2, the collector of IGBT pipe Q3, the negative electrode of fast recovery diode D3 connect altogether and as the high voltage input end P of Intelligent Power Module, P generally accesses 300V voltage.

The effect of HVIC chip 101 is that the logical signal of 0 ~ 5V HIN1, HIN2, HIN3, LIN1, LIN2, LIN3 received passes to HO1, HO2, HO3, LO1, LO2, LO3 respectively, the logical signal of what wherein HO1, HO2 and HO3 exported is VS ~ VS+15V, LO1, LO2, LO3 are the logical signals of 0 ~ 15V; The input signal of same phase can not be high level simultaneously, namely the input signal of brachium pontis signal end HIN1 and first time brachium pontis signal end LIN1 can not be high level simultaneously on first, on second, the input signal of brachium pontis signal end HIN2 and second time brachium pontis signal end LIN2 can not be high level simultaneously, and on the 3rd, the input signal of brachium pontis signal end HIN3 and the 3rd time brachium pontis signal end LIN3 can not be high level simultaneously.

HVIC chip 101 inside includes boostrap circuit, and the structure of this boostrap circuit is as follows:

The source electrode of high pressure DMOS pipe DM1, the source electrode of high pressure DMOS pipe DM2 and the source electrode of high pressure DMOS pipe DM3 are connected to the power end VCC of HVIC chip 101 altogether, the substrate of high pressure DMOS pipe DM1, the substrate of high pressure DMOS pipe DM2 and the equal ground connection of substrate of high pressure DMOS pipe DM3, the drain electrode of high pressure DMOS pipe DM1, the drain electrode of high pressure DMOS pipe DM2 and the drain electrode of high pressure DMOS pipe DM3 connect the first power supply anode VB1 of HVIC chip 101 respectively, second power supply anode VB2 and the 3rd power supply anode VB3, the input end of U phase control circuit 1011, the input end of V phase control circuit 1012 and the input end of W phase control circuit 1013 connect first time brachium pontis signal end LIN1 of HVIC chip 101 respectively, second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3, the output terminal of U phase control circuit 1011, the output terminal of V phase control circuit 1012 and the output terminal of W phase control circuit 1013 respectively with the grid of high pressure DMOS pipe DM1, the grid of high pressure DMOS pipe DM2 and the grid of high pressure DMOS pipe DM3 are connected.

When practical application, as shown in Figure 2, electric capacity C4 is connected between UVB and UVS the mode of connection of Intelligent Power Module, and electric capacity C5 is connected between VVB and VVS, and electric capacity C6 is connected between WVB and WVS; UN, VN, WN are connected to the first end of resistance R1 altogether, and second end of resistance R1 and COM are connected to ground altogether.Below the principle of work that Intelligent Power Module is described for U phase:

When LIN1 is high level, HIN1 is then necessary for low level, now, LO1 and HO1 exports high level and low level respectively, thus makes the voltage at VS1 place be about 0V, when LIN1 is high level, U phase control circuit 1011 exports high level and makes high pressure DMOS pipe DM1 conducting, VCC charge to electric capacity C1 and electric capacity C4 by high pressure DMOS pipe DM1, when time long enough or the dump energy before making electric capacity C1 and electric capacity C4 charging abundant time, VB1 to the voltage of VS1 close to 15V.

When LIN1 is low level, HIN1 is low level or high level.When HIN1 is low level, the equal output low level of LO1 and HO1, now U phase higher-pressure region does not work and no-output; And when HIN1 is high level, LO1 and HO1 output low level and high level respectively, thus make the voltage at VS1 place be about 300V.When LIN1 is low level, U phase control circuit 1011 output low level makes high pressure DMOS pipe DM1 end, the voltage of VB1 is raised to about 315V, the work of U phase higher-pressure region is maintained by the electricity of electric capacity C1 and electric capacity C4, if HIN1 is the duration of high level, electricity that is enough short or electric capacity C1 and electric capacity C4 storage is abundant, in the course of work of U phase higher-pressure region, VB1 can remain on more than 14V to the voltage of VS1.In actual application, after the electric capacity C4 that Intelligent Power Module is external fully charges, VB1 can remain on to maintain the normal work of Intelligent Power Module between 14V ~ 15V the voltage of VS1, but when just powering on, VB1 to the waveform of the voltage VB1-VS1 of VS1 often as shown in Figure 3.Initial quantity of electricity due to electric capacity C1 and electric capacity C4 is 0, so when just powering on, electric capacity C1 and electric capacity C4 will be charged, when the voltage LIN1-GND of LIN1 to GND is high level, U phase control circuit 1011 controls high pressure DMOS pipe DM1 conducting, so that VCC charges to electric capacity C1 and electric capacity C4, electric capacity due to electric capacity C4 is general larger and can reach 0.5 ~ 1mF, so, according to existing charging principle, electric capacity C1 and electric capacity C4 only could be charged when LIN1 is high level, then after the power-up LIN1 input first three input signal time, voltage V required when VB1 stablizes the saturation voltage drop that the voltage of VS1 does not often reach IGBT pipe Q1 iGBT, and when HO1 exports high level, HO1 is consistent to the voltage difference of VS1 with the voltage difference of VB1 to VS1, therefore, when just powering on, the voltage of HO1 to VS1 does not reach V iGBT, then IGBT pipe Q1 cannot stablize conducting.According to the grid-emitter voltage V of IGBT pipe gEwith its saturation voltage drop V cESATrelation property, work as V gE<V iGBTtime, the saturation voltage drop V of IGBT pipe cESATsharply can rise, and then cause the power consumption during conducting of IGBT pipe sharply to increase.

Therefore, for above-mentioned existing Intelligent Power Module, when just powering on, the saturation voltage drop of IGBT pipe can be very large, causes IGBT pipe sharply to generate heat because power consumption suddenly increases, for some special operation condition, IGBT pipe even can be caused to explode because of heat accumulation, and for conventional operating mode, sharply generating heat of each powered on moment also can cause shorten the serviceable life of IGBT pipe, and then shorten the serviceable life of Intelligent Power Module.

In sum, the saturation voltage drop of IGBT pipe excessive and sharply heating and reduction of service life when existing Intelligent Power Module exists because powering on, the problem even can damaged because the blast of IGBT pipe.

Summary of the invention

The invention provides a kind of Intelligent Power Module, be intended to solve existing for existing Intelligent Power Module because powering on time IGBT pipe saturation voltage drop excessive and sharply heating and reduction of service life, the problem even can damaged because the blast of IGBT pipe.

The present invention realizes like this, a kind of Intelligent Power Module, comprises HVIC chip, IGBT pipe Q1, fast recovery diode D1, IGBT pipe Q2, fast recovery diode D2, IGBT pipe Q3, fast recovery diode D3, IGBT pipe Q4, fast recovery diode D4, IGBT pipe Q5, fast recovery diode D5, IGBT pipe Q6, fast recovery diode D6, filter capacitor C1, filter capacitor C2 and filter capacitor C3, the power end of described HVIC chip is that the low-pressure area of described Intelligent Power Module is powered anode, described HVIC chip first on brachium pontis signal end, brachium pontis input end in the U phase that on second, on brachium pontis signal end and the 3rd, brachium pontis signal end is respectively described Intelligent Power Module, brachium pontis input end in brachium pontis input end and W phase in V phase, first time brachium pontis signal end of described HVIC chip, second time brachium pontis signal end and the 3rd time brachium pontis signal end are respectively the lower brachium pontis input end of U phase of described Intelligent Power Module, the lower brachium pontis input end of V phase and the lower brachium pontis input end of W phase, the earth terminal of described HVIC chip to be powered negative terminal as the low-pressure area of described Intelligent Power Module, first power supply anode of described HVIC chip to be powered anode as the U phase higher-pressure region of described Intelligent Power Module, first higher-pressure region control end of described HVIC chip is connected with the grid of described IGBT pipe Q1, first power supply negative terminal of described HVIC chip and the source electrode of described IGBT pipe Q1, the anode of described fast recovery diode D1, the drain electrode of described IGBT pipe D4 and the negative electrode of the described fast recovery diode D4 U phase higher-pressure region connect altogether as described Intelligent Power Module powers negative terminal, the U phase higher-pressure region that described filter capacitor C1 is connected to described Intelligent Power Module anode of powering is powered between negative terminal with U phase higher-pressure region, second power supply anode of described HVIC chip to be powered anode as the V phase higher-pressure region of described Intelligent Power Module, second higher-pressure region control end of described HVIC chip is connected with the grid of described IGBT pipe Q2, second power supply negative terminal of described HVIC chip and the source electrode of described IGBT pipe Q2, the anode of described fast recovery diode D2, the drain electrode of described IGBT pipe Q5 and the negative electrode of the described fast recovery diode D5 V phase higher-pressure region connect altogether as Intelligent Power Module powers negative terminal, the V phase higher-pressure region that described filter capacitor C2 is connected to described Intelligent Power Module anode of powering is powered between negative terminal with V phase higher-pressure region, 3rd power supply anode of described HVIC chip to be powered anode as the W phase higher-pressure region of described Intelligent Power Module, the third high nip control end of described HVIC chip is connected with the grid of described IGBT pipe Q3, 3rd power supply negative terminal of described HVIC chip and the source electrode of described IGBT pipe Q3, the anode of described fast recovery diode D3, the drain electrode of described IGBT pipe Q6 and the negative electrode of the described fast recovery diode D6 W phase higher-pressure region connect altogether as described Intelligent Power Module powers negative terminal, the W phase higher-pressure region that described filter capacitor C3 is connected to Intelligent Power Module anode of powering is powered between negative terminal with W phase higher-pressure region, first low-pressure area control end of described HVIC chip, the second low-pressure area control end and the 3rd low-pressure area control end are connected with the grid of the grid of described IGBT pipe Q4, the grid of described IGBT pipe Q5 and described IGBT pipe Q6 respectively, the drain electrode of described IGBT pipe Q1 and the negative electrode of described fast recovery diode D1, the drain electrode of described IGBT pipe Q2, the negative electrode of described fast recovery diode D2, the drain electrode of described IGBT pipe Q3 and the negative electrode of described fast recovery diode D3 connect the high voltage input end of formed common contact as described Intelligent Power Module altogether, source electrode and the anode of described fast recovery diode D4 of described IGBT pipe Q4 connect the U phase low reference voltage end of formed common contact as described Intelligent Power Module altogether, source electrode and the anode of described fast recovery diode D5 of described IGBT pipe Q5 connect the V phase low reference voltage end of formed common contact as described Intelligent Power Module altogether, source electrode and the anode of described fast recovery diode D6 of described IGBT pipe Q6 connect the W phase low reference voltage end of formed common contact as described Intelligent Power Module altogether,

Described HVIC chip comprises a boostrap circuit, and described boostrap circuit comprises:

High pressure DMOS pipe DM1, high pressure DMOS pipe DM2, high pressure DMOS pipe DM3, U phase adjusting module, V phase adjusting module, W phase adjusting module, U phase voltage sampling module, V phase voltage sampling module and W phase voltage sampling module;

The source electrode of the source electrode of described high pressure DMOS pipe DM1 and the source electrode of described high pressure DMOS pipe DM2 and described high pressure DMOS pipe DM3 is connected to the power end of described HVIC chip altogether, the drain electrode of described high pressure DMOS pipe DM1, the drain electrode of described high pressure DMOS pipe DM2 and the drain electrode of described high pressure DMOS pipe DM3 connect the first power supply anode of described HVIC chip respectively, second power supply anode and the 3rd power supply anode, the substrate of described high pressure DMOS pipe DM1, the substrate of described high pressure DMOS pipe DM2 and the equal ground connection of substrate of described high pressure DMOS pipe DM3, the first input end of described U phase adjusting module and the control end of described U phase voltage sampling module are connected to first time brachium pontis signal end of described HVIC chip altogether, input end and the output terminal of described U phase voltage sampling module are connected the drain electrode of described high pressure DMOS pipe DM1 and the second input end of described U phase adjusting module respectively, 3rd input end and the output terminal of described U phase adjusting module are connected the first power supply negative terminal of described HVIC chip and the grid of described high pressure DMOS pipe DM1 respectively, the first input end of described V phase adjusting module and the control end of described V phase voltage sampling module are connected to second time brachium pontis signal end of described HVIC chip altogether, input end and the output terminal of described V phase voltage sampling module are connected the drain electrode of described high pressure DMOS pipe DM2 and the second input end of described V phase adjusting module respectively, 3rd input end and the output terminal of described V phase adjusting module are connected the second power supply negative terminal of described HVIC chip and the grid of described high pressure DMOS pipe DM2 respectively, the first input end of described W phase adjusting module and the control end of described W phase voltage sampling module are connected to the 3rd time brachium pontis signal end of described HVIC chip altogether, input end and the output terminal of described W phase voltage sampling module are connected the drain electrode of described high pressure DMOS pipe DM3 and the second input end of described W phase adjusting module respectively, 3rd input end and the output terminal of described W phase adjusting module are connected the 3rd power supply negative terminal of described HVIC chip and the grid of described high pressure DMOS pipe DM3 respectively,

When first time brachium pontis signal end of described HVIC chip, second time brachium pontis signal end and the 3rd time brachium pontis signal end are high level, described HVIC chip first on brachium pontis signal end, second on brachium pontis signal end and the 3rd brachium pontis signal end be low level; When first time brachium pontis signal end of described HVIC chip, second time brachium pontis signal end and the 3rd time brachium pontis signal end are low level, described HVIC chip first on brachium pontis signal end, second on brachium pontis signal end and the 3rd brachium pontis signal end be high level or low level;

When on first of described HVIC chip, brachium pontis signal end is low level, the level that described U phase adjusting module inputs according to first time brachium pontis signal end of described HVIC chip, the voltage of the output voltage of described U phase voltage sampling module and the first power supply negative terminal of described HVIC chip exports high level and drives described high pressure DMOS pipe DM1 conducting, and the voltage that inputs of the power end of described HVIC chip is charged to filter capacitor C1 and the U phase higher-pressure region that the is connected to described Intelligent Power Module storage capacitor that anode and U phase higher-pressure region power between negative terminal of powering by described high pressure DMOS pipe DM1,

When on second of described HVIC chip, brachium pontis signal end is low level, the level that described V phase adjusting module inputs according to second time brachium pontis signal end of described HVIC chip, the voltage of the output voltage of described V phase voltage sampling module and the second power supply negative terminal of described HVIC chip exports high level and drives described high pressure DMOS pipe DM2 conducting, and the voltage that inputs of the power end of described HVIC chip is charged to filter capacitor C2 and the V phase higher-pressure region that the is connected to described Intelligent Power Module storage capacitor that anode and V phase higher-pressure region power between negative terminal of powering by described high pressure DMOS pipe DM2,

When on the 3rd of described HVIC chip the, brachium pontis signal end is low level, described W phase adjusting module is according to the level that the 3rd of described HVIC chip the time brachium pontis signal end inputs, the voltage of the output voltage of described W phase voltage sampling module and the 3rd power supply negative terminal of described HVIC chip exports high level and drives described high pressure DMOS pipe DM3 conducting, and the voltage that inputs of the power end of described HVIC chip is charged to filter capacitor C3 and the W phase higher-pressure region that the is connected to described Intelligent Power Module storage capacitor that anode and W phase higher-pressure region power between negative terminal of powering by described high pressure DMOS pipe DM3.

In the present invention, high pressure DMOS pipe DM1 is comprised by adopting in Intelligent Power Module, high pressure DMOS pipe DM2, high pressure DMOS pipe DM3, U phase adjusting module, V phase adjusting module, W phase adjusting module, U phase voltage sampling module, the HVIC chip of V phase voltage sampling module and W phase voltage sampling module, brachium pontis signal end on first of HVIC chip, the first power supply anode of HVIC chip can be made when brachium pontis signal end is low level (low level time is greater than high level time) on brachium pontis signal end and the 3rd on second, second power supply anode and the 3rd power supply anode charge to filter capacitor and the external storage capacitor of Intelligent Power Module, duration of charging is significantly increased, thus Intelligent Power Module is correspondingly increased the duration of charging of filter capacitor and storage capacitor when starting, and and then reduce the thermal value of IGBT pipe when electrifying startup works, extend the serviceable life of IGBT pipe and the serviceable life of Intelligent Power Module, improve the safety in utilization of Intelligent Power Module, solve existing for existing Intelligent Power Module because powering on time IGBT pipe saturation voltage drop excessive and sharply heating and reduction of service life, the problem even can damaged because of the blast of IGBT pipe.

Accompanying drawing explanation

Fig. 1 is the structural representation of existing Intelligent Power Module;

Fig. 2 is Intelligent Power Module schematic diagram in actual applications;

Fig. 3 is each waveform voltage signal figure involved in the course of work of existing Intelligent Power Module after electrifying startup;

Fig. 4 is the structural representation of the Intelligent Power Module that the embodiment of the present invention provides;

Fig. 5 is the exemplary circuit structural drawing of the U phase adjusting module included by HVIC chip in the Intelligent Power Module that provides of the embodiment of the present invention and U phase voltage sampling module;

Fig. 6 is the exemplary circuit structural drawing of the V phase adjusting module included by HVIC chip in the Intelligent Power Module that provides of the embodiment of the present invention and V phase voltage sampling module;

Fig. 7 is the exemplary circuit structural drawing of the W phase adjusting module included by HVIC chip in the Intelligent Power Module that provides of the embodiment of the present invention and W phase voltage sampling module;

Fig. 8 is the involved in the course of the work level signal oscillogram of the U phase adjusting module included by HVIC chip in the Intelligent Power Module that provides of the embodiment of the present invention.

Embodiment

In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.

The embodiment of the present invention comprises high pressure DMOS pipe DM1 by adopting in Intelligent Power Module, high pressure DMOS pipe DM2, high pressure DMOS pipe DM3, U phase adjusting module, V phase adjusting module, W phase adjusting module, U phase voltage sampling module, the HVIC chip of V phase voltage sampling module and W phase voltage sampling module, Intelligent Power Module is correspondingly increased the duration of charging of filter capacitor and storage capacitor when starting, and and then reduce the thermal value of IGBT pipe when electrifying startup works, extend the serviceable life of IGBT pipe and the serviceable life of Intelligent Power Module, improve the safety in utilization of Intelligent Power Module.

Fig. 4 shows the structure of the Intelligent Power Module that the embodiment of the present invention provides, and for convenience of explanation, illustrate only part related to the present invention, details are as follows:

Intelligent Power Module comprises HVIC chip 100, IGBT pipe Q1, fast recovery diode D1, IGBT pipe Q2, fast recovery diode D2, IGBT pipe Q3, fast recovery diode D3, IGBT pipe Q4, fast recovery diode D4, IGBT pipe Q5, fast recovery diode D5, IGBT pipe Q6, fast recovery diode D6, filter capacitor C1, filter capacitor C2 and filter capacitor C3.

The power end VCC of HVIC chip 100 is that the low-pressure area of Intelligent Power Module 100 is powered anode VDD, HVIC chip 100 first on brachium pontis signal end HIN1, brachium pontis input end UHIN in the U phase that on second, on brachium pontis signal end HIN2 and the 3rd, brachium pontis signal end HIN3 is respectively Intelligent Power Module, brachium pontis input end WHIN in brachium pontis input end VHIN and W phase in V phase, first time brachium pontis signal end LIN1 of HVIC chip 100, second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3 is respectively the U phase brachium pontis input end ULIN down of Intelligent Power Module, the lower brachium pontis input end VLIN of V phase and the lower brachium pontis input end WLIN of W phase, the earth terminal GND of HVIC chip 100 to power negative terminal COM as the low-pressure area of Intelligent Power Module, first power supply anode VB1 of HVIC chip 100 to power anode UVB as the U phase higher-pressure region of Intelligent Power Module, first higher-pressure region control end HO1 of HVIC chip 100 is connected with the grid of IGBT pipe Q1, the source electrode of the first power supply negative terminal VS1 and IGBT pipe Q1 of HVIC chip 100, the anode of fast recovery diode D1, the drain electrode of IGBT pipe D4 and the negative electrode of the fast recovery diode D4 U phase higher-pressure region connect altogether as Intelligent Power Module powers negative terminal UVS, the U phase higher-pressure region that filter capacitor C1 the is connected to Intelligent Power Module anode UVB that powers powers between negative terminal UVS with U phase higher-pressure region, second power supply anode VB2 of HVIC chip 100 to power anode VVB as the V phase higher-pressure region of Intelligent Power Module, second higher-pressure region control end HO2 of HVIC chip 100 is connected with the grid of IGBT pipe Q2, the source electrode of the second power supply negative terminal VS2 and IGBT pipe Q2 of HVIC chip 100, the anode of fast recovery diode D2, the drain electrode of IGBT pipe Q5 and the negative electrode of the fast recovery diode D5 V phase higher-pressure region connect altogether as Intelligent Power Module powers negative terminal VVS, the V phase higher-pressure region that filter capacitor C2 the is connected to Intelligent Power Module anode VVB that powers powers between negative terminal VVS with V phase higher-pressure region, 3rd power supply anode VB3 of HVIC chip 100 to power anode WVB as the W phase higher-pressure region of Intelligent Power Module, the third high nip control end HO3 of HVIC chip 100 is connected with the grid of IGBT pipe Q3, the source electrode of the 3rd power supply negative terminal VS3 and IGBT pipe Q3 of HVIC chip 100, the anode of fast recovery diode D3, the drain electrode of IGBT pipe Q6 and the negative electrode of the fast recovery diode D6 W phase higher-pressure region connect altogether as Intelligent Power Module powers negative terminal WVS, the W phase higher-pressure region that filter capacitor C3 the is connected to Intelligent Power Module anode WVB that powers powers between negative terminal WVS with W phase higher-pressure region, first low-pressure area control end LO1, the second low-pressure area control end LO2 of HVIC chip 100 and the 3rd low-pressure area control end LO3 are connected with the grid of the grid of IGBT pipe Q4, the grid of IGBT pipe Q5 and IGBT pipe Q6 respectively, the drain electrode of IGBT pipe Q1 and the negative electrode of fast recovery diode D1, the drain electrode of IGBT pipe Q2, the negative electrode of fast recovery diode D2, the drain electrode of IGBT pipe Q3 and the negative electrode of fast recovery diode D3 meet the high voltage input end P of formed common contact as Intelligent Power Module altogether, the source electrode of IGBT pipe Q4 and the anode of fast recovery diode D4 meet the U phase low reference voltage end UN of formed common contact as Intelligent Power Module altogether, the source electrode of IGBT pipe Q5 and the anode of fast recovery diode D5 meet the V phase low reference voltage end VN of formed common contact as Intelligent Power Module altogether, the source electrode of IGBT pipe Q6 and the anode of fast recovery diode D6 meet the W phase low reference voltage end WN of formed common contact as Intelligent Power Module altogether.

HVIC chip 100 comprises a boostrap circuit 10, and this boostrap circuit 10 comprises high pressure DMOS pipe DM1, high pressure DMOS pipe DM2, high pressure DMOS pipe DM3, U phase adjusting module 101, V phase adjusting module 102, W phase adjusting module 103, U phase voltage sampling module 104, V phase voltage sampling module 105 and W phase voltage sampling module 106.

The source electrode of the source electrode of high pressure DMOS pipe DM1 and the source electrode of high pressure DMOS pipe DM2 and high pressure DMOS pipe DM3 is connected to the power end VCC of HVIC chip 100 altogether, the drain electrode of high pressure DMOS pipe DM1, the drain electrode of high pressure DMOS pipe DM2 and the drain electrode of high pressure DMOS pipe DM3 connect the first power supply anode VB1 of HVIC chip 100 respectively, second power supply anode VB2 and the 3rd power supply anode VB3, the substrate of high pressure DMOS pipe DM1, the substrate of high pressure DMOS pipe DM2 and the equal ground connection of substrate of high pressure DMOS pipe DM3, the first input end of U phase adjusting module 101 and the control end of U phase voltage sampling module 104 are connected to first time brachium pontis signal end LIN1 of HVIC chip 100 altogether, input end and the output terminal of U phase voltage sampling module 104 are connected the drain electrode of high pressure DMOS pipe DM1 and the second input end of U phase adjusting module 101 respectively, 3rd input end and the output terminal of U phase adjusting module 101 are connected the first power supply negative terminal of HVIC chip 100 and the grid of high pressure DMOS pipe DM1 respectively, the first input end of V phase adjusting module 102 and the control end of V phase voltage sampling module 105 are connected to second time brachium pontis signal end LIN2 of HVIC chip 100 altogether, input end and the output terminal of V phase voltage sampling module 105 are connected the drain electrode of high pressure DMOS pipe DM2 and the second input end of V phase adjusting module 102 respectively, 3rd input end and the output terminal of V phase adjusting module 102 are connected the second power supply negative terminal of HVIC chip 100 and the grid of high pressure DMOS pipe DM2 respectively, the first input end of W phase adjusting module 103 and the control end of W phase voltage sampling module 106 are connected to the 3rd time brachium pontis signal end LIN3 of HVIC chip 100 altogether, input end and the output terminal of W phase voltage sampling module 106 are connected the drain electrode of high pressure DMOS pipe DM3 and the second input end of W phase adjusting module 103 respectively, 3rd input end and the output terminal of W phase adjusting module 103 are connected the grid of the 3rd power supply negative terminal VS1 and high pressure DMOS pipe DM3 of HVIC chip 100 respectively.

Because the input signal of brachium pontis signal end HIN1 and first time brachium pontis signal end LIN1 can not be high level on first of HVIC chip 100 simultaneously, HVIC chip 100 second on the input signal of brachium pontis signal end HIN2 and second time brachium pontis signal end LIN2 can not be high level simultaneously, HVIC chip 100 the 3rd on the input signal of brachium pontis signal end HIN3 and the 3rd time brachium pontis signal end LIN3 can not be high level simultaneously, so, at first time brachium pontis signal end LIN1 of HVIC chip 100, when second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3 is respectively high level, HVIC chip 100 first on brachium pontis signal end HIN1, on second, on brachium pontis signal end HIN2 and the 3rd, brachium pontis signal end HIN3 is respectively low level, when first time brachium pontis signal end LIN1, second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3 of HVIC chip 100 is respectively low level, HVIC chip 100 first on brachium pontis signal end HIN1, second on brachium pontis signal end HIN2 and the 3rd brachium pontis signal end HIN3 be respectively high level or low level, it can thus be appreciated that, HVIC chip 100 first on brachium pontis signal end HIN1, second on brachium pontis signal end HIN2 and the 3rd brachium pontis signal end HIN3 be in the time that the low level time is greater than high level respectively.

When on first of HVIC chip 100, brachium pontis signal end HIN1 is low level, the level that U phase adjusting module 101 inputs according to first time brachium pontis signal end LIN1 of HVIC chip 100, the voltage of the output voltage of U phase voltage sampling module 104 and the first power supply negative terminal VS1 of HVIC chip 100 exports high level and drives high pressure DMOS pipe DM1 conducting, and the voltage that inputs of the power end VCC of HVIC chip 100 is charged to filter capacitor C1 and the U phase higher-pressure region that the is connected to Intelligent Power Module storage capacitor C4 (as shown in Figure 2) that anode UVB and U phase higher-pressure region power between negative terminal UVS that powers by high pressure DMOS pipe DM1.

When on second of HVIC chip 100, brachium pontis signal end HIN2 is low level, the level that V phase adjusting module 102 inputs according to second time brachium pontis signal end LIN2 of HVIC chip 100, the voltage of the output voltage of V phase voltage sampling module 105 and the second power supply negative terminal VS2 of HVIC chip 100 exports high level and drives high pressure DMOS pipe DM2 conducting, and the voltage that inputs of the power end VCC of HVIC chip 100 is charged to filter capacitor C2 and the V phase higher-pressure region that the is connected to Intelligent Power Module storage capacitor C5 (as shown in Figure 2) that anode VVB and V phase higher-pressure region power between negative terminal VVS that powers by high pressure DMOS pipe DM2.

When on the 3rd of HVIC chip 100 the, brachium pontis signal end HIN3 is low level, W phase adjusting module 103 is according to the level that the 3rd of HVIC chip 100 the time brachium pontis signal end LIN3 inputs, the voltage of the output voltage of W phase voltage sampling module 106 and the 3rd power supply negative terminal VS3 of HVIC chip 100 exports high level and drives high pressure DMOS pipe DM3 conducting, and the voltage that inputs of the power end of HVIC chip 100 is charged to filter capacitor C3 and the W phase higher-pressure region that the is connected to Intelligent Power Module storage capacitor C6 (as shown in Figure 2) that anode WVB and W phase higher-pressure region power between negative terminal WVS that powers by high pressure DMOS pipe DM3.

Wherein, for U phase adjusting module 101 (V phase adjusting module 102 and W phase adjusting module 103 are in like manner), when the first input end of U phase adjusting module 101 is low level, the output terminal of U phase adjusting module 101 can export high level, and receives the voltage of the first power supply negative terminal of HVIC chip 100 from its second input end simultaneously; When the first input end of U phase adjusting module 101 is high level, U phase adjusting module 101 according to its first input end upper be once high level time, its voltage received by the second input end and its first input end become the voltage correspondingly output level of its 3rd input end after low level, and this level is divided into following two kinds of situations:

(1) when the magnitude of voltage of the second input end is lower than preset voltage value V iTtime, concrete condition is as follows:

If the magnitude of voltage of the 3rd input end is lower than 15V-V iT, then U phase adjusting module 101 keeps high level output;

If the magnitude of voltage of the 3rd input end is higher than 15V-V iT, then U phase adjusting module 101 output low level.

(2) when the magnitude of voltage of the second input end is higher than preset voltage value V iTtime, U phase adjusting module 101 output low level.

As one embodiment of the invention, as shown in Figure 5, U phase adjusting module 101 comprises:

First Schmidt trigger U1, first or door U2, the first Sheffer stroke gate U3, the first not gate U4, the second not gate U5, the 3rd not gate U6, the first rest-set flip-flop RS1, the 4th not gate U7, the first comparer U8, the first voltage source V 1, the 5th not gate U9, the first rejection gate U10, the 6th not gate U11, the 7th not gate U12, electric capacity C7, the second rest-set flip-flop RS2, the second comparer U13, the 8th not gate U14, the second voltage source V 2 and high pressure DMOS pipe DM4;

The input end of the first Schmidt trigger U1 is the first input end of U phase adjusting module 101, the output terminal of the first Schmidt trigger U1 connects first or the first input end 1 of door U2 and the second input end S of the second rest-set flip-flop RS2 simultaneously, first or second input end 2 of door U2 connect the output terminal of the 4th not gate U7, first or output terminal 3 and the output terminal of the second not gate U5 of door U2 be connected first input end 1 and second input end 2 of the first Sheffer stroke gate U3 respectively, the output terminal 3 of the first Sheffer stroke gate U3 connects the input end of the first not gate U4, the output terminal of the first not gate U4 is the output terminal of U phase adjusting module 101, the in-phase input end of the first comparer U8 is the second input end of U phase adjusting module 101, anode and the negative terminal of the first voltage source V 1 are connected inverting input-and the ground of the first comparer U8 respectively, the output terminal of the first comparer U8 connects the input end of the 3rd not gate U6 simultaneously, the input end of the 5th not gate U9 and the input end of the 6th not gate U11, the output terminal of the 3rd not gate U6 connects the first input end R of the first rest-set flip-flop RS1, the output terminal of the 5th not gate U9 connects the first input end 1 of the first rejection gate U10, the output terminal of the 6th not gate U11 and the first end of electric capacity C7 are connected to the input end of the 7th not gate U12 altogether, the second end ground connection of electric capacity C7, the output terminal of the 7th not gate U12 connects second input end 2 of the first rejection gate U10, the output terminal 3 of the first rejection gate U10 connects the second input end S of the first rest-set flip-flop RS1, the output terminal Q of the first rest-set flip-flop RS1 connects the input end of the 4th not gate U7, the drain electrode of high pressure DMOS pipe DM4 is the 3rd input end of U phase adjusting module 101, the Substrate ground of high pressure DMOS pipe DM4, the source electrode of high pressure DMOS pipe DM4 connects the in-phase input end of the second comparer U13, the grid of high pressure DMOS pipe DM4 is connected with the output terminal Q of the second rest-set flip-flop RS2 and the input end of the 8th not gate U14 simultaneously, anode and the negative terminal of the second voltage source V 2 are connected inverting input and the ground of the second comparer U13 respectively, the output terminal of the second comparer U13 connects the first input end R of the second rest-set flip-flop RS2, the output terminal of the 8th not gate U14 connects the input end of the second not gate U5.Wherein, the anode voltage sum to negative terminal of anode to the voltage of negative terminal and the second voltage source V 2 of the first voltage source V 1 is 15V.

As one embodiment of the invention, as shown in Figure 6, V phase adjusting module 102 comprises:

Second Schmidt trigger U15, second or door U16, the second Sheffer stroke gate U17, the 9th not gate U18, the tenth not gate U19, the 11 not gate U20, the 3rd rest-set flip-flop RS3, the 12 not gate U21, the 3rd comparer U22, tertiary voltage source V3, the 13 not gate U23, the second rejection gate U24, the 14 not gate U25, the 15 not gate U26, electric capacity C8, the 4th rest-set flip-flop RS4, the 4th comparer U27, the 16 not gate U28, the 4th voltage source V 4 and high pressure DMOS pipe DM5;

The input end of the second Schmidt trigger U15 is the first input end of V phase adjusting module 102, the output terminal of the second Schmidt trigger U15 connects second or the first input end 1 of door U16 and the second input end S of the 4th rest-set flip-flop RS4 simultaneously, second or second input end 2 of door U16 connect the output terminal of the 12 not gate U21, second or output terminal 3 and the output terminal of the tenth not gate U19 of door U16 be connected first input end 1 and second input end 2 of the second Sheffer stroke gate U17 respectively, the output terminal 3 of the second Sheffer stroke gate U17 connects the input end of the 9th not gate U18, the output terminal of the 9th not gate U18 is the output terminal of V phase adjusting module 102, the in-phase input end of the 3rd comparer U22 is the second input end of V phase adjusting module 102, anode and the negative terminal of tertiary voltage source V3 are connected inverting input-and the ground of the 3rd comparer U22 respectively, the output terminal of the 3rd comparer U22 connects the input end of the 11 not gate U20 simultaneously, the input end of the 13 not gate U23 and the input end of the 14 not gate U25, the output terminal of the 11 not gate U20 connects the first input end R of the 3rd rest-set flip-flop RS3, the output terminal of the 13 not gate U23 connects the first input end 1 of the second rejection gate U24, the output terminal of the 14 not gate U25 and the first end of electric capacity C8 are connected to the input end of the 15 not gate U26 altogether, the second end ground connection of electric capacity C8, the output terminal of the 15 not gate U26 connects second input end 2 of the second rejection gate U24, the output terminal 3 of the second rejection gate U24 connects the second input end S of the 3rd rest-set flip-flop RS3, the output terminal Q of the 3rd rest-set flip-flop RS3 connects the input end of the 12 not gate U21, the drain electrode of high pressure DMOS pipe DM5 is the 3rd input end of V phase adjusting module 102, the Substrate ground of high pressure DMOS pipe DM5, the source electrode of high pressure DMOS pipe DM5 connects the in-phase input end of the 4th comparer U27, the grid of high pressure DMOS pipe DM5 is connected with the output terminal Q of the 4th rest-set flip-flop RS4 and the input end of the 16 not gate U28 simultaneously, anode and the negative terminal of the 4th voltage source V 4 are connected inverting input and the ground of the 4th comparer U27 respectively, the output terminal of the 4th comparer U27 connects the first input end R of the 4th rest-set flip-flop RS4, the output terminal of the 16 not gate U28 connects the input end of the tenth not gate U19.Wherein, the anode voltage sum to negative terminal of anode to the voltage of negative terminal and the 4th voltage source V 4 of tertiary voltage source V3 is 15V.

As one embodiment of the invention, as shown in Figure 7, W phase adjusting module 103 comprises:

3rd Schmidt trigger U29, 3rd or door U30, 3rd Sheffer stroke gate U31, 17 not gate U32, 18 not gate U33, 19 not gate U34, 5th rest-set flip-flop RS5, 20 not gate U35, 5th comparer U36, 5th voltage source V 5, 21 not gate U37, 3rd rejection gate U38, 22 not gate U39, 23 not gate U40, electric capacity C9, 6th rest-set flip-flop RS6, 6th comparer U41, 24 not gate U42, 6th voltage source V 6 and high pressure DMOS pipe DM6,

The input end of the 3rd Schmidt trigger U29 is the first input end of W phase adjusting module 103, the output terminal of the 3rd Schmidt trigger U29 connects the 3rd or the first input end 1 of door U30 and the second input end S of the 6th rest-set flip-flop RS6 simultaneously, 3rd or second input end 2 of door U30 connect the output terminal of the 20 not gate U35, 3rd or output terminal 3 and the output terminal of the 18 not gate U33 of door U30 be connected first input end 1 and second input end 2 of the 3rd Sheffer stroke gate U31 respectively, the output terminal 3 of the 3rd Sheffer stroke gate U31 connects the input end of the 17 not gate U32, the output terminal of the 17 not gate U32 is the output terminal of W phase adjusting module 103, the in-phase input end of the 5th comparer U36 is the second input end of W phase adjusting module 103, anode and the negative terminal of the 5th voltage source V 5 are connected inverting input and the ground of the 5th comparer U36 respectively, the output terminal of the 5th comparer U36 connects the input end of the 19 not gate U34 simultaneously, the input end of the 21 not gate U37 and the input end of the 22 not gate U39, the output terminal of the 19 not gate U34 connects the first input end R of the 5th rest-set flip-flop RS5, the output terminal of the 21 not gate U37 connects the first input end 1 of the 3rd rejection gate U38, the output terminal of the 22 not gate U39 and the first end of electric capacity C9 are connected to the input end of the 23 not gate U40 altogether, the second end ground connection of electric capacity C9, the output terminal of the 23 not gate U40 connects second input end 2 of the 3rd rejection gate U38, the output terminal 3 of the 3rd rejection gate U38 connects the second input end S of the 5th rest-set flip-flop RS5, the output terminal Q of the 5th rest-set flip-flop RS5 connects the input end of the 20 not gate U35, the drain electrode of high pressure DMOS pipe DM6 is the 3rd input end of W phase adjusting module 103, the Substrate ground of high pressure DMOS pipe DM6, the source electrode of high pressure DMOS pipe DM6 connects the in-phase input end of the 6th comparer U41, the grid of high pressure DMOS pipe DM6 is connected with the output terminal Q of the 6th rest-set flip-flop RS6 and the input end of the 24 not gate U42 simultaneously, anode and the negative terminal of the 6th voltage source V 6 are connected inverting input and the ground of the 6th comparer U41 respectively, the output terminal of the 6th comparer U41 connects the first input end R of the 6th rest-set flip-flop RS6, the output terminal of the 24 not gate U42 connects the input end of the 18 not gate U33.Wherein, the anode voltage sum to negative terminal of anode to the voltage of negative terminal and the 6th voltage source V 6 of the 5th voltage source V 5 is 15V.

As one embodiment of the invention, as shown in Figure 5, U phase voltage sampling module 104 comprises:

25 not gate U43, the 26 not gate U44 and high pressure DMOS pipe DM7;

The input end of the 25 not gate U43 is the control end of U phase voltage sampling module 104, the output terminal of the 25 not gate U43 connects the input end of the 26 not gate U44, the output terminal of the 26 not gate U44 connects the grid of high pressure DMOS pipe DM7, the drain electrode of high pressure DMOS pipe DM7 and source electrode are respectively input end and the output terminal of U phase voltage sampling module 104, the Substrate ground of high pressure DMOS pipe DM7.

As one embodiment of the invention, as shown in Figure 6, V phase voltage sampling module 105 comprises:

27 not gate U45, the 28 not gate U46 and high pressure DMOS pipe DM8;

The input end of the 27 not gate U45 is the control end of V phase voltage sampling module 105, the output terminal of the 27 not gate U45 connects the input end of the 28 not gate U46, the output terminal of the 28 not gate U46 connects the grid of high pressure DMOS pipe DM8, the drain electrode of high pressure DMOS pipe DM8 and source electrode are respectively input end and the output terminal of V phase voltage sampling module 105, the Substrate ground of high pressure DMOS pipe DM8.

As one embodiment of the invention, as shown in Figure 7, W phase voltage sampling module 106 comprises:

29 not gate U47, the 30 not gate U48 and high pressure DMOS pipe DM9;

The input end of the 29 not gate U47 is the control end of W phase voltage sampling module 106, the output terminal of the 29 not gate U47 connects the input end of the 30 not gate U48, the output terminal of the 30 not gate U48 connects the grid of high pressure DMOS pipe DM9, the drain electrode of high pressure DMOS pipe DM9 and source electrode are respectively input end and the output terminal of W phase voltage sampling module 106, the Substrate ground of high pressure DMOS pipe DM9.

Because U phase adjusting module 101 is identical with the inner structure of V phase adjusting module 102 and W phase adjusting module 103, and U phase voltage sampling module 104 is identical with the inner structure of V phase voltage sampling module 105 and W phase voltage sampling module 106, so be described further above-mentioned Intelligent Power Module below in conjunction with the principle of work of U phase adjusting module 101 and U phase voltage sampling module 104:

Suppose that the anode of the first voltage source V 1 is V to the voltage of negative terminal iT, then the anode of the second voltage source V 2 is 15V-V to the voltage of negative terminal iT.

When the power end VCC of HVIC chip 100 just powers on, the output terminal Q of the first rest-set flip-flop RS1 and output terminal Q all output low levels of the second rest-set flip-flop RS2.

State one: when LIN1 accesses high level first, then LO1 is also high level, so IGBT pipe Q4 conducting, thus make VS1 be 0 voltage, VB1 is not now charged, so be also 0 voltage, the high level of LIN1 is also high level after the first Schmidt trigger U1, thus make first or door U2 output high level, and the second input end S of the second rest-set flip-flop RS2 is high level, then the output terminal Q of the second rest-set flip-flop RS2 exports as high level, and then make described high pressure DMOS pipe DM4 conducting, so the second comparer U13 is by voltage (the i.e. 15V-V of the voltage of VS1 and the second voltage source V 2 iT) compare, because VS1 is 0 voltage, so the second comparer U13 output low level, 8th not gate U14 output low level and second not gate U5 export high level, that is first Sheffer stroke gate U3 first input end 1 and the second input end 2 be all high level, so the first Sheffer stroke gate U3 output low level, this low transition is high level output by the first not gate U4, then high pressure DMOS pipe DM1 conducting, the power end VCC of HVIC chip 100 charges to filter capacitor C1 and storage capacitor C4 charging (namely charging to filter capacitor C1 and storage capacitor C4) by high pressure DMOS pipe DM1 to VB1, the high level of LIN1 is high level after the 25 not gate U43 and the 26 not gate U44, then high pressure DMOS pipe DM7 conducting, and the first comparer U8 is by voltage (the i.e. V of the voltage of VB1 and the first voltage source V 1 iT) compare, and due to VB1 place just by charging time voltage very low, so the first voltage comparator U8 keeps low level output, and then make the 3rd not gate U6 export high level, 5th not gate U9 exports high level, then the first input end R of the first rest-set flip-flop RS1 and the second input end S is respectively high level and low level, and the first rest-set flip-flop RS1 output terminal Q keeps low level output, then the 4th not gate U7 exports high level, be continuously charged to VB1 voltage over the ground higher than V at VB1 iT, then the output of the first comparer U8 becomes high level from low level, 3rd not gate U6 output low level thereupon, the high level that first comparer U8 exports is from the waveform M of the common contact of the input end of the input end of the 5th not gate U9 and the 6th not gate U11, the waveform A of the first input end 1 of the first rejection gate U10, the waveform C of the waveform B of second input end 2 of the first rejection gate U10 and the output terminal 3 of the first rejection gate U10 as shown in Figure 8, owing to there is electric capacity C7, input end and the high level of the common contact of the input end of the 6th not gate U11 of the 5th not gate U9 arrive the time slightly time delay of time than the first input end 1 of the first rejection gate U10 of second input end 2 of the first rejection gate U10, delay time can be set to 300ns by the electric capacity of adjustment electric capacity C7, then the output terminal 3 of the first rejection gate U10 can produce the high level of a 300ns at the rising edge of waveform M, this high level can make the output terminal Q of the first rest-set flip-flop RS1 export high level, and after the high level of waveform C disappears, make the output terminal Q of the first rest-set flip-flop RS1 keep high level constant.

State two: when LIN1 becomes low level from high level, if the voltage of VB1 is higher than V iT, then the 4th not gate U7 output low level, if the voltage of VB1 is still lower than V iT, then the output of the 4th not gate U7 is high level; If the 4th not gate U7 output low level, then first or door U2 output low level, then the first Sheffer stroke gate U3 exports high level, the first not gate U4 output low level, and then high pressure DMOS pipe DM1 is turned off, and the power end VCC stopping of HVIC chip 100 is charged to VB1; If the 4th not gate U7 exports high level, then first or door U2 export high level, so, when LIN1 just becomes low level from high level, the second input end S of the second rest-set flip-flop RS2 becomes low level, and the single R of its first input keeps low level, at this moment, the output terminal Q of the second rest-set flip-flop RS2 keeps original high level output;

In above process, the voltage of VS1 may raise gradually, when the voltage of VS1 is also lower than voltage (the i.e. 15V-V of the second voltage source V 2 iT) time, the output terminal Q of the second comparer U13 keeps high level, then the 8th not gate U14 keeps low level output, and the second not gate U5 keeps high level output, so the first Sheffer stroke gate U3 output low level, first not gate U4 exports high level, so high pressure DMOS pipe DM1 keeps conducting state, the power end VCC of HVIC chip 100 continues to charge to VB1, and then ensure that the pressure drop ratio between VB1 and VS1 is lower, and LIN1 is when being in low level state, still can be charged to VB1 by the power end VCC of HVIC chip 100, thus make Intelligent Power Module when just starting, the ascending velocity of the voltage of VB1 is largely increased.

When the voltage of VS1 is higher than voltage (the i.e. 15-V of the second voltage source V 2 iT) time, second comparer U13 exports high level, then the output terminal Q of the second rest-set flip-flop RS2 is reset and output low level, so high pressure DMOS pipe DM4 turns off, after high pressure DMOS pipe SM4 is turned off, the output of the second comparer U13 reverts to low level, but the second input end S because of the second rest-set flip-flop RS2 is still low level, so the output terminal Q of the second rest-set flip-flop RS2 keeps low level constant, the then constant output high level of the 8th not gate U14, second not gate U5 then constant output low level, thus make the first Sheffer stroke gate U3 export high level, first not gate U4 output low level, high pressure DMOS pipe DM1 is turned off, the power end VCC of HVIC chip 100 stops charging to VB1.

State three: when LIN1 accesses high level again, the output terminal Q of the second rest-set flip-flop RS2 is become high level by set again, LO1 exports high level, IGBT pipe Q4 conducting, then VS1 is no-voltage, the input/output state of each components and parts returns to the situation of above-mentioned state one, so moves in circles and carries out work.

Because U phase adjusting module 101 is identical with the inner structure of V phase adjusting module 102 and W phase adjusting module 103, U phase voltage sampling module 104 is identical with the inner structure of V phase voltage sampling module 105 and W phase voltage sampling module 106, so V phase adjusting module 102 is identical with the principle of work of principle of work all with above-mentioned of W phase voltage sampling module 106 with W phase adjusting module 103 with the principle of work of V phase voltage sampling module 105, therefore repeat no more.

The embodiment of the present invention comprises high pressure DMOS pipe DM1 by adopting in Intelligent Power Module, high pressure DMOS pipe DM2, high pressure DMOS pipe DM3, U phase adjusting module, V phase adjusting module, W phase adjusting module, U phase voltage sampling module, the HVIC chip of V phase voltage sampling module and W phase voltage sampling module, brachium pontis signal end on first of HVIC chip, the first power supply anode of HVIC chip can be made when brachium pontis signal end is low level (low level time is greater than high level time) on brachium pontis signal end and the 3rd on second, second power supply anode and the 3rd power supply anode charge to filter capacitor and the external storage capacitor of Intelligent Power Module, duration of charging is significantly increased, thus Intelligent Power Module is correspondingly increased the duration of charging of filter capacitor and storage capacitor when starting, and and then reduce the thermal value of IGBT pipe when electrifying startup works, extend the serviceable life of IGBT pipe and the serviceable life of Intelligent Power Module, improve the safety in utilization of Intelligent Power Module.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.

Claims (7)

1. an Intelligent Power Module, comprises HVIC chip, IGBT pipe Q1, fast recovery diode D1, IGBT pipe Q2, fast recovery diode D2, IGBT pipe Q3, fast recovery diode D3, IGBT pipe Q4, fast recovery diode D4, IGBT pipe Q5, fast recovery diode D5, IGBT pipe Q6, fast recovery diode D6, filter capacitor C1, filter capacitor C2 and filter capacitor C3, the power end of described HVIC chip is that the low-pressure area of described Intelligent Power Module is powered anode, described HVIC chip first on brachium pontis signal end, brachium pontis input end in the U phase that on second, on brachium pontis signal end and the 3rd, brachium pontis signal end is respectively described Intelligent Power Module, brachium pontis input end in brachium pontis input end and W phase in V phase, first time brachium pontis signal end of described HVIC chip, second time brachium pontis signal end and the 3rd time brachium pontis signal end are respectively the lower brachium pontis input end of U phase of described Intelligent Power Module, the lower brachium pontis input end of V phase and the lower brachium pontis input end of W phase, the earth terminal of described HVIC chip to be powered negative terminal as the low-pressure area of described Intelligent Power Module, first power supply anode of described HVIC chip to be powered anode as the U phase higher-pressure region of described Intelligent Power Module, first higher-pressure region control end of described HVIC chip is connected with the grid of described IGBT pipe Q1, first power supply negative terminal of described HVIC chip and the source electrode of described IGBT pipe Q1, the anode of described fast recovery diode D1, the drain electrode of described IGBT pipe D4 and the negative electrode of the described fast recovery diode D4 U phase higher-pressure region connect altogether as described Intelligent Power Module powers negative terminal, the U phase higher-pressure region that described filter capacitor C1 is connected to described Intelligent Power Module anode of powering is powered between negative terminal with U phase higher-pressure region, second power supply anode of described HVIC chip to be powered anode as the V phase higher-pressure region of described Intelligent Power Module, second higher-pressure region control end of described HVIC chip is connected with the grid of described IGBT pipe Q2, second power supply negative terminal of described HVIC chip and the source electrode of described IGBT pipe Q2, the anode of described fast recovery diode D2, the drain electrode of described IGBT pipe Q5 and the negative electrode of the described fast recovery diode D5 V phase higher-pressure region connect altogether as Intelligent Power Module powers negative terminal, the V phase higher-pressure region that described filter capacitor C2 is connected to described Intelligent Power Module anode of powering is powered between negative terminal with V phase higher-pressure region, 3rd power supply anode of described HVIC chip to be powered anode as the W phase higher-pressure region of described Intelligent Power Module, the third high nip control end of described HVIC chip is connected with the grid of described IGBT pipe Q3, 3rd power supply negative terminal of described HVIC chip and the source electrode of described IGBT pipe Q3, the anode of described fast recovery diode D3, the drain electrode of described IGBT pipe Q6 and the negative electrode of the described fast recovery diode D6 W phase higher-pressure region connect altogether as described Intelligent Power Module powers negative terminal, the W phase higher-pressure region that described filter capacitor C3 is connected to Intelligent Power Module anode of powering is powered between negative terminal with W phase higher-pressure region, first low-pressure area control end of described HVIC chip, the second low-pressure area control end and the 3rd low-pressure area control end are connected with the grid of the grid of described IGBT pipe Q4, the grid of described IGBT pipe Q5 and described IGBT pipe Q6 respectively, the drain electrode of described IGBT pipe Q1 and the negative electrode of described fast recovery diode D1, the drain electrode of described IGBT pipe Q2, the negative electrode of described fast recovery diode D2, the drain electrode of described IGBT pipe Q3 and the negative electrode of described fast recovery diode D3 connect the high voltage input end of formed common contact as described Intelligent Power Module altogether, source electrode and the anode of described fast recovery diode D4 of described IGBT pipe Q4 connect the U phase low reference voltage end of formed common contact as described Intelligent Power Module altogether, source electrode and the anode of described fast recovery diode D5 of described IGBT pipe Q5 connect the V phase low reference voltage end of formed common contact as described Intelligent Power Module altogether, source electrode and the anode of described fast recovery diode D6 of described IGBT pipe Q6 connect the W phase low reference voltage end of formed common contact as described Intelligent Power Module altogether, it is characterized in that:
Described HVIC chip comprises a boostrap circuit, and described boostrap circuit comprises:
High pressure DMOS pipe DM1, high pressure DMOS pipe DM2, high pressure DMOS pipe DM3, U phase adjusting module, V phase adjusting module, W phase adjusting module, U phase voltage sampling module, V phase voltage sampling module and W phase voltage sampling module;
The source electrode of the source electrode of described high pressure DMOS pipe DM1 and the source electrode of described high pressure DMOS pipe DM2 and described high pressure DMOS pipe DM3 is connected to the power end of described HVIC chip altogether, the drain electrode of described high pressure DMOS pipe DM1, the drain electrode of described high pressure DMOS pipe DM2 and the drain electrode of described high pressure DMOS pipe DM3 connect the first power supply anode of described HVIC chip respectively, second power supply anode and the 3rd power supply anode, the substrate of described high pressure DMOS pipe DM1, the substrate of described high pressure DMOS pipe DM2 and the equal ground connection of substrate of described high pressure DMOS pipe DM3, the first input end of described U phase adjusting module and the control end of described U phase voltage sampling module are connected to first time brachium pontis signal end of described HVIC chip altogether, input end and the output terminal of described U phase voltage sampling module are connected the drain electrode of described high pressure DMOS pipe DM1 and the second input end of described U phase adjusting module respectively, 3rd input end and the output terminal of described U phase adjusting module are connected the first power supply negative terminal of described HVIC chip and the grid of described high pressure DMOS pipe DM1 respectively, the first input end of described V phase adjusting module and the control end of described V phase voltage sampling module are connected to second time brachium pontis signal end of described HVIC chip altogether, input end and the output terminal of described V phase voltage sampling module are connected the drain electrode of described high pressure DMOS pipe DM2 and the second input end of described V phase adjusting module respectively, 3rd input end and the output terminal of described V phase adjusting module are connected the second power supply negative terminal of described HVIC chip and the grid of described high pressure DMOS pipe DM2 respectively, the first input end of described W phase adjusting module and the control end of described W phase voltage sampling module are connected to the 3rd time brachium pontis signal end of described HVIC chip altogether, input end and the output terminal of described W phase voltage sampling module are connected the drain electrode of described high pressure DMOS pipe DM3 and the second input end of described W phase adjusting module respectively, 3rd input end and the output terminal of described W phase adjusting module are connected the 3rd power supply negative terminal of described HVIC chip and the grid of described high pressure DMOS pipe DM3 respectively,
When first time brachium pontis signal end of described HVIC chip, second time brachium pontis signal end and the 3rd time brachium pontis signal end are high level, described HVIC chip first on brachium pontis signal end, second on brachium pontis signal end and the 3rd brachium pontis signal end be low level; When first time brachium pontis signal end of described HVIC chip, second time brachium pontis signal end and the 3rd time brachium pontis signal end are low level, described HVIC chip first on brachium pontis signal end, second on brachium pontis signal end and the 3rd brachium pontis signal end be high level or low level;
When on first of described HVIC chip, brachium pontis signal end is low level, the level that described U phase adjusting module inputs according to first time brachium pontis signal end of described HVIC chip, the voltage of the output voltage of described U phase voltage sampling module and the first power supply negative terminal of described HVIC chip exports high level and drives described high pressure DMOS pipe DM1 conducting, and the voltage that inputs of the power end of described HVIC chip is charged to filter capacitor C1 and the U phase higher-pressure region that the is connected to described Intelligent Power Module storage capacitor that anode and U phase higher-pressure region power between negative terminal of powering by described high pressure DMOS pipe DM1,
When on second of described HVIC chip, brachium pontis signal end is low level, the level that described V phase adjusting module inputs according to second time brachium pontis signal end of described HVIC chip, the voltage of the output voltage of described V phase voltage sampling module and the second power supply negative terminal of described HVIC chip exports high level and drives described high pressure DMOS pipe DM2 conducting, and the voltage that inputs of the power end of described HVIC chip is charged to filter capacitor C2 and the V phase higher-pressure region that the is connected to described Intelligent Power Module storage capacitor that anode and V phase higher-pressure region power between negative terminal of powering by described high pressure DMOS pipe DM2,
When on the 3rd of described HVIC chip the, brachium pontis signal end is low level, described W phase adjusting module is according to the level that the 3rd of described HVIC chip the time brachium pontis signal end inputs, the voltage of the output voltage of described W phase voltage sampling module and the 3rd power supply negative terminal of described HVIC chip exports high level and drives described high pressure DMOS pipe DM3 conducting, and the voltage that inputs of the power end of described HVIC chip is charged to filter capacitor C3 and the W phase higher-pressure region that the is connected to described Intelligent Power Module storage capacitor that anode and W phase higher-pressure region power between negative terminal of powering by described high pressure DMOS pipe DM3.
2. Intelligent Power Module as claimed in claim 1, it is characterized in that, described U phase adjusting module comprises:
First Schmidt trigger, first or door, the first Sheffer stroke gate, the first not gate, the second not gate, the 3rd not gate, the first rest-set flip-flop, the 4th not gate, the first comparer, the first voltage source, the 5th not gate, the first rejection gate, the 6th not gate, the 7th not gate, electric capacity C7, the second rest-set flip-flop, the second comparer, the 8th not gate, the second voltage source and high pressure DMOS pipe DM4;
The input end of described first Schmidt trigger is the first input end of described U phase adjusting module, the output terminal of described first Schmidt trigger connects described first or the first input end of door and the second input end of described second rest-set flip-flop simultaneously, described first or the second input end of door connect the output terminal of described 4th not gate, described first or output terminal and the output terminal of described second not gate of door be connected first input end and second input end of described first Sheffer stroke gate respectively, the output terminal of described first Sheffer stroke gate connects the input end of described first not gate, the output terminal of described first not gate is the output terminal of described U phase adjusting module, the in-phase input end of described first comparer is the second input end of described U phase adjusting module, anode and the negative terminal of described first voltage source are connected inverting input and the ground of described first comparer respectively, the output terminal of described first comparer connects the input end of described 3rd not gate simultaneously, the input end of described 5th not gate and the input end of described 6th not gate, the output terminal of described 3rd not gate connects the first input end of described first rest-set flip-flop, the output terminal of described 5th not gate connects the first input end of described first rejection gate, the output terminal of described 6th not gate and the first end of described electric capacity C7 are connected to the input end of described 7th not gate altogether, the second end ground connection of described electric capacity C7, the output terminal of described 7th not gate connects the second input end of described first rejection gate, the output terminal of described first rejection gate connects the second input end of described first rest-set flip-flop, the output terminal of described first rest-set flip-flop connects the input end of described 4th not gate, the drain electrode of described high pressure DMOS pipe DM4 is the 3rd input end of described U phase adjusting module, the Substrate ground of described high pressure DMOS pipe DM4, the source electrode of described high pressure DMOS pipe DM4 connects the in-phase input end of described second comparer, the grid of described high pressure DMOS pipe DM4 is connected with the output terminal of described second rest-set flip-flop and the input end of described 8th not gate simultaneously, anode and the negative terminal of described second voltage source are connected inverting input and the ground of described second comparer respectively, the output terminal of described second comparer connects the first input end of described second rest-set flip-flop, the output terminal of described 8th not gate connects the input end of described second not gate.
3. Intelligent Power Module as claimed in claim 1, it is characterized in that, described V phase adjusting module comprises:
Second Schmidt trigger, second or door, the second Sheffer stroke gate, the 9th not gate, the tenth not gate, the 11 not gate, the 3rd rest-set flip-flop, the 12 not gate, the 3rd comparer, tertiary voltage source, the 13 not gate, the second rejection gate, the 14 not gate, the 15 not gate, electric capacity C8, the 4th rest-set flip-flop, the 4th comparer, the 16 not gate, the 4th voltage source and high pressure DMOS pipe DM5;
The input end of described second Schmidt trigger is the first input end of described V phase adjusting module, the output terminal of described second Schmidt trigger connects described second or the first input end of door and the second input end of described 4th rest-set flip-flop simultaneously, described second or the second input end of door connect the output terminal of described 12 not gate, described second or output terminal and the output terminal of described tenth not gate of door be connected first input end and second input end of described second Sheffer stroke gate respectively, the output terminal of described second Sheffer stroke gate connects the input end of described 9th not gate, the output terminal of described 9th not gate is the output terminal of described V phase adjusting module, the in-phase input end of described 3rd comparer is the second input end of described V phase adjusting module, anode and the negative terminal in described tertiary voltage source are connected inverting input and the ground of described 3rd comparer respectively, the output terminal of described 3rd comparer connects the input end of described 11 not gate simultaneously, the input end of described 13 not gate and the input end of described 14 not gate, the output terminal of described 11 not gate connects the first input end of described 3rd rest-set flip-flop, the output terminal of described 13 not gate connects the first input end of described second rejection gate, the output terminal of described 14 not gate and the first end of described electric capacity C8 are connected to the input end of described 15 not gate altogether, the second end ground connection of described electric capacity C8, the output terminal of described 15 not gate connects the second input end of described second rejection gate, the output terminal of described second rejection gate connects the second input end of described 3rd rest-set flip-flop, the output terminal of described 3rd rest-set flip-flop connects the input end of described 12 not gate, the drain electrode of described high pressure DMOS pipe DM5 is the 3rd input end of described V phase adjusting module, the Substrate ground of described high pressure DMOS pipe DM5, the source electrode of described high pressure DMOS pipe DM5 connects the in-phase input end of described 4th comparer, the grid of described high pressure DMOS pipe DM5 is connected with the output terminal of described 4th rest-set flip-flop and the input end of described 16 not gate simultaneously, anode and the negative terminal of described 4th voltage source are connected inverting input and the ground of described 4th comparer respectively, the output terminal of described 4th comparer connects the first input end of described 4th rest-set flip-flop, the output terminal of described 16 not gate connects the input end of described tenth not gate.
4. Intelligent Power Module as claimed in claim 1, it is characterized in that, described W phase adjusting module comprises:
3rd Schmidt trigger, the 3rd or door, the 3rd Sheffer stroke gate, the 17 not gate, the 18 not gate, the 19 not gate, the 5th rest-set flip-flop, the 20 not gate, the 5th comparer, the 5th voltage source, the 21 not gate, the 3rd rejection gate, the 22 not gate, the 23 not gate, electric capacity C9, the 6th rest-set flip-flop, the 6th comparer, the 24 not gate, the 6th voltage source and high pressure DMOS pipe DM6;
The input end of described 3rd Schmidt trigger is the first input end of described W phase adjusting module, the output terminal of described 3rd Schmidt trigger connects the described 3rd or the first input end of door and the second input end of described 6th rest-set flip-flop simultaneously, described 3rd or the second input end of door connect the output terminal of described 20 not gate, described 3rd or output terminal and the output terminal of described 18 not gate of door be connected first input end and second input end of described 3rd Sheffer stroke gate respectively, the output terminal of described 3rd Sheffer stroke gate connects the input end of described 17 not gate, the output terminal of described 17 not gate is the output terminal of described W phase adjusting module, the in-phase input end of described 5th comparer is the second input end of described W phase adjusting module, anode and the negative terminal of described 5th voltage source are connected inverting input and the ground of described 5th comparer respectively, the output terminal of described 5th comparer connects the input end of described 19 not gate simultaneously, the input end of described 21 not gate and the input end of described 22 not gate, the output terminal of described 19 not gate connects the first input end of described 5th rest-set flip-flop, the output terminal of described 21 not gate connects the first input end of described 3rd rejection gate, the output terminal of described 22 not gate and the first end of described electric capacity C9 are connected to the input end of described 23 not gate altogether, the second end ground connection of described electric capacity C9, the output terminal of described 23 not gate connects the second input end of described 3rd rejection gate, the output terminal of described 3rd rejection gate connects the second input end of described 5th rest-set flip-flop, the output terminal of described 5th rest-set flip-flop connects the input end of described 20 not gate, the drain electrode of described high pressure DMOS pipe DM6 is the 3rd input end of described W phase adjusting module, the Substrate ground of described high pressure DMOS pipe DM6, the source electrode of described high pressure DMOS pipe DM6 connects the in-phase input end of described 6th comparer, the grid of described high pressure DMOS pipe DM6 is connected with the output terminal of described 6th rest-set flip-flop and the input end of described 24 not gate simultaneously, anode and the negative terminal of described 6th voltage source are connected inverting input and the ground of described 6th comparer respectively, the output terminal of described 6th comparer connects the first input end of described 6th rest-set flip-flop, the output terminal of described 24 not gate connects the input end of described 18 not gate.
5. Intelligent Power Module as claimed in claim 1, it is characterized in that, described U phase voltage sampling module comprises:
25 not gate, the 26 not gate and high pressure DMOS pipe DM7;
The input end of described 25 not gate is the control end of described U phase voltage sampling module, the output terminal of described 25 not gate connects the input end of described 26 not gate, the output terminal of described 26 not gate connects the grid of described high pressure DMOS pipe DM7, the drain electrode of described high pressure DMOS pipe DM7 and source electrode are respectively input end and the output terminal of described U phase voltage sampling module, the Substrate ground of described high pressure DMOS pipe DM7.
6. Intelligent Power Module as claimed in claim 1, it is characterized in that, described V phase voltage sampling module comprises:
27 not gate, the 28 not gate and high pressure DMOS pipe DM8;
The input end of described 27 not gate is the control end of described V phase voltage sampling module, the output terminal of described 27 not gate connects the input end of described 28 not gate, the output terminal of described 28 not gate connects the grid of described high pressure DMOS pipe DM8, the drain electrode of described high pressure DMOS pipe DM8 and source electrode are respectively input end and the output terminal of described V phase voltage sampling module, the Substrate ground of described high pressure DMOS pipe DM8.
7. Intelligent Power Module as claimed in claim 1, it is characterized in that, described W phase voltage sampling module comprises:
29 not gate, the 30 not gate and high pressure DMOS pipe DM9;
The input end of described 29 not gate is the control end of described W phase voltage sampling module, the output terminal of described 29 not gate connects the input end of described 30 not gate, the output terminal of described 30 not gate connects the grid of described high pressure DMOS pipe DM9, the drain electrode of described high pressure DMOS pipe DM9 and source electrode are respectively input end and the output terminal of described W phase voltage sampling module, the Substrate ground of described high pressure DMOS pipe DM9.
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CN104821705B (en) * 2015-04-28 2018-03-27 广东美的制冷设备有限公司 Intelligent power module circuit and air conditioner
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