CN203055466U - Shifting register unit, shifting register, array substrate and display device - Google Patents
Shifting register unit, shifting register, array substrate and display device Download PDFInfo
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- CN203055466U CN203055466U CN 201320060333 CN201320060333U CN203055466U CN 203055466 U CN203055466 U CN 203055466U CN 201320060333 CN201320060333 CN 201320060333 CN 201320060333 U CN201320060333 U CN 201320060333U CN 203055466 U CN203055466 U CN 203055466U
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- shift register
- switching tube
- register cell
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Abstract
The embodiment of the utility model discloses a shifting register unit, a shifting register, an array substrate and a display device, relates to the field of displays and can independently reset all the shifting register units. The shifting register unit comprises a sampling part, an outputting part and a resetting part, wherein the sampling part comprises a first switching tube and a second switching tube; the outputting part comprises a fifth switching tube, a sixth switching tube, a first capacitor and a second capacitor; and the resetting part comprises a third switching tube and a fourth switching tube.
Description
Technical field
The utility model relates to field of display, relates in particular to a kind of shift register cell, shift register, array base palte and display device.
Background technology
Continuous development along with display technique, adopt the active matrix display of thin film transistor (TFT) to become the most common panel display apparatus, its gate driver circuit is realized in the mode of shift register usually, shift register is made up of the shift register cell of a plurality of cascades, each shift register cell is output signal successively, to realize the driving line by line of grid.
Existing shift register cell comprises sampling, three duties of exporting, reset.In two adjacent shift register cells, the output signal of a back shift register cell is as the reset signal of previous shift register cell, so that previous shift register cell stops output.But if previous shift register cell does not receive the reset signal from a back shift register cell, previous shift register cell just can not stop output.Therefore, resetting of previous shift register cell controlled by a back shift register cell in the prior art, then can't smoothly or postpone to feed back to previous shift register cell as if the reset signal from a back shift register cell, then previous shift register cell just can not stop output according to predetermined time, and what then may cause whole array base palte even LCD can't operate as normal.So, need to solve the problem that this shift register cell can't individual reset.
The utility model content
Technical problem to be solved in the utility model is to provide a kind of shift register cell, shift register, array base palte and display device, makes that each shift register cell can individual reset.
For solving the problems of the technologies described above, the utility model adopts following technical scheme:
The utility model first aspect provides a kind of shift register cell, comprising:
Sampling section, output and the part that resets,
Wherein, described sampling section comprises first switching tube and second switch pipe, and described output comprises the 5th switching tube, the 6th switching tube, first electric capacity and second electric capacity, and described reset portion branch comprises the 3rd switching tube, the 4th switching tube;
The source electrode of described first switching tube connects the input end of described shift register cell, receives the input signal from described input end, and the grid of described first switching tube connects first clock signal; The grid of described second switch pipe is connected the second clock signal with source electrode, described second clock signal and described first clock signal are anti-phase; The grid of described the 3rd switching tube is connected described first clock signal with source electrode; The grid of described the 4th switching tube connects described second clock signal, and the source electrode of described the 4th switching tube connects power supply input signal; The source electrode of described the 5th switching tube connects described second clock signal, and the grid of described the 5th switching tube connects the drain electrode of described first switching tube and described second switch pipe, and the drain electrode of described the 5th switching tube connects the output terminal of described shift register cell; The grid of described the 6th switching tube connects the drain electrode of described the 3rd switching tube and described the 4th switching tube, and the source electrode of described the 6th switching tube connects described power supply input signal, and the drain electrode of described the 6th switching tube connects the output terminal of described shift register cell; One end of described first electric capacity connects the grid of described the 5th switching tube, and the other end connects the output terminal of described shift register cell; One end of described second electric capacity connects the grid of described the 6th switching tube, and the other end connects described power supply input signal.
Described first to the 6th switching tube is metal-oxide-semiconductor or thin film transistor (TFT).
Described thin film transistor (TFT) is P type thin film transistor (TFT) or is the N-type thin film transistor (TFT).
When described first to the 6th switching tube was P type thin film transistor (TFT), described power supply input signal was high level;
In very first time section, described input signal is low level, and described first clock signal is low level, and described second clock signal is high level, and then the output signal of described shift register cell is high level;
In second time period, described input signal is high level, and described first clock signal is high level, and described second clock signal is low level, and then the output signal of described shift register cell is low level;
In the 3rd time period, described input signal is high level, and described first clock signal is low level, and described second clock signal is high level, and then the output signal of described shift register cell is high level.
When described first to the 6th switching tube was the N-type thin film transistor (TFT), described power supply input signal was low level;
In very first time section, described input signal is high level, and described first clock signal is high level, and described second clock signal is low level, and then the output signal of described shift register cell is low level;
In second time period, described input signal is low level, and described first clock signal is low level, and described second clock signal is high level, and then the output signal of described shift register cell is high level;
In the 3rd time period, described input signal is low level, and described first clock signal is high level,
Described second clock signal is low level, and then the output signal of described shift register cell is low level.
The utility model second aspect provides a kind of shift register, the above-mentioned shift register cell that comprises n cascade, described n is the integer greater than 1, wherein, the input end of the 1st described shift register cell is connected to the signal input part of described shift register, and the output terminal of n described shift register cell is connected to the signal output part of described shift register.
The utility model third aspect provides a kind of array base palte, comprises above-mentioned shift register.
The utility model fourth aspect provides a kind of LCD, comprises above-mentioned array base palte.
In embodiment of the present utility model, the structure of this shift register cell makes this shift register cell after receiving input signal, can export corresponding output signal, and behind output signal output, from horizontal reset, need not wait by the time the output signal of next shift register cell as reset signal after, reset according to reset signal again.Guarantee the operate as normal of shift register cell, and then guaranteed the operate as normal of whole array base palte even LCD.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, the accompanying drawing of required use is done to introduce simply in will describing embodiment below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the structural representation of the shift register cell among the utility model embodiment;
Fig. 2 is the structural representation of the shift register cell of the P type thin film transistor (TFT) among the utility model embodiment;
Fig. 3 is the sequential chart of the shift register cell of the P type thin film transistor (TFT) among the utility model embodiment;
Fig. 4 is the structural representation of the shift register cell of the N-type thin film transistor (TFT) among the utility model embodiment;
Fig. 5 is the sequential chart of the shift register cell of the N-type thin film transistor (TFT) among the utility model embodiment.
Embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the utility model protection.
The first aspect of the utility model embodiment provides a kind of shift register cell, and to the description of this shift register cell, as shown in Figure 1, described shift register cell comprises for convenience:
Wherein, described sampling section comprises first switch transistor T 1 and second switch pipe T2, and described output comprises the 5th switch transistor T 5, the 6th switch transistor T 6, first capacitor C 1 and second capacitor C 2, and described reset portion branch comprises the 3rd switch transistor T 3, the 4th switch transistor T 4;
Concrete, the source electrode of described first switch transistor T 1 connects the input end of described shift register cell, receives the input signal IN from described input end, and the grid of described first switch transistor T 1 connects the first clock signal C K; The grid of described second switch pipe T2 is connected second clock signal CKB with source electrode, described second clock signal CKB and the described first clock signal C K are anti-phase; The grid of described the 3rd switch transistor T 3 is connected the described first clock signal C K with source electrode; The grid of described the 4th switch transistor T 4 connects described second clock signal CKB, and the source electrode of described the 4th switch transistor T 4 connects power supply input signal V; The source electrode of described the 5th switch transistor T 5 connects described second clock signal CKB, the grid of described the 5th switch transistor T 5 connects the drain electrode of described first switch transistor T 1 and described second switch pipe T2, and the drain electrode of described the 5th switch transistor T 5 connects the output terminal of described shift register cell; The grid of described the 6th switch transistor T 6 connects the drain electrode of described the 3rd switch transistor T 3 and described the 4th switch transistor T 4, the source electrode of described the 6th switch transistor T 6 connects described power supply input signal V, and the drain electrode of described the 6th switch transistor T 6 connects the output terminal of described shift register cell; One end of described first capacitor C 1 connects the grid of described the 5th switch transistor T 5, and the other end connects the output terminal of described shift register cell; One end of described second capacitor C 2 connects the grid of described the 6th switch transistor T 6, and the other end connects described power supply input signal V.
In the technical scheme of present embodiment, the structure of this shift register cell makes this shift register cell after receiving input signal, can export corresponding output signal, and behind output signal output, from horizontal reset, need not wait by the time the output signal of next shift register cell as reset signal after, reset according to reset signal again.Guarantee the operate as normal of shift register cell, and then guaranteed the operate as normal of whole array base palte even LCD.
Need to prove that in the utility model embodiment, high level is VGH to be represented, low level is VGL and represents.
Preferably, described first to the 6th switching tube all can be metal-oxide-semiconductor or thin film transistor (TFT).Further, described thin film transistor (TFT) can be P type thin film transistor (TFT) or is the N-type thin film transistor (TFT), wherein, because the mobility of polycrystalline SiTFT is higher, is particularly useful for shift register cell.
As shown in Figure 2, when described first to the 6th switching tube is P type thin film transistor (TFT),
In very first time section t1, described input signal IN is low level VGL, and the described first clock signal C K is low level VGL, and described second clock signal CKB is high level VGH, and then the output signal OUT of described shift register cell is high level VGH;
Concrete, in very first time section t1, described shift register cell enters sample phase.
At this moment, described input signal IN is low level VGL, and the described first clock signal C K is low level VGL, makes first and third switch transistor T 1, T3 conducting; Simultaneously, because described second clock signal CKB and the described first clock signal C K are anti-phase, then described second clock signal CKB is VGH, and then second switch pipe T2 and the 4th switch transistor T 4 can't conductings.So the level that this moment, N1, N2 were ordered is pulled down to (threshold voltage of any thin film transistor (TFT) of low level VGL+Vth() accordingly), so the 6th switch transistor T 6 conductings, because the source electrode of the 6th switch transistor T 6 connects high level VGH, drain electrode connects the output terminal of described shift register cell.Then the output signal OUT of described shift register cell is high level VGH.
And because the level that N1 is ordered is (low level VGL+Vth), the output terminal output high level VGH of the 6th switch transistor T 6, at this moment, first capacitor C 1 between the output terminal of N1 point and the 6th switch transistor T 6 is recharged, IN charges to input signal, and then the voltage difference at first capacitor C, 1 two ends is (high level VGH-low level VGL-threshold voltage Vth).
In second time period t 2, described input signal is high level VGH, and the described first clock signal C K is high level VGH, and described second clock signal CKB is low level VGL, and then the output signal of described shift register cell is low level VGL;
Concrete, in second time period t 2, described shift register cell enters output stage.
At this moment, input signal IN and the first clock signal C K are high level VGH, and the switch transistor T 1 of winning is turn-offed, because the effect of first capacitor C 1, the level that N1 is ordered is kept, and still is (low level VGL+ threshold voltage Vth), so the T5 conducting, output low level VGL.Simultaneously, because the level of second clock signal CKB is low level VGL, so second, four switch transistor T 2, T4 conducting, because the source electrode of the 4th switch transistor T 4 connects high level VGH, the level that this moment, N2 was ordered is high level VGH, has turn-offed the 6th switch transistor T 6.Then this moment, the output signal of shift register cell is the low level VGL of the 5th switch transistor T 5 outputs.
In the 3rd time period t 3, described input signal IN is high level VGH, and the described first clock signal C K is low level VGL, and described second clock signal CKB is high level VGH, and then the output signal of described shift register cell is high level VGH.
Concrete, in the 3rd time period t 3, described shift register cell enters reseting stage.
At this moment, the first clock signal C K is low level VGL, and input signal IN is high level VGH, 1 conducting of first switch transistor T, and the level that makes N1 order is drawn high high level VGH, and the 5th switch transistor T 5 is turned off.Simultaneously, because the first clock signal C K is low level VGL, 3 conductings of the 3rd switch transistor T, the current potential of N2 is pulled low to (low level VGL+ threshold voltage Vth), make the 6th switch transistor T 6 be switched on, make the output signal OUT of shift register cell be drawn high again and be high level VGH, realize the individual reset of shift register cell.
In addition, in other stages of this shift register cell, second capacitor C 2 has kept the N2 point to be in low level VGL, has guaranteed the conducting of the 6th switch transistor T 6, makes output signal OUT be always high level VGH, has improved the stability of output signal OUT.
As shown in Figure 4, when described first to the 6th switching tube is the N-type thin film transistor (TFT), shift register cell also can be realized the individual reset function, the power supply input signal V of this moment is low level VGL, because the shift register cell course of work of N-type thin film transistor (TFT) and the shift register cell of P type thin film transistor (TFT) are similar, do not repeat them here.
Need to prove that the input signal IN of the shift register cell of N-type thin film transistor (TFT), the first clock signal C K, second clock signal CKB and output signal OUT are all anti-phase in the shift register cell of P type thin film transistor (TFT), specifically referring to Fig. 5.
In addition, the source electrode of general thin film transistor (TFT) and drain electrode can be exchanged setting.
The second aspect of present embodiment provides a kind of shift register, the above-mentioned shift register cell that comprises n cascade, described n is the integer greater than 1, wherein, the input end of the 1st described shift register cell is connected to the signal input part of described shift register, and the output terminal of n described shift register cell is connected to the signal output part of described shift register.
Because the shift register that the utility model embodiment provides has identical technical characterictic with the shift register cell that above-mentioned the utility model embodiment provides, so also can produce identical technique effect, solves identical technical matters.
The third aspect of present embodiment provides a kind of array base palte, comprises above-mentioned shift register.
The fourth aspect of present embodiment provides a kind of display device, comprises above-mentioned array base palte.Described LCD can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, televisor, display, notebook computer, digital album (digital photo frame), navigating instrument.Especially adopt the active organic LED display of low temperature polycrystalline silicon technology.
The above; it only is embodiment of the present utility model; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; can expect easily changing or replacing, all should be encompassed within the protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the protection domain of described claim.
Claims (8)
1. a shift register cell is characterized in that, comprising:
Sampling section, output and the part that resets,
Wherein, described sampling section comprises first switching tube and second switch pipe, and described output comprises the 5th switching tube, the 6th switching tube, first electric capacity and second electric capacity, and described reset portion branch comprises the 3rd switching tube, the 4th switching tube;
The source electrode of described first switching tube connects the input end of described shift register cell, receives the input signal from described input end, and the grid of described first switching tube connects first clock signal; The grid of described second switch pipe is connected the second clock signal with source electrode, described second clock signal and described first clock signal are anti-phase; The grid of described the 3rd switching tube is connected described first clock signal with source electrode; The grid of described the 4th switching tube connects described second clock signal, and the source electrode of described the 4th switching tube connects power supply input signal; The source electrode of described the 5th switching tube connects described second clock signal, and the grid of described the 5th switching tube connects the drain electrode of described first switching tube and described second switch pipe, and the drain electrode of described the 5th switching tube connects the output terminal of described shift register cell; The grid of described the 6th switching tube connects the drain electrode of described the 3rd switching tube and described the 4th switching tube, and the source electrode of described the 6th switching tube connects described power supply input signal, and the drain electrode of described the 6th switching tube connects the output terminal of described shift register cell; One end of described first electric capacity connects the grid of described the 5th switching tube, and the other end connects the output terminal of described shift register cell; One end of described second electric capacity connects the grid of described the 6th switching tube, and the other end connects described power supply input signal.
2. shift register cell according to claim 1 is characterized in that, described first to the 6th switching tube is metal-oxide-semiconductor or thin film transistor (TFT).
3. shift register cell according to claim 2 is characterized in that, described thin film transistor (TFT) is P type thin film transistor (TFT) or is the N-type thin film transistor (TFT).
4. shift register cell according to claim 3 is characterized in that, when described first to the 6th switching tube was P type thin film transistor (TFT), described power supply input signal was high level;
In very first time section, described input signal is low level, and described first clock signal is low level, and described second clock signal is high level, and then the output signal of described shift register cell is high level;
In second time period, described input signal is high level, and described first clock signal is high level, and described second clock signal is low level, and then the output signal of described shift register cell is low level;
In the 3rd time period, described input signal is high level, and described first clock signal is low level, and described second clock signal is high level, and then the output signal of described shift register cell is high level.
5. shift register cell according to claim 3 is characterized in that, when described first to the 6th switching tube was the N-type thin film transistor (TFT), described power supply input signal was low level;
In very first time section, described input signal is high level, and described first clock signal is high level, and described second clock signal is low level, and then the output signal of described shift register cell is low level;
In second time period, described input signal is low level, and described first clock signal is low level, and described second clock signal is high level, and then the output signal of described shift register cell is high level;
In the 3rd time period, described input signal is low level, and described first clock signal is high level, and described second clock signal is low level, and then the output signal of described shift register cell is low level.
6. shift register, it is characterized in that, comprise n cascade as each described shift register cell of claim 1-5, described n is the integer greater than 1, wherein, the input end of the 1st described shift register cell is connected to the signal input part of described shift register, and the output terminal of n described shift register cell is connected to the signal output part of described shift register.
7. an array base palte is characterized in that, comprises shift register as claimed in claim 6.
8. a display device is characterized in that, comprises array base palte as claimed in claim 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320060333 CN203055466U (en) | 2013-02-01 | 2013-02-01 | Shifting register unit, shifting register, array substrate and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320060333 CN203055466U (en) | 2013-02-01 | 2013-02-01 | Shifting register unit, shifting register, array substrate and display device |
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| CN203055466U true CN203055466U (en) | 2013-07-10 |
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| CN 201320060333 Withdrawn - After Issue CN203055466U (en) | 2013-02-01 | 2013-02-01 | Shifting register unit, shifting register, array substrate and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103761938A (en) * | 2013-02-01 | 2014-04-30 | 京东方科技集团股份有限公司 | Shifting register units, shifting register, array substrate and display device |
-
2013
- 2013-02-01 CN CN 201320060333 patent/CN203055466U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103761938A (en) * | 2013-02-01 | 2014-04-30 | 京东方科技集团股份有限公司 | Shifting register units, shifting register, array substrate and display device |
| WO2014117433A1 (en) * | 2013-02-01 | 2014-08-07 | 京东方科技集团股份有限公司 | Shift register units, shift register, array substrate, and display device |
| US9159447B2 (en) | 2013-02-01 | 2015-10-13 | Boe Technology Group Co., Ltd. | Shift register unit, shift register, array substrate and display apparatus |
| CN103761938B (en) * | 2013-02-01 | 2015-12-30 | 京东方科技集团股份有限公司 | Shift register cell, shift register, array base palte and display device |
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Granted publication date: 20130710 Effective date of abandoning: 20151230 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |