CN203038926U - Semiconductor power device possessing terminal protection structure - Google Patents
Semiconductor power device possessing terminal protection structure Download PDFInfo
- Publication number
- CN203038926U CN203038926U CN 201220741947 CN201220741947U CN203038926U CN 203038926 U CN203038926 U CN 203038926U CN 201220741947 CN201220741947 CN 201220741947 CN 201220741947 U CN201220741947 U CN 201220741947U CN 203038926 U CN203038926 U CN 203038926U
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- power device
- terminal protection
- semiconductor power
- edge
- epitaxial loayer
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Abstract
The utility model discloses a semiconductor power device possessing a terminal protection structure. The device comprises an active area and terminal protection areas which surround the active area. Each terminal protection area possesses a scribing edge and comprises a groove which is filled with an insulating material. The groove passes through a substrate layer along a bottom of the substrate layer and is extended into an epitaxial layer. In a width direction, the groove comprises a first edge which is overlapped with the scribing edge and a second edge which is opposite to the first edge. The second edge is extended into the substrate layer and the epitaxial layer in the active area. By using the semiconductor power device of the utility model, a length of the power device terminal protection areas is greatly shortened; a voltage endurance capability of the power device is increased.
Description
Technical field
The utility model relates to semiconductor equipment, more specifically, is a kind of semiconductor power device with terminal protection structure.
Background technology
Usually, as shown in Figure 1, it is cellular region that semiconductor power device includes source region 11() and terminal protection district 12.Wherein, active area is the working region of power device.Be example with the N-channel MOS device, active area is to form epitaxial loayer at silicon substrate, and further forms the P well region on epitaxial loayer.Wherein, silicon substrate is the N+ zone, and the bottom connects high potential during work, and epitaxial loayer is the N-zone.The terminal protection district is used for guaranteeing each active area after scribing, reduces surface field intensity, prevents the edge breakdown of device.This be because, after common active area scribing, the side (being scribe area) that is positioned at chip edge and bottom equipotential, so, at fringe region, if do not add any action, just need laterally bear very high voltage.Therefore, the side of chip is prolonged, form the terminal protection district, become the conventional way of industry.
The terminal protection district has multiple structure setting.For example, in means commonly used, one or more P traps be can increase in the terminal protection district, guard ring or potential dividing ring formed.Simultaneously, in existing processes, for preventing producing parasitic triode in the N-zone transoid on the surface, marginal portion in terminal protection district, also can inject a N trap in the marginal portion of terminal, form by ring structure.
Yet in existing terminal protection structure, the size of whole terminal withstand voltage zone is all bigger, and much larger than the thickness of active area epitaxial loayer, this can take many chip areas to its length, has promoted manufacturing cost usually.
Therefore, need a kind of semiconductor power device with new model terminal protection structure.
The utility model content
The purpose of this utility model is to solve the long problem of terminal protection section length because considering for voltage endurance capability to cause in the conventional semiconductor power device, thereby has proposed a kind of semiconductor power device with new model terminal protection structure of innovation.
Semiconductor power device with terminal protection structure of the present utility model; the terminal protection district that includes the source region and arrange around this active area; this terminal protection district has the scribing edge; this active area comprises the substrate layer of first kind conduction type; the well region that is formed at the epitaxial loayer of the first kind conduction type on this substrate layer and is formed at the second class conduction type on this epitaxial loayer; this epitaxial loayer top is coated with oxide layer and metal level; especially; described terminal protection district comprises a groove of filling full insulating material; this groove passes this substrate layer from the bottom of this substrate layer; extend into this epitaxial loayer; and; this groove Width comprise one with equitant first edge, this scribing edge and second edge relative with this first edge, this second edge extends into substrate layer and the epitaxial loayer in this active area.
Preferably, described groove extend into the degree of depth of described epitaxial loayer be the described whole epitaxial loayer degree of depth 10% to 90% between.
Preferably, second edge of the described groove width that extends into substrate layer in this active area and epitaxial loayer be not more than this groove whole width 50%.
Preferably, described insulating material is silicon dioxide or silicon nitride.
Preferably, described semiconductor power device is the power tube of vertical stratification.
Preferably, described semiconductor power device is field effect transistor.
Preferably, described semiconductor power device is igbt.
Preferably, described semiconductor power device is power diode.
Semiconductor power device of the present utility model; owing to be provided with the deep trouth of fill insulant in the terminal protection structure that adopts; electric isolation has been carried out in side and the bottom of semiconductor power device; thereby greatly shortened the length in power device terminal protection district, and improved the voltage endurance capability of power device.
Description of drawings
Fig. 1 is the vertical view of semiconductor power device;
Fig. 2 is the cross-sectional view with semiconductor power device of terminal protection structure of the present utility model;
Fig. 3 is the preparation flow schematic diagram with semiconductor power device of terminal protection structure of the present utility model;
Fig. 4 is the process structure schematic diagram among the step S100 among Fig. 3;
Fig. 5 is the process structure schematic diagram of step S200 and S300 among Fig. 3;
Fig. 6 is the potential profile of semiconductor power device of the present utility model inside.
Embodiment
Below in conjunction with the drawings and specific embodiments, structure, preparation flow and the substantive distinguishing features of semiconductor power device of the present utility model is elaborated.
In general; semiconductor power device of the present utility model; be provided with a groove in the terminal protection district, this groove is offered by the one side (being the bottom surface) at device substrate layer place, and extends to epitaxial loayer; on Width; side and the scribing edge of this groove coincide, and when namely wafer being carried out scribing, pass this groove in the vertical and cut; another side of this groove extends in the active area of semiconductor power device, and fills full insulating material in this groove.Realize the electricity isolation of power device side and bottom thus, thereby need not as prior art that the size in terminal protection district is carried out long design, and this has reduced size of devices, has also promoted voltage endurance capability simultaneously.
Particularly; as shown in Figure 2; semiconductor power device of the present utility model; the terminal protection district that includes the source region and arrange around this active area (only showing the cut-away view of a section side among the figure); routinely, the terminal protection district has a scribing edge 21, after the semiconductor wafer preparation is finished; cut this scribing edge 21 vertically and carried out the scribing processing, formed semiconductor device.And, active area comprises the substrate layer 1 of first kind conduction type, the well region 6 that is formed at the epitaxial loayer 2 of the first kind conduction type on this substrate layer 1 and is formed at the second class conduction type on this epitaxial loayer 2, and these epitaxial loayer 2 tops are coated with oxide layer 4 and metal level 5.For the device that upper surface is the P trap, the substrate layer 1 of this first kind conduction type is the substrate layer of N type, and the epitaxial loayer 2 of this first kind conduction type is the epitaxial loayer of N type, and this well region 6 is the P well region.Understand easily, accordingly, for the device that upper surface is the N trap, the substrate layer 1 of this first kind conduction type is the substrate layer of P type, and the epitaxial loayer 2 of this first kind conduction type is the epitaxial loayer of P type, and this well region 6 is the N well region.
Especially; in semiconductor power device of the present utility model; the terminal protection district comprises a groove 3 of filling full insulating material; this groove 3 passes this substrate layer 1 from the bottom of substrate layer 1; extend into epitaxial loayer 2; and groove 3 comprises that at Width second edge 32, the second edges 32 relative with these 21 equitant first edges 31, scribing edge and this first edge 31 extend into substrate layer 1 and the epitaxial loayer 2 in the active area.
For the size design of groove 3, in the longitudinal direction, preferably, the degree of depth that groove 3 extends into epitaxial loayer 2 be whole epitaxial loayer 2 degree of depth 10% to 90% between.More preferably, the degree of depth that groove 3 extends into epitaxial loayer 2 is 50% ~ 70% of whole epitaxial loayer 2 degree of depth, and for example, the degree of depth that groove 3 extends into epitaxial loayer 2 is about 70% of whole epitaxial loayer 2 degree of depth.On Width, preferably, the width that second edge 32 of groove 3 extends into substrate layer 1 in the active area and epitaxial loayer 2 be not more than groove 3 whole width 50%.For example, one preferred embodiment in, second edge 32 of groove 3 extends into substrate layer 1 in the active area and the width (being W1 among Fig. 2) of epitaxial loayer 2 is 5 microns.
As mentioned above, filling completely has insulating material in groove 3, and this insulating material can be silicon dioxide, silicon nitride or other suitable insulation things.
Semiconductor power device of the present utility model can be the power tube of any vertical stratification.For example, this semiconductor power device can be field effect transistor, igbt, power diode, pliotron etc.
As shown in Figure 3, the schematic flow sheet for preparing for this semiconductor power device.Below, in addition in conjunction with Fig. 1, Fig. 4 and Fig. 5, the preparation flow of semiconductor power device of the present utility model is elaborated.
In conjunction with Fig. 4, in step S100, at first be formed with the source region in chip front side, and the maintenance certain distance L between the adjacent active area, this distance is preferably at least 70 microns.Be the terminal protection district of two adjacent devices in the zone of L length.The technology that is formed with the source region can adopt common process, to finish the generation of P trap or N trap 6, oxide layer 4 and metal level 5.
In conjunction with Fig. 5, in step S200, spin upside down chip, after the reduction processing, from silicon chip between two active areas of chip over against back side excavation groove 3, understand easily, adjacent two power device internal channel width that the width of this groove 3 forms for the section back and.This width is preferably from 70 microns to the 150%L, and on Width, the left and right sides of groove 3 all should extend into substrate layer and the epitaxial loayer of active area, on depth direction, groove 3 should extend in the epitaxial loayer, as mentioned above, groove 3 extend into the degree of depth of epitaxial loayer be whole epitaxial loayer 2 degree of depth 10% to 90% between.
Continuation is in conjunction with Fig. 5, in step S300, and fill insulant in groove 3.As mentioned above, this insulating material can be silica, silicon nitride or other suitable insulation things.
At last, in step S400, chip is carried out slicing treatment, form the final devices structure.In conjunction with Fig. 5, when carrying out slicing treatment, preferably cut into slices at the center position of groove 3.Certainly, consider error component, also can depart from the center position certain distance of groove 3, cut into slices.After step S400 finishes, the final device architecture that forms as shown in Figure 2.
As shown in Figure 6, be potential profile at device inside of the present utility model.Wherein S is the equipotential line.As can be seen from the figure, because the utility model has adopted the terminal protection structure of innovation, the electromotive force of its side is no longer identical with bottom potential, but more near the surface, electromotive force is more low.This shows that the utility model successfully realized the electric isolation of side and bottom, and need as existing terminal protection structure need not a very wide lateral separation.
In sum, semiconductor power device of the present utility model, utilized the electric buffer action of insulating barrier, namely by introducing the groove structure of filling megohmite insulant, make side and the bottom of device be opened by electric isolation, thereby when satisfying the device withstand voltage requirement, reduced the area of chip terminal withstand voltage zone.
Claims (8)
1. semiconductor power device with terminal protection structure; the terminal protection district that includes the source region and arrange around this active area; this terminal protection district has the scribing edge; this active area comprises the substrate layer of first kind conduction type, the well region that is formed at the epitaxial loayer of the first kind conduction type on this substrate layer and is formed at the second class conduction type on this epitaxial loayer; this epitaxial loayer top is coated with oxide layer and metal level; it is characterized in that
Described terminal protection district comprises a groove of filling full insulating material; this groove passes this substrate layer from the bottom of this substrate layer; extend into this epitaxial loayer; and; this groove Width comprise one with equitant first edge, this scribing edge and second edge relative with this first edge, this second edge extends into substrate layer and the epitaxial loayer in this active area.
2. the semiconductor power device with terminal protection structure according to claim 1 is characterized in that, the degree of depth that described groove extends into described epitaxial loayer be the described whole epitaxial loayer degree of depth 10% to 90% between.
3. the semiconductor power device with terminal protection structure according to claim 1 and 2 is characterized in that, the width that second edge of described groove extends into substrate layer in this active area and epitaxial loayer be not more than this groove whole width 50%.
4. the semiconductor power device with terminal protection structure according to claim 1 is characterized in that, described insulating material is silicon dioxide or silicon nitride.
5. the semiconductor power device with terminal protection structure according to claim 1 is characterized in that, described semiconductor power device is the power tube of vertical stratification.
6. the semiconductor power device with terminal protection structure according to claim 5 is characterized in that, described semiconductor power device is field effect transistor.
7. the semiconductor power device with terminal protection structure according to claim 5 is characterized in that, described semiconductor power device is igbt.
8. the semiconductor power device with terminal protection structure according to claim 5 is characterized in that, described semiconductor power device is power diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220741947 CN203038926U (en) | 2012-12-28 | 2012-12-28 | Semiconductor power device possessing terminal protection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220741947 CN203038926U (en) | 2012-12-28 | 2012-12-28 | Semiconductor power device possessing terminal protection structure |
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| Publication Number | Publication Date |
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| CN203038926U true CN203038926U (en) | 2013-07-03 |
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| CN 201220741947 Withdrawn - After Issue CN203038926U (en) | 2012-12-28 | 2012-12-28 | Semiconductor power device possessing terminal protection structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066104A (en) * | 2012-12-28 | 2013-04-24 | 上海贝岭股份有限公司 | Semiconductor power device with terminal protection structure |
| CN103617954A (en) * | 2013-11-27 | 2014-03-05 | 上海联星电子有限公司 | Method for manufacturing Trench-RB-IGBT |
-
2012
- 2012-12-28 CN CN 201220741947 patent/CN203038926U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066104A (en) * | 2012-12-28 | 2013-04-24 | 上海贝岭股份有限公司 | Semiconductor power device with terminal protection structure |
| CN103066104B (en) * | 2012-12-28 | 2015-11-18 | 上海贝岭股份有限公司 | There is the semiconductor power device of terminal protection structure |
| CN103617954A (en) * | 2013-11-27 | 2014-03-05 | 上海联星电子有限公司 | Method for manufacturing Trench-RB-IGBT |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20130703 Effective date of abandoning: 20151118 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |