CN202975960U - Low level reset circuit of system provided with multiple reset sources corresponding to multiple processors - Google Patents

Abstract

The utility model relates to a low level reset circuit of a system provided with multiple reset sources corresponding to multiple processors; the low level reset circuit is characterized by comprising N reset sources and a gate circuit which have the connection relationship that the N reset sources are respectively connected with N input ends of the gate circuit; an output end of the gate circuit is respectively connected with reset ports of N processers; the reset ports of the processors are respectively and externally connected with a divider resistor matched with a reset level; and the N processors are connected with one another by a plurality of communication lines. Therefore, the low level reset circuit has good circuit stability and layout flexibility as well as very strong applicability and practicality; the problems that the reset signals are disordered and the processors to be reset can not act since the plurality of rest sources are used for acting in a mixed way can be completely avoided; and the reliability of power-on reset, programming reset and program watchdog reset of the system can be improved to the utmost extent.

Description

The low-level reset circuit of a kind of many reset source to multicomputer system

Technical field

The present invention relates to a kind of many reset source to the low-level reset circuit of multicomputer system, belong to the circuit field of multiprocessor, many reset source immixture.

Background technology

In the practical application of existing industry control electron trade, for running into two or more reset source immixtures when the processor in reset circuit, the time of sending reset signal due to a plurality of reset source is not the same, make the high-low level on synchronization processor reset pin to clash, thereby cause the reset level state uncertain and can't realize the purpose of processor reset.In this case, generally can adopt in reset source and treat that the mode of series resistor between the resetting processor corresponding pin solves this level conflict, when the output terminal of one of them reset source is high level like this, the another one reset source can play the effect that resets to processor.If in the situation that such circuit is constant, after the reset source transposition, original reset source has just no longer played the effect that resets but simultaneously.If adopt this moment in reset source and the method for the treatment of series resistor between the corresponding pin of resetting processor, result can make again the level value of reset signal be in the nondeterministic statement of discussion at the beginning again, and reset source has entered again failure state like this.If using special-purpose connect chip processes, can improve the cost of design on the one hand, on the other hand in PCB layout because the integrated of chip brings zonal inconvenience to wiring, and in circuit model of the present invention, the ingredient of AND circuit can be placed on the PCB optional position, has greatly improved the dirigibility of PCB layout.

Existing reset circuit form only has single reset source to act on simultaneously single or multiple processors, and will cause all reset source to lose efficacy or only have an effective phenomenon of reset source for form and the treating method thereof of many reset source immixture.

Summary of the invention

The technical matters that solves

For fear of the deficiencies in the prior art part, the present invention proposes a kind of many reset source to the low-level reset circuit of multicomputer system, solves the problem that reset source that a plurality of reset source immixtures cause in one or more processors lost efficacy.

Technical scheme

The low-level reset circuit of a kind of many reset source to multicomputer system is characterized in that comprising N reset source and AND circuit; Annexation is: N reset source is connected with N input end of AND circuit; The output terminal of AND circuit is connected with N processor reseting port separately, and the external divider resistance that mates with reset level of the reseting port of each processor; Some order wire interconnection are arranged between N processor.

The ripple voltage when breakdown reverse voltage of the diode in described AND circuit is exported high level greater than the reset source of connection corresponding to it.

The withstand voltage of the magnitude of voltage during described AND circuit output high level and the reseting port of back-end processor is complementary.

The selection of described divider resistance satisfies condition:

Wherein, V _CPUiThe withstand voltage that represents i processor port, V _ANDOExpression and gate output terminal magnitude of voltage, R _iI the divider resistance that the processor port connects, i=1,2 ... N.

Beneficial effect

The low-level reset circuit of a kind of many reset source that the present invention proposes to multicomputer system, the pin of the transmission reset signal of reset source is connected to the input end of AND circuit, the negative pole that namely forms the diode of AND circuit, the break-make of respective diode in the control AND circuit.The output terminal of AND circuit is connected on the reset pin of each processor to be resetted, and its effect is to send reset signal to each processor.When reset source has reset signal to send, be the characteristic of low level and AND circuit due to reset signal, the low level reset signal will by with door and by being sent to processor to be resetted with door, make processor reset.

So the present invention has good circuit stability and layout dirigibility, has simultaneously very strong applicability and practicality; Stop the reset signal disorder that causes because of a plurality of reset source immixtures fully and treat the problem that resetting processor can't move; Improved to greatest extent system power-on reset, programming resets and the reliability of program watchdog reset.

Description of drawings

Fig. 1 is the schematic diagram of circuit model in example of the present invention:

In Fig. 1, reset source represents to send circuit or processor or other any one processing units of reset signal; D ₁~ D _NFor forming the diode of AND circuit; Processor 1～N is deal with data and need the processing unit of reset function in system; Withstand voltage when high level represents normal operation on the reset pin of back-end processor.

Embodiment

Now in conjunction with the embodiments, the invention will be further described for accompanying drawing:

In the present embodiment: N reset source is connected with N input end of AND circuit; The output terminal of AND circuit is connected with N processor reseting port separately, and the external divider resistance that mates with reset level of the reseting port of each processor; Some order wire interconnection are arranged between N processor.

The main points that this circuit connects:

1, for all diodes of all reset source in native system, AND circuit, all processors of rear end, when all reset source have some or all of all when carrying out above step, effect due to AND circuit, result only has the low level reset signal can be by with door and act on the processor of rear end, the state that makes processor reach to reset.

2, when selecting diode component, the ripple voltage when should be noted that the reset source output high level of the size of breakdown reverse voltage of diode and connections corresponding to it needs the assurance diode can not breakdownly cause the path damage.

3, the magnitude of voltage during AND circuit output high level also needs to be complementary with the withstand voltage of the reseting port of back-end processor; Because the withstand voltage of a plurality of processor ports of system is not quite similar, some withstand voltages are high, some withstand voltages are low, not damaged in order to guarantee the processor port, need to coordinate processor port withstand voltage to choose with the gate output terminal high level, and the filtering of the pulse voltage that may comprise in this high level will being tried one's best is clean.

4, in order to process above the 3rd described Noticed Problems, and guarantee that processor can misoperation, high level with gate output terminal can be chosen for the highest level value of withstand voltage in all processors, and then add that in withstand voltage low processor port a resistance carries out dividing potential drop, make the level value of this processor port of input meet the demands.Concrete resistance value must be chosen and should satisfy formula:

$V_{\mathrm{CPUi}}=\frac{R_i}{R+R_i}\×V_{\mathrm{ANDO}}$

Wherein, V _CPUiThe withstand voltage that represents i processor port, V _ANDOExpression and gate output terminal magnitude of voltage, R _iI the divider resistance that the processor port connects, i=1,2 ... N.

5, send about each reset source the time that reset signal continues, due to all processors that need to reset of the reset signal with gate output terminal output, need that the longest processor reset of reset signal time in all processors so the duration of the reset signal that each reset source is sent must guarantee to make, such reset signal is only effective reset signal.

For reset source 1～N, with gate diode D ₁~ D _NAnd treat resetting processor 1～N, according to the time sequencing of the problem of processing, the present invention program can be divided into following step:

Step 1

Reset source 1 is sent the low level reset signal, and this reset signal acts on the diode D of AND circuit ₁, reset signal and D ₁Anodal high level acting in conjunction makes D ₁Produce pressure drop between both positive and negative polarity.

Step 2

D in step 1 ₁The both positive and negative polarity pressure drop makes diode D ₁Conducting causes D ₁Positive pole be pulled to low level, output reset signal, this reset signal acts on the processor of rear end.

Step 3

For the processor of rear end, after it receives the reset signal that the front end AND circuit sends, can produce homing action, make the duty of processor get back to the initial reset state.

In table 1, the importation represents the part that reset source is connected with diode, is also the place that reset source sends reset signal; Output expression diode is also the output terminal of AND circuit, transmits a signal to the reset pin of each processor; In table 1 expression reset source is not sent reset signal, and it is high level that this reset source reset signal sends pin, and 0 expression reset source has been sent reset signal, and it is low level that this reset source reset signal sends pin.

Table 1

Annotate: 0 expression low level in upper table, 1 expression high level.

Claims (4)

1. the low-level reset circuit of reset source more than a kind to multicomputer system, is characterized in that comprising N reset source and AND circuit; Annexation is: N reset source is connected with N input end of AND circuit; The output terminal of AND circuit is connected with N processor reseting port separately, and the external divider resistance that mates with reset level of the reseting port of each processor; Some order wire interconnection are arranged between N processor.

2. the low-level reset circuit of many reset source to multicomputer system according to claim 1 is characterized in that: the ripple voltage of the breakdown reverse voltage of the diode in described AND circuit during greater than the reset source output high level of connection corresponding to it.

3. the low-level reset circuit of many reset source to multicomputer system according to claim 1, it is characterized in that: the withstand voltage of the magnitude of voltage during described AND circuit output high level and the reseting port of back-end processor is complementary.

4. the low-level reset circuit of many reset source to multicomputer system according to claim 1, it is characterized in that: the selection of described divider resistance satisfies condition:

Wherein, V _CPUiThe withstand voltage that represents i processor port, V _ANDOExpression and gate output terminal magnitude of voltage, R _iI the divider resistance that the processor port connects, i=1,2 ... N.