CN202872422U - Charging system and digital interface circuit thereof - Google Patents
Charging system and digital interface circuit thereof Download PDFInfo
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- CN202872422U CN202872422U CN 201220558332 CN201220558332U CN202872422U CN 202872422 U CN202872422 U CN 202872422U CN 201220558332 CN201220558332 CN 201220558332 CN 201220558332 U CN201220558332 U CN 201220558332U CN 202872422 U CN202872422 U CN 202872422U
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Abstract
The utility model discloses a charging system and digital interface circuit thereof. In one embodiment, the charging system includes an ac-dc converter circuit, a load, a battery, a system management bus host, a control circuit, a first switch, and a second switch. The control circuit comprises a digital interface circuit, wherein the digital interface circuit comprises a control register which is an N-bit register. The N-bit register comprises a master state machine which is positioned at the first part of bits and indicates the working state of the system management bus host, and a slave state machine which is positioned at the second part of bits and indicates the data transmission bit number of the control instruction of the system management bus host. The utility model discloses a charging system and digital interface circuit thereof has reduced the quantity of control register among the digital interface circuit, and the cost is reduced has improved the integrated level.
Description
Technical field
The utility model relates to battery charging field, and is concrete but be not limited to relate to the system and method that a kind of use intelligent battery management bus (SMBus) carries out digital control battery charging.
Background technology
The function that electronic equipment possesses is more, performance is higher, and its structure, technology, system are just more complicated.In Intelligent battery management system, interface circuit often adopts two kinds of methods.A kind of is to build traditional analog circuit as interface circuit, but traditional analogue technique power management is difficult to satisfy the demand of the complexity that the power management intellectuality brings, and price is also very expensive simultaneously.Another kind method is to adopt the digital code programming to realize digital control, and digital interface circuit is simple and be easy to expansion, is the development trend of present intelligent power supply management domain, has quick response, high integrated and high controlled huge advantage.
In digital control Intelligent battery management system; usually can use System Management Bus (SMBus) that power supply is controlled; wherein, digital interface circuit is positioned at the control circuit front end, is used for receiving and transmitting from System Management Bus SMBus the relevant information signal of battery.Yet, when adopting the digital code programming, in digital interface circuit, usually comprise a plurality of registers, such as control register, buffer register, data storage register etc. etc.Wherein, the control of state machine in the control register, coordinate other registers and finish transmission course, for example determine intelligent charge state number, and determine data bits corresponding to each state.
Figure 1 shows that the control register schematic diagram of digital interface circuit in the prior art.As shown in Figure 1, digital interface circuit 110 is positioned at control circuit 100 front ends, comprises register 111 and register 112.Wherein register 111 is the transmission state register, comprises first state machine, is used for determining System Management Bus SMBus transmission state number.Register 112 is the Count of Status register, comprises second state machine, be used for determining under each transmission state, and the figure place of corresponding control command transfer of data, synchronous with a clock line SCL of external smart battery management system.Transmission state register 111 and Count of Status register 112 be the composition control register together, to the instruction bus 113 output control signals of control circuit 110.The quantity of register is too much, and meeting and is unfavorable for integrated so that circuit cost increases.
The utility model content
For one or more problems of the prior art, the utility model provides electric power system and the digital interface circuit thereof that contains intelligent electric power management.
Aspect one of the present utility model, a kind of charging system has been proposed, comprise power circuit, load, battery, the System Management Bus main frame, control circuit, the first switch, second switch, it is characterized in that described control circuit comprises a digital interface circuit, described digital interface circuit comprises a control register, and wherein said control register is a N bit register, comprise host state machine, be positioned at the first position of described control register, be used to indicate System Management Bus host work state, wherein N is the positive integer more than or equal to 2; From state machine, be positioned at the second portion position of described control register, be used to indicate under each operating state of System Management Bus main frame the figure place of corresponding control command transfer of data.
In one embodiment, described first position be described N bit register first to the M position, described second portion position be the M+1 position of described N bit register to the N position, wherein M is positive integer, M＜N, wherein N is the positive integer more than or equal to 3.
In one embodiment, described first position is the odd bits of described N bit register, and described second portion position is the even bit of described N bit register.
In one embodiment, described first position be described N bit register first to the K position, described second portion position be the M position of described N bit register to the N position, K wherein, M is positive integer, K＞M, wherein N is the positive integer more than or equal to 3.
In one embodiment, described charging system also comprises a clock lines and a data wire, described power circuit links to each other with an end of described the first switch, the other end of described the first switch links to each other with an end and the described load of described second switch, the other end of described second switch links to each other with described battery, the other end of described battery links to each other with described System Management Bus main frame with described clock line by described data wire, described System Management Bus main frame is further exported the battery information signal to described control circuit by described data wire and described clock line, and described control circuit outputs control signals to described the first switch and described second switch;
Described digital interface circuit also comprises control bus, data register and data/address bus, wherein said control register receives the information of described clock line, export according to described host state machine and the described control command of determining from state machine to described control bus, described control bus further couples described data/address bus, described data register is by described data/address bus, according to control command and described data wire swap data, and determine the state that turns on and off of described the first switch and described second switch; And
Described control register further comprises enable register and startup-stop detected register.
In one embodiment, described charging system is characterised in that wherein M equals 3, N and equals 7
On the other hand of the present utility model, a kind of digital interface circuit has been proposed, comprise a control register, it is characterized in that, described control register is a N bit register, comprises host state machine, is positioned at the first position of described control register, be used to indicate the operating state of a System Management Bus main frame, wherein N is the positive integer more than or equal to 2; From state machine, be positioned at the second portion position of described control register, be used to indicate corresponding control command data transfer figure place under each operating state of described System Management Bus main frame.
Utilize the utility model embodiment, reduced in the digital interface circuit, the quantity of control register has reduced cost, has improved integrated level.
Description of drawings
Following accompanying drawing relates to the description of the embodiment of the non-limiting and non exhaustive property of relevant the utility model.Except as otherwise noted, otherwise same numbers and symbols TYP or similar part in whole accompanying drawing.Accompanying drawing need not to draw in proportion.In addition, the size of relevant portion shown in the figure may be different from the size of narrating in the specification.For understanding better the utility model, following details is described and accompanying drawing will be provided to as a reference.
Figure 1 shows that the control register schematic diagram of digital interface circuit in the prior art;
Figure 2 shows that and adopt the circuit module schematic diagram of the charging system 200 of intelligent battery management bus according to an embodiment of the present utility model;
Figure 3 shows that according to digital interface circuit 251 schematic diagrames in the utility model one specific embodiment;
Figure 4 shows that according to host state machine in the utility model one implementation with from the state machine working state schematic representation.
Embodiment
The below will describe specific embodiment of the utility model in detail, should be noted that the embodiments described herein only is used for illustrating, and be not limited to the utility model.In the following description, in order to provide thorough understanding of the present utility model, a large amount of specific detail have been set forth.Yet, it is evident that for those of ordinary skills: needn't adopt these specific detail to carry out the utility model.In other examples, for fear of obscuring the utility model, do not specifically describe known circuit, material or method.
Figure 2 shows that and adopt the circuit module schematic diagram of the charging system 200 of intelligent battery management bus according to an embodiment of the present utility model.Charging system 200 comprises power circuit 210, load 220, battery 230, System Management Bus main frame SMBus240, control circuit 250, current path switch S 1 and S2.Wherein, control circuit 250 comprises digital interface circuit 251, is positioned at control circuit 250 front ends.Charging system 200 also comprises data wire SDA and clock line SCL.Power circuit 210 links to each other with an end of switch S 1, the other end of switch S 1 links to each other with an end and the load 220 of switch S 2, the other end of switch S 2 links to each other with battery 230, the other end of battery links to each other with System Management Bus SMBus main frame 240 with clock line SCL by data wire SDA, System Management Bus SMBus is arranged in System Management Bus main frame 240, export the battery information signal to control circuit 250 by data wire SDA and clock link SCL, the turn-on and turn-off of control circuit 250 output control signal control switch S1 and switch S 2.
When switch S 1 and S2 conducting, input voltage gives load 220 power supplies through power circuit 210, gives simultaneously battery 230 chargings, when switch S 1 disconnection, and during the S2 conducting, the battery powering load.Control circuit 250 receives the battery information signal from System Management Bus SMBus main frame 240, the turn-on and turn-off of control switch S1 and switch S 2 by digital interface circuit 251.According to System Management Bus SMBus read-write protocol, when data wire SDA is in by the high transitional states to logic low of logic, simultaneously clock line SCL is in logic when high, System Management Bus SMBus main frame takies bus, after System Management Bus SMBus main frame is finished transfer of data, data wire SDA is that logic is high by the logic low saltus step, and clock line SCL also is in logic when high, and bus discharges.Except beginning to connect and finish connection status, only when clock line SCL was logic low, data wire SDA just can change other states.
Having average technical staff in this area can understand, and in other embodiment of the present utility model, except switch S1 and S2, also may comprise one or more other current path switches.
Figure 3 shows that according to digital interface circuit 251 schematic diagrames in the utility model one specific embodiment.As shown in Figure 3, digital interface circuit 251 comprises a control register 252, and in one embodiment, control register 252 is a N bit register, comprises two state machines: host state machine 2521 and from state machine 2522.N be one more than or equal to 2 positive integer.Host state machine 2521 is positioned at the first position of control register 252, is positioned at the second portion position of control register 252 from state machine 2522.In one embodiment, above-mentioned first position be first of control register 252 to the M position, above-mentioned second portion position be the M+1 position of control register to the N position, wherein M is positive integer, M＜N, wherein N is the positive integer more than or equal to 3.Host state machine 2521 indication mechanism management bus SMBus host work states, in one embodiment, the operating state of System Management Bus SMBus main frame comprises open state, read states, writes state, off-mode etc.Indicate under each operating state from state machine 2522, the figure place of corresponding control command transfer of data, SCL is synchronous with clock line.For example, System Management Bus SMBus host work has 2
3Individual state, then host state machine 2521 is the triad counter, M=3 in control register 252 is arranged in the front three of control register 252; Be the tetrad counter from state machine 2522, be arranged in the 4th to the 7th of control register 252, so supreme command the transmission of data figure place corresponding to each state of System Management Bus SMBus main frame be 2
4-1.
Those skilled in the art are appreciated that may there be the arrangement mode that is different from above-described embodiment the above-mentioned first position and the second portion position that are arranged in control register 252.For example, in one embodiment, the first position is the odd bits of control register 252, and the second portion position is the even bit of control register 252.In another embodiment, the first position be first of control register 252 to the K position, the second portion position is N position, M position to the, K wherein, M is positive integer, K＞M, wherein N is the positive integer more than or equal to 3, i.e. be main state machine and share from state machine of the part of control register.
Those skilled in the art are appreciated that in other embodiments except control register 252, digital interface circuit 251 also may comprise control bus 253, data register 254 and data/address bus 255.Control register 252 is couple to clock line SCL, the information of receive clock line SCL, simultaneously control register 252 is couple to control bus 253, and control bus 253 outputs in the control circuit 250 are according to host state machine 2521 and the control command determined from state machine 2522.Control bus 250 also further couples data/address bus 255 so that control command control data register 254 passes through data/address bus 255, with data wire SDA swap data, and determine switch S1, the state that turns on and off of S2.In certain embodiments, the data register 254 in the charging system 200 may comprise the register of a plurality of types, for example the address date register, the charging voltage data register, charging current data register, input current data register, input buffer, output buffer etc.
Those skilled in the art it is also understood that, in other embodiments, control register 252 may comprise two or more registers, for example, comprise host state machine and from the N bit register of state machine except mentioned above, control register 252 also may comprise enable register, starts-stop detected register, etc.
Compare with prior art digital interface circuit shown in Figure 1, in one embodiment, but the control work of a N bit register of 252 need of control register shown in Figure 3 completion system management bus SMBus main frame, in this control register 252, comprise two state machines, be host state machine 2521 and from state machine 2522, determine respectively the figure place of the director data transmission that System Management Bus SMBus host work state and each state of System Management Bus SMBus main frame are corresponding.
Figure 4 shows that according to master slave mode machine working state schematic representation in the utility model one implementation.In the embodiment shown in fig. 4, control register comprises host state machine 410 and from state machine 420, wherein the indication code of the host state machine operating state of correspondence system management bus order successively from small to large.In one embodiment, System Management Bus SMBus main frame has eight operating states, and during normal operation, these eight operating states are followed successively by: spare bits, start slave, order, write a high position, write low level, restart slave, read a high position, read low level etc.Therefore, the host state machine of indication mechanism management bus SMBus host work state is a triad number state machine (M=3), represents idle condition, starts slave status, represents coomand mode, writes high-end trim, writes low-end trim, restarts slave status, reads high-end trim, reads low-end trim with binary number 111 representatives with binary number 110 representatives with binary number 101 representatives with binary number 100 representatives with binary number 011 representative with binary number 010 with binary number 001 representative with binary number 000 respectively.In the embodiment shown in fig. 4, synchronous with clock line SCL from state machine 420, the data bits that needs serial transmission is the eight-digit binary number logarithmic data, therefore, needing the tetrad code to represent the data bits of serial transmission, is the tetrad state machine from state machine 420.Corresponding control command data transfer figure place equals the binary number code from state machine 420 under each operating state of System Management Bus SMBus main frame, namely take binary number 1000 expression System Management Bus SMBus main frame transmitted data bits as eight, represent that take binary number 0111 transmitted data bits of System Management Bus SMBus main frame is as seven, by that analogy.Those skilled in the art are appreciated that in other embodiments in this area, use tetrad can represent 2 from state machine is the highest
4-1 System Management Bus SMBus main frame transmitted data bits.Therefore in the embodiment shown in fig. 4, control register amounts to seven to the binary number of control bus transmission, the operating state of front three indication mechanism management bus SMBus main frame wherein, the data bitss of rear four indication serial transmissions.
Need to prove that especially embodiment illustrated in fig. 4 only is specific embodiment of the utility model, host state machine 410 and can be according to system's needs arbitrary extension from the number of bits of state machine 420.For example, in one embodiment, control register need to increase error-detecting and addressing function, and then host state machine 410 needs to increase by two states, so that host state machine 410 number of bits become four by three.For example, represent idle condition, start slave status, represent coomand mode, write high-end trim, write low-end trim, restart slave status, read high-end trim, read low-end trim, detect with binary number 1000 Representative errors with binary number 0111 representative with binary number 0110 representative with binary number 0101 representative with binary number 0100 representative with binary number 0011 representative with binary number 0010 with binary number 0001 representative with binary number 0000 respectively, represent addressing with binary number 1001.The tetrad host state machine can represent 2 at most
4Individual state.In one embodiment, need serial transmission sixteen bit binary data, then need to expand to five bit state machines from state machine, take binary number 10000 expression System Management Bus SMBus main frame the transmission of datas as the sixteen bit binary data, represent that take binary number 01111 transmitted data bits of System Management Bus SMBus main frame is as 15, by that analogy.Five bits can represent 2 from state machine is the highest
5-1 System Management Bus SMBus main frame transmitted data bits.Other situations that need to expand the like.
What need statement is that above-mentioned utility model content and embodiment are intended to prove the practical application of technical scheme that the utility model provides, and should not be construed as the restriction to the utility model protection range.Those skilled in the art are in spirit of the present utility model and principle, when doing various modifications, being equal to and replacing or improve.Protection range of the present utility model is as the criterion with appended claims.
Claims (7)
1. charging system, comprise power circuit, load, battery, System Management Bus main frame, control circuit, the first switch and second switch, it is characterized in that described control circuit comprises a digital interface circuit, described digital interface circuit comprises a control register, wherein said control register is a N bit register, N is the integer more than or equal to 2, and described N bit register comprises:
Host state machine is positioned at the first position of described control register, is used to indicate the operating state of described System Management Bus main frame; With
From state machine, be positioned at the second portion position of described control register, be used to indicate the figure place of control command transfer of data corresponding under each operating state of described System Management Bus main frame.
2. charging system as claimed in claim 1 is characterized in that, wherein said first position be described N bit register first to the M position, described second portion position is that the M+1 position of described N bit register is to the N position, wherein M is positive integer, M＜N, and wherein N is the positive integer more than or equal to 3.
3. charging system as claimed in claim 1 is characterized in that, wherein said first position is the odd bits of described N bit register, and described second portion position is the even bit of described N bit register.
4. charging system as claimed in claim 1 is characterized in that, wherein said first position be described N bit register first to the K position, described second portion position be the M position of described N bit register to the N position, K wherein, M is positive integer, K＞M, wherein N is the positive integer more than or equal to 3.
5. charging system as claimed in claim 1, it is characterized in that, wherein said charging system also comprises a clock lines and a data wire, described power circuit links to each other with an end of described the first switch, the other end of described the first switch links to each other with an end and the described load of described second switch, the other end of described second switch links to each other with described battery, the other end of described battery links to each other with described System Management Bus main frame with described clock line by described data wire, described System Management Bus main frame is further exported the battery information signal to described control circuit by described data wire and described clock line, and described control circuit outputs control signals to described the first switch and described second switch;
Described digital interface circuit also comprises control bus, data register and data/address bus, wherein said control register receives the information of described clock line, export according to described host state machine and the described control command of determining from state machine to described control bus, described control bus further couples described data/address bus, described data register is by described data/address bus, according to control command and described data wire swap data, and determine the state that turns on and off of described the first switch and described second switch; And
Described control register further comprises enable register and startup-stop detected register.
6. charging system as claimed in claim 2 is characterized in that, wherein M equals 3, N and equals 7.
7. a digital interface circuit that is used for the charging system management comprises a control register, it is characterized in that described control register is a N bit register, and N is the positive integer more than or equal to 2, and described N bit register comprises:
Host state machine is positioned at the first position of described control register, is used to indicate the operating state of a System Management Bus main frame; With
From state machine, be positioned at the second portion position of described control register, be used to indicate corresponding control command data transfer figure place under each operating state of described System Management Bus main frame.
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| CN 201220558332 CN202872422U (en) | 2012-10-29 | 2012-10-29 | Charging system and digital interface circuit thereof |
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| CN 201220558332 CN202872422U (en) | 2012-10-29 | 2012-10-29 | Charging system and digital interface circuit thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102882261A (en) * | 2012-10-29 | 2013-01-16 | 成都芯源系统有限公司 | charging system, digital interface circuit and control method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102882261A (en) * | 2012-10-29 | 2013-01-16 | 成都芯源系统有限公司 | charging system, digital interface circuit and control method thereof |
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