CN202816957U - Thin film transistor, array substrate and display device - Google Patents
Thin film transistor, array substrate and display device Download PDFInfo
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- CN202816957U CN202816957U CN 201220519148 CN201220519148U CN202816957U CN 202816957 U CN202816957 U CN 202816957U CN 201220519148 CN201220519148 CN 201220519148 CN 201220519148 U CN201220519148 U CN 201220519148U CN 202816957 U CN202816957 U CN 202816957U
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Abstract
The utility model discloses a thin film transistor, an array substrate and a display device in order to increase the width of the conducting channel of the thin film transistor on the basis of unchanged source electrode capacitance, enhance the performances of the thin film transistor and improve image qualities. The thin film transistor comprises a substrate; a gate electrode, a source electrode, at least two drain electrodes and a semiconductor layer formed on the substrate; a gate electrode protective layer formed on the substrate and located between the gate electrode and the semiconductor layer; and an etching resistant layer formed on the substrate and located among the semiconductor layer, the source electrode and the drain electrodes. The source electrode and the drain electrodes are connected with the semiconductor layer respectively via through holes.
Description
Technical field
The utility model relates to the Display Technique field, relates in particular to a kind of thin-film transistor, array base palte and display unit.
Background technology
In the Display Technique field, panel display apparatus, such as liquid crystal display (Liquid Crystal Display, LCD) and display of organic electroluminescence (Organic Light Emitting Display, OLED), because it is light, thin, low-power consumption, high brightness, and the advantage such as high image quality, consequence occupied in the flat panel display field.
Wherein, the characteristic as the thin-film transistor (Thin Film Transistor, TFT) of pixel switch device plays an important role to the high image quality display unit.
TFT is summarized as follows as the operation principle of switching device: as the voltage V that applies for the gate electrode of TFT with respect to ground GND
gWhen (abbreviation gate electrode voltage), the gate electrode of TFT and with drain electrode that data wire links to each other between can produce an electric field, the electron channel that TFT forms under the effect of this electric field makes the source electrode that links to each other with pixel electrode and described drain electrode by the semiconductor layer conducting of TFT, and the forward voltage between gate electrode and the source electrode is poor (also to be threshold voltage V
Th) larger, conducting channel is wider, and On current is also larger, and is also stronger to the charging ability of pixel electrode; When the negative voltage that applies for the gate electrode of TFT with respect to ground GND, source electrode and drain electrode are closed, the switching characteristic of Here it is TFT.Charging ability to pixel electrode is higher, can be so that pixel electrode thoroughly discharge and recharge, thus improve image quality.
This shows that the semiconductor layer electron mobility of TFT is higher, conducting channel is wider, and On current is also larger.
At present, use metal oxide obviously can improve the On current of TFT as the TFT semiconductor layer, this is because the electron mobility of metal oxide semiconductor layer is 5 ~ 10 times of electron mobility of amorphous silicon semiconductor layer.Behind the material decision of semiconductor layer, the electric conductivity of TFT (mainly instructing galvanization here) depends on the structure of TFT.
Referring to Fig. 1, for existing TFT schematic top plan view, comprising: source electrode 15, drain electrode 16, gate electrode 11, the scan line 17 that links to each other with gate electrode 11 and the data wire 18 that links to each other with drain electrode 16.
Wherein, the quantity of the source electrode 15 on the TFT and drain electrode 16 respectively is one.
When the TFT conducting, On current flows to source electrode 15 by drain electrode 16 by conducting channel, distance between drain electrode 16 and the source electrode 15 determines the length of raceway groove, drain electrode 16 determines that with the size of source electrode 15 width of conducting channel is (in pixel TFT, because the diameter of drain electrode and source electrode is generally in several micron dimensions, the pattern of source electrode and drain electrode is generally the circle with certain diameter, can equivalence be the square with certain length of side also, in order to improve the performance of TFT, increase the width of conducting channel, can realize by the area of increase source electrode and drain electrode, but can there be following problems in the area that increases the source electrode:
The area of source electrode and drain electrode increases, and the area of shared subpixel area also becomes greatly, and the source electrode is to link to each other with the pixel electrode of TFT, especially when the source electrode area is larger, may cause the aperture opening ratio of TFT to descend.The more important thing is that when the area of source electrode was larger, it is large that the electric capacity between source electrode and the semiconductor layer becomes, in the situation of the voltage jump of pixel electrode, can cause the colour cast (colour cast namely has deviation for each pixel Show Color and theoretical color) that shows image.
Existing thin-film transistor TFT is guaranteeing that conducting channel is less under the less source electrode capacitance, and the TFT On current is less, and the TFT performance is lower.
The utility model content
The utility model embodiment provides a kind of thin-film transistor, array base palte and display unit, in order to improve the performance of TFT, improves the image quality of image.
For achieving the above object, the thin-film transistor that the utility model embodiment provides comprises:
Substrate;
Be formed on gate electrode on the substrate, source electrode, at least two drain electrodes and semiconductor layer;
Be formed on the gate electrode protective layer between described gate electrode and semiconductor layer on the described substrate, be formed on the etching barrier layer between described semiconductor layer and source electrode and drain electrode on the described substrate; Wherein, described source electrode links to each other with described semiconductor layer by via hole respectively with described drain electrode.
The array base palte that the utility model embodiment provides comprises described thin-film transistor.
The display unit that the utility model embodiment provides comprises described array base palte.
The thin-film transistor TFT that the utility model embodiment provides, each TFT forms a source electrode and at least two drain electrodes, each drain electrode links to each other with semiconductor layer by via hole, form conducting channel between source electrode and the drain electrode, thin-film transistor described in the utility model, more than one of the conducting channel that each TFT forms has increased the effective width of conducting channel, increase the On current of TFT semiconductor layer, improved the performance of TFT.And when On current increased, because drain electrode shares a source electrode, the area of source electrode did not increase with respect to the design of existing TFT, and the electric capacity of source electrode does not increase yet, and the image of whole display unit shows that image quality is improved.
Description of drawings
Fig. 1 is the TFT part-structure schematic top plan view that prior art has a drain electrode;
The array base palte overall structure schematic diagram that Fig. 2 provides for the utility model embodiment;
The bottom gate type TFT structural representation that Fig. 3 provides for the utility model embodiment;
The top gate type TFT structural representation that Fig. 4 provides for the utility model embodiment;
The TFT that Fig. 5 provides for the utility model embodiment has the structural representation of two drain electrodes;
Fig. 6 forms leg-of-mutton array base palte part-structure schematic diagram for two drain electrodes and source electrode that the utility model embodiment provides;
Two drain electrodes and the straight array base palte part-structure of a source electrode shape schematic diagram that Fig. 7 provides for the utility model embodiment;
The semiconductor layer pattern schematic diagram that Fig. 8 provides for the utility model embodiment;
The TFT complete structure schematic diagram that Fig. 9 provides for the utility model embodiment;
The manufacture method schematic flow sheet of the bottom gate type TFT that Figure 10 provides for the utility model embodiment;
The manufacture method schematic flow sheet of the top gate type TFT that Figure 11 provides for the utility model embodiment.
Embodiment
The utility model embodiment provides a kind of thin-film transistor, array base palte and display unit, in order to improving the performance of TFT, thereby improves the image quality of image.
At present, use metal oxide obviously can improve the On current of TFT as the TFT semiconductor layer, this is because the electron mobility of metal oxide semiconductor layer is 5 ~ 10 times of electron mobility of amorphous silicon semiconductor layer.Behind the material decision of semiconductor layer, the electric conductivity of TFT (mainly instructing galvanization here) depends on the structure of TFT.
The utility model embodiment describes mainly for metal oxide TFT, but the utility model order also also goes for simultaneously non-crystalline silicon tft etc.
The TFT that the utility model embodiment provides, each TFT is formed with a source electrode and at least two drain electrodes, the source electrode links to each other with semiconductor layer by via hole respectively with drain electrode, form conducting channel between source electrode and each drain electrode, a plurality of conducting channels are so that the On current of TFT increases, and the performance of TFT is improved, and the area of source electrode does not increase, the electric capacity of source electrode does not change, and the demonstration image quality of image is improved.
The technical scheme that provides in order to be illustrated more clearly in the utility model embodiment, the below will be from TFT and array base palte two aspect explanations.
The TFT that the utility model embodiment provides comprises:
Substrate;
Be formed on gate electrode on the substrate, source electrode, at least two drain electrodes and semiconductor layer;
Be formed on the gate electrode protective layer between described gate electrode and semiconductor layer on the described substrate, be formed on the etching barrier layer between described semiconductor layer and source electrode and drain electrode on the described substrate.
Below in conjunction with the structure of TFT explanation array base palte, array base palte comprises:
Substrate, one or more thin-film transistor TFT, and scan line and data wire;
Described TFT comprises: be formed on gate electrode on the substrate, source electrode, at least two drain electrodes and semiconductor layer, described scan line links to each other with described gate electrode, and described data wire links to each other with all drain electrodes;
Described TFT also comprises: be formed on the gate electrode protective layer between described gate electrode and semiconductor layer on the described substrate, be formed on the etching barrier layer between described semiconductor layer and source electrode and drain electrode on the described substrate;
Wherein, described source electrode links to each other with described semiconductor layer by the different via hole on the etching barrier layer respectively with described drain electrode.
Specify the technical scheme that the utility model embodiment provides below by accompanying drawing.
Referring to Fig. 2, be the array base palte schematic top plan view, comprising:
Each TFT2 comprises gate electrode g, source electrode s and the drain electrode d that is formed on the substrate 1;
Scan line 3 links to each other with gate electrode g, for TFT provides cut-in voltage;
In the process of implementation, the source electrode s of TFT2 links to each other with the pixel electrode 5 shown in Fig. 2, and when source electrode and drain electrode conducting, described picture frame signal voltage is loaded on this pixel electrode 5.
Referring to Fig. 3, on the array base palte along the sectional view of scan line shown in Figure 23 directions.
TFT2 comprises: substrate 1, the gate electrode 21 on the substrate 1, source electrode 22, at least two drain electrodes 23, and semiconductor layer 24;
TFT2 also comprises: be formed on the gate electrode protective layer 25 between gate electrode 21 and semiconductor layer 24 on the substrate 1, and be formed on the etching barrier layer 26 between semiconductor layer 24 and source electrode 22 and drain electrode 23 on the substrate 1;
Wherein, source electrode 22 links to each other with semiconductor layer 24 by the different via hole on the etching barrier layer 26 respectively with drain electrode 23.
The described TFT of the utility model embodiment can be that the bottom gate type structure also can be the top gate type structure.
TFT shown in Figure 3 is the bottom gate type structure.
Particularly, gate electrode 21 is positioned on the substrate 1;
Gate electrode protective layer 25 is positioned on the gate electrode 21;
Referring to Fig. 4, TFT is the top gate type structure.
Gate electrode protective layer 25 is positioned on source electrode 22 and the drain electrode 23;
In specific implementation process, in Fig. 3 and the TFT structure shown in Figure 4, the source electrode links to each other with semiconductor layer by via hole with drain electrode, preferably, cause source electrode and drain electrode may cover whole via hole for fear of the skill manufacturing deviation, cause the TFT hydraulic performance decline, the size of source electrode and drain electrode should be greater than the size of via hole, and Fig. 3 and Fig. 4 only are exemplary plot.
Need to prove, Fig. 3 does not embody scan line and the data wire that links to each other with thin-film transistor with Fig. 4, and the distribution of drain electrode and source electrode, in specific implementation process, scan line on the array base palte and gate electrode arrange with layer, source electrode and drain electrode arrange with layer, and data wire and source electrode and drain electrode arrange with layer.
The said film transistor working principle is summarized as follows:
The source electrode is connected by the semiconductor layer (such as metal oxide IGZO) that is positioned at its below with drain electrode, after the voltage signal of array base palte upper tracer is opened the TFT gate electrode, source electrode and drain electrode are by the semiconductor layer conducting, being loaded into the pixel electrode that with source electrode link to each other by drain electrode with conducting channel between the electrode of source from the signal voltage of data wire, is the pixel electrode charging.Drain electrode on the TFT that the utility model embodiment provides arranges more than one, and the source electrode arranges one.All drain electrodes are connected on the data lines simultaneously, and source electrode and each drain electrode form conducting channel.Therefore more than one of the conducting channel of the TFT that provides of the utility model embodiment, the distance between source electrode and the drain electrode determines the length of conducting channel, the size of source electrode and drain electrode determines the width of conducting channel.In the certain situation of the distance between source electrode and the drain electrode and size, the utility model is by increasing the number of drain electrode, increased the number of conducting channel, increased in fact the effective width of conducting channel, be loaded on the pixel electrode that links to each other with the source electrode so that the signal voltage on the data wire is easier, in the situation that the source electrode area does not have to increase, TFT is that the charging ability of pixel electrode improves, reduced pixel electrode saltus step the time cause the possibility of image colour cast.
Need to prove, source electrode and drain electrode and between distance in micron dimension, concrete shape can equivalence be square or circular, distance between source electrode and the drain electrode refers to the source electrode centers to the distance at drain electrode center, and the size of source electrode and drain electrode can be with the length of side or diameter as measurement index.
Lower mask body is introduced the set-up mode of the TFT that the utility model embodiment provides.
In order not affect the aperture opening ratio of each subpixel area pixel on the array base palte, in the scope that Mapping Technology allows, the TFT that is positioned at subpixel area should be the smaller the better.When the drain electrode quantity on the TFT is too much, because drain electrode links to each other with pixel electrode, drain electrode can affect the aperture opening ratio of TFT, in the specific implementation process, can decide according to size and the structure of display unit, namely design according to the actual requirements the drain electrode of the suitable size of suitable quantity.
The viewing area be used for to show that the structure of TFT of image is identical on the array base palte, and the below is with a bottom gate type TFT, and the TFT structure that two or three drain electrodes are set on the TFT is the example explanation.
Referring to Fig. 5, be TFT part-structure schematic top plan view.
Be the subpixel area that data wire 4 and scan line 3 surround such as Fig. 5.
TFT comprises two drain electrodes, the first drain electrode 231 and 232, one source electrodes 22 of the second drain electrode;
The first drain electrode 231, the second drain electrode 232, and the line of source electrode 22 a formation triangle (as shown in Figure 5) perhaps consist of straight line as shown in Figure 6.
Referring to Fig. 5, the first drain electrode 231, the second drain electrode 232, and the line between the source electrode 22 consists of right-angled triangle, acute triangle or obtuse triangle (Figure 5 shows that right-angled triangle) take source electrode 22 as drift angle.
Preferably, for so that different drain electrode is consistent with channel length between the electrode of source, and channel width is consistent, guarantees the optimum performance of TFT, and preferably, the distance of source electrode distance drain electrode equates.
Preferably, the size of source electrode equals the size of drain electrode.
The first drain electrode 231 shown in Figure 5, the second drain electrode 232, and the line of source electrode 22 consists of an isosceles triangle.
Same as the prior art, source electrode 22 and drain electrode 23 all are arranged on the gate electrode 21, and the upright projection of source electrode 22 and drain electrode 23 is within the transistorized zone of gate electrode 21 cover films.
Preferably, referring to Fig. 7, TFT comprises three drain electrodes, the first drain electrode 231, the second drain electrode 232 and the 3rd drain electrode 233;
The first drain electrode 231, the second drain electrode 232, and the line of source electrode 22 consists of right-angled triangle, acute triangle or obtuse triangle take source electrode 22 as drift angle; And second drain electrode 232, the 3rd drain electrode 233, and the line of source electrode 22 consists of right-angled triangle, acute triangle or obtuse triangle take source electrode 22 as drift angle.
In like manner, described right-angled triangle, acute triangle or obtuse triangle are that isosceles triangle is best, and the TFT performance is higher.
The triangle that consists of when the interconnecting line between two drain electrodes and the source electrode straight line of comparing is better, and the source electrode can be arranged on the position nearer apart from pixel electrode like this, and in the specific implementation process, technological design is simple.
When the triangle of the formation of the interconnecting line between two drain electrodes and the source electrode was acute triangle, the drift angle of acute triangle was not less than 30 degree.
This is because according to present Mapping Technology ability, making live width is relatively difficulty of the following pattern of 3 μ m, the minimum diameter of source described in the utility model electrode and drain electrode is 4 μ m, the shortest 4 μ m of distance between source electrode and the drain electrode, distance between two drain electrodes is very near, but in order to form two complete conducting channels, any two drain electrodes can not contact, when the drift angle of two acute triangles is spent less than 30, distance between two drain electrodes might be less than the live width limit 3 μ m, when the distance between two drain electrodes during less than the live width limit 3 μ m, might be so that mutual conduction between two drain electrodes, two raceway groove conductings of finishing, the performance of reduction TFT.
Because drain electrode 23 is overlapping in the upright projection on the substrate and the upright projection of gate electrode 21 on substrate, therefore do not affect the aperture opening ratio of TFT pixel.
In specific implementation process, only need guarantee that the mistake hole size of answering with the source electrode pair equals the excessively hole size corresponding with drain electrode, by composition technique, large source electrode and the drain electrodes such as formation.
It is the higher metal oxide of electron mobility that the utility model embodiment preferably is applicable to semiconductor layer.
In order to realize the better TFT of performance, the better display unit of image quality, described semiconductor layer is the conductive film layer in covering TFT zone, or for covering the conductive film layer of conducting channel, is illustrated in figure 8 as the conductive film layer pattern of source electrode, drain electrode line correspondence triangular in shape.
Preferably, described semiconductor layer is metal oxide semiconductor layer, and described semiconductor layer is not less than and covers source electrode, drain electrode and the conducting channel planimetric area on substrate at the planimetric area on the substrate.
Need to prove; referring to Fig. 9, the thin-film transistor that the utility model embodiment provides also comprises, is positioned at the outermost passivation protection layer 6 of thin-film transistor; and being positioned on the substrate 1 resilient coating 7 with substrate contacts, this resilient coating 7 can increase the adhesive force of rete on substrate and the substrate.This resilient coating can be to be formed by metals such as molybdenum Mo, titanium Ti, Mo alloy, Ti alloy, Cu alloys.
Passivation protection layer 6 can be to be made by organic resin material.The organic resin inorganic material hardness of comparing is less, more is conducive to the thin-film transistor outermost layer is played smooth effect, is conducive to the ideal alignment of the liquid crystal molecule between subsequent technique color membrane substrates and the thin-film transistor.
Above-mentioned only is the explanation technical solutions of the utility model as an example of bottom gate type TFT example, and invention order of the present utility model is applicable to top gate type TFT too, repeats no more here.
In addition, the described TFT of the utility model embodiment not only goes for the pixel TFT that array base palte viewing area (A-A zone) is used for showing image, equally also go for the array substrate peripheral zone for the TFT of antistatic, it is larger that the TFT of antistatic can arrange, it is more more that the drain electrode number can arrange, can need not to consider the problem of aperture opening ratio so that electrostatic induced current is in time led away, design is got up more convenient.
The below illustrates the manufacture method of the thin-film transistor that the utility model embodiment provides from the technological process aspect.
The method integral body of the making thin-film transistor that the utility model embodiment provides comprises:
Adopt composition technique to form gate electrode, source electrode at substrate, drain electrode, and the process of semiconductor layer, wherein each TFT comprises at least two drain electrodes; And
Adopt composition technique at the gate electrode protective layer of substrate formation between described gate electrode and semiconductor layer, and the process of the etching barrier layer between described semiconductor layer and source electrode and drain electrode.
In specific implementation process, also comprise: adopt composition technique to form the process of the gate line that links to each other with described gate electrode and the data wire that links to each other with described drain electrode at substrate.
Described composition technique refers to make mask, exposure, development, the photoetching of figure, the processes such as etching.
For instance, adopt composition technique to form gate electrode at substrate, be specially: at first deposit gate electrode layer at substrate, then be coated with photoresist, utilize mask plate that photoresist is exposed and form photoetching agent pattern with development treatment, then utilize this photoetching agent pattern as etching mask, remove corresponding electrode layer by techniques such as etchings, and remove remaining photoresist, finally form gate electrode figure at substrate.
Referring to Figure 10, bottom gate type TF T manufacture method comprises:
S11, employing composition technique form gate electrode at substrate;
S12, employing composition technique form the gate electrode protective layer at described gate electrode;
S13, employing composition technique form semiconductor layer at described gate electrode protective layer;
S14, employing composition technique form etching barrier layer at described semiconductor layer;
S15, employing composition technique form source electrode and drain electrode at described etching barrier layer.
In specific implementation process, bottom gate type TFT manufacture method also comprises:
When forming gate electrode, form the scan line that links to each other with gate electrode, gate electrode and scan line arrange with layer.
When forming drain electrode, form the data wire that links to each other with described drain electrode, drain electrode and data wire arrange with layer.
Referring to Figure 11, the method for making the thin-film transistor of top gate type TFT comprises:
S21, employing composition technique form semiconductor layer at substrate;
S22, employing composition technique form etching barrier layer at described semiconductor layer;
S23, employing composition technique form source electrode and drain electrode at described etching barrier layer.
S24, employing composition technique form the gate electrode protective layer at described source electrode and drain electrode;
S25, employing composition technique form gate electrode at described gate electrode protective layer.
In specific implementation process, bottom gate type TFT manufacture method also comprises:
When forming gate electrode, form the scan line that links to each other with gate electrode, gate electrode and scan line arrange with layer.
When forming drain electrode, form the data wire that links to each other with described drain electrode, drain electrode and data wire arrange with layer.
Above-mentioned employing composition technique also namely adopts exposure, development, photoetching and etching technics to form the rete of certain pattern, and the specific implementation process that composition technique forms certain pattern all belongs to prior art, repeats no more here.
The utility model improvements are, make in the process of SD layer (layer at source electrode, drain electrode and data wire place becomes the SD layer), each TFT is formed with a source electrode and at least two drain electrodes, the source electrode links to each other with semiconductor layer by via hole respectively with drain electrode, form conducting channel between source electrode and each drain electrode, a plurality of conducting channels are so that the On current of TFT increases, and the performance of TFT is improved.
Also comprise after step S15 and S25: formation is positioned at the outermost passivation layer protective layer of thin-film transistor.
Need to prove that the TFT that the utility model embodiment provides can be metal oxide TFT, also can be non-crystalline silicon tft.
The below specifies the technological process of making TFT to make bottom gate type metal oxide TFT shown in Figure 9 as example;
Thin-film transistor manufacture method shown in the utility model embodiment comprises:
Step 1: the forming process of resilient coating, gate electrode and scan line on the substrate.
At first in order to increase the adhesive force between each rete and the substrate, at first adopt the method for sputter or thermal evaporation at substrate (such as transparent glass substrate or quartz base plate), form the resilient coating that one deck covers whole substrate, resilient coating can be silica or silicon nitride dielectric layer.
Then, in the substrate employing sputter that is formed with resilient coating or the method for thermal evaporation, deposition layer of metal layer is used for making gate electrode and scan line, forms gate electrode and scan line by single exposure development, photoetching and etching technics.The gate electrode that forms and the pattern of scan line and the position is same as the prior art repeats no more here.
Step 2: the forming process of gate electrode protective layer on the substrate.
Pass through the insulating barrier of chemical vapour deposition technique (PECVD) successive sedimentation one deck silicon nitride or silica at the substrate of completing steps one; Form the grid electrode insulating layer of covering grid electrode by single exposure development, photoetching and etching technics.
Step 3: the forming process of substrate upper semiconductor layer.
By sputtering method successive sedimentation metal oxide rete, by single exposure development, photoetching, etching technics forms semiconductor layer.
Described metal oxide can be indium gallium zinc oxide IGZO, indium-zinc oxide IZO or other metal oxides.
Step 4: the forming process of etching barrier layer on the substrate.
On the substrate of completing steps three, by the insulating barrier of PECVD method deposition one deck silica or silicon nitride, by single exposure development, photoetching, etching technics forms the etching barrier layer that covers semiconductor layer.
Step 5: the forming process of the via hole corresponding with source electrode and drain electrode on the substrate.
Be formed with on the substrate of etching barrier layer, by exposure imaging, chemical wet etching technique, forming connection source electrode and semiconductor layer, and connecting drain electrode and semi-conductive a plurality of via holes.
Step 6: source electrode, drain electrode on the substrate, and the forming process of data wire.
Method by sputter or thermal evaporation has certain thickness metallic diaphragm in the TFT formation that is formed with via hole, forms source electrode, drain electrode by single exposure development, chemical wet etching technique, and the data wire that links to each other with the source electrode.Described metallic diaphragm can be crome metal Cr, tungsten W, Titanium Ti, metal tantalum Ta, metal molybdenum Mo etc., or the alloy of above-mentioned at least two kinds of metals.Can be that the single-layer metal layer also can be the multiple layer metal layer.
Step 7: the forming process of passivation layer on the substrate.
Substrate at completing steps eight deposits one deck oxide, nitride or oxynitrides rete by the PECVD method.
It is similar for forming bottom gate type metal oxide TFT technological process to step 7 to form top gate type metal oxide TFT technological process and above-mentioned steps one, repeats no more here.
The utility model embodiment also provides a kind of array base palte, comprises the said film transistor.Especially comprise oxide thin film transistor, the concrete structure of oxide thin film transistor and principle do not repeat them here with above-mentioned embodiment.This array base palte can comprise the array of pixel cell.This oxide thin film transistor for example is used for the switching transistor of pixel cell.In some instances, the source electrode of oxide thin film transistor is connected with the pixel electrode of pixel cell, and pixel electrode is transparency electrode.The utility model embodiment also provides a kind of display unit, comprise described array base palte, this display unit can be the display unit such as liquid crystal panel, liquid crystal display, LCD TV, ORGANIC ELECTROLUMINESCENCE DISPLAYS oled panel, OLED display, OLED TV or Electronic Paper.
In sum, the utility model embodiment provides a kind of thin-film transistor, array base palte and display unit, by a more than drain electrode is set in each TFT of SD layer, a plurality of drain electrodes and source electrode form a plurality of conducting channels, increase the ducting capacity of TFT, the electric capacity of source electrode does not increase, thereby so that the performance of TFT is improved, the display device images image quality improves.
Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these are revised and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these changes and modification interior.
Claims (10)
1. a thin-film transistor is characterized in that, comprising:
Substrate;
Be formed on gate electrode on the substrate, source electrode, at least two drain electrodes and semiconductor layer;
Be formed on the gate electrode protective layer between described gate electrode and semiconductor layer on the described substrate, be formed on the etching barrier layer between described semiconductor layer and source electrode and drain electrode on the described substrate; Wherein, described source electrode links to each other with described semiconductor layer by via hole respectively with described drain electrode.
2. thin-film transistor according to claim 1 is characterized in that,
Described gate electrode is positioned on the described substrate;
Described gate electrode protective layer is positioned on the described gate electrode;
Described semiconductor layer is positioned on the described gate electrode protective layer;
Described etching barrier layer is positioned on the described semiconductor layer;
Described source electrode and drain electrode are positioned on the described etching barrier layer.
3. thin-film transistor according to claim 1 is characterized in that,
Described semiconductor layer is positioned on the described substrate;
Described etching barrier layer is positioned on the described semiconductor layer;
Described source electrode and drain electrode are positioned on the described etching barrier layer;
Described gate electrode protective layer is positioned on described source electrode and the drain electrode;
Described gate electrode is positioned on the described gate electrode protective layer.
4. thin-film transistor according to claim 1 is characterized in that, comprises two drain electrodes, the first drain electrode and the second drain electrode;
The first drain electrode, the second drain electrode, and the line structure between the electrode of source is in line or consist of isosceles triangle take the source electrode as drift angle.
5. thin-film transistor according to claim 1 is characterized in that, comprises three drain electrodes, the first drain electrode, the second drain electrode and the 3rd drain electrode;
The first drain electrode, the second drain electrode, and the line of source electrode consists of the isosceles triangle take the source electrode as drift angle; And
The second drain electrode, the 3rd drain electrode, and the line of source electrode consists of the isosceles triangle take the source electrode as drift angle.
6. thin-film transistor according to claim 1, it is characterized in that, described semiconductor layer is metal oxide semiconductor layer, and described semiconductor layer is not less than and covers source electrode, drain electrode and the conducting channel planimetric area on substrate at the planimetric area on the substrate.
7. according to claim 5 or 6 described thin-film transistors, it is characterized in that the drift angle of described isosceles triangle is not less than 30 °.
8. thin-film transistor according to claim 1 is characterized in that, the size of source electrode equals the size of drain electrode.
9. an array base palte is characterized in that, comprises the described thin-film transistor of claim 1 to 8.
10. a display unit is characterized in that, comprises array base palte claimed in claim 9.
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| CN 201220519148 CN202816957U (en) | 2012-10-11 | 2012-10-11 | Thin film transistor, array substrate and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916051A (en) * | 2012-10-11 | 2013-02-06 | 京东方科技集团股份有限公司 | Thin-film transistor, manufacturing method of thin-film transistor, array substrate and display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102916051A (en) * | 2012-10-11 | 2013-02-06 | 京东方科技集团股份有限公司 | Thin-film transistor, manufacturing method of thin-film transistor, array substrate and display device |
| CN102916051B (en) * | 2012-10-11 | 2015-09-02 | 京东方科技集团股份有限公司 | A kind of thin-film transistor and preparation method thereof, array base palte and display unit |
| US9196735B2 (en) | 2012-10-11 | 2015-11-24 | Boe Technology Group Co., Ltd. | Thin film transistor and method for manufacturing the same, array substrate, and display device |
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