CN202798666U - Boosted exclusive OR circuit structure - Google Patents
Boosted exclusive OR circuit structure Download PDFInfo
- Publication number
- CN202798666U CN202798666U CN 201220424264 CN201220424264U CN202798666U CN 202798666 U CN202798666 U CN 202798666U CN 201220424264 CN201220424264 CN 201220424264 CN 201220424264 U CN201220424264 U CN 201220424264U CN 202798666 U CN202798666 U CN 202798666U
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- integrated chip
- gate integrated
- xor gate
- exclusive
- resistance
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Abstract
The utility model discloses a boosted exclusive OR circuit structure. The structure is characterized by comprising an exclusive-OR gate integrated chip U1, an exclusive-OR gate integrated chip U2, a resistor R1, a backing protective circuit and a boosted circuit, wherein the exclusive-OR gate integrated chip U1 and the exclusive-OR gate integrated chip U2 are connected mutually, the resistor R1 is connected to input ends of the exclusive-OR gate integrated chip U1 and the exclusive-OR gate integrated chip U2, the backing protective circuit is connected to the exclusive-OR gate integrated chip U1 in parallel, and the boosted circuit is connected to output ends of the exclusive-OR gate integrated chip U1 and the exclusive-OR gate integrated chip U2. The structure is simple, low in production cost and maintenance cost and capable of solving the defect that a traditional exclusive OR circuit does not have a backing protection function.
Description
Technical field
The utility model relates to a kind of circuit structure, specifically refers to a kind of XOR circuit structure of boosting.
Background technology
At present, people can use various electronic equipments in life, and all have NOR gate circuit in the most electronic equipment, with by identify height, end level comes electronic equipment is controlled.But present NOR gate circuit does not on the market all have reversal connection protection function and boost function, and therefore when the unexpected appearance of external power supply level conversion of the high end, its peak value can produce larger impact to NOR gate circuit, and then affects its recognition effect.
The utility model content
The purpose of this utility model is to overcome the defective that present NOR gate circuit does not have reversal connection protection function and boost function, provides a kind of simple in structure, has a kind of XOR circuit structure of boosting of good reversal connection protection function and boost function.
The utility model is achieved through the following technical solutions: a kind of XOR circuit structure of boosting; mainly by two interconnective XOR gate integrated chip U1 and XOR gate integrated chip U2; the resistance R 1 that all is connected with the input of XOR gate integrated chip U1 and XOR gate integrated chip U2; the reverse-connection protection circuit that is in parallel with XOR gate integrated chip U1, and the booster circuit that is connected with the output of XOR gate integrated chip U1 and XOR gate integrated chip U2 forms.
Further; described reverse-connection protection circuit is by an end and the input of XOR gate integrated chip U1 is connected, the other end is connected with the output of XOR gate integrated chip U1 after diode D3, relay K fuse F; and the diode D4 that is in parallel with relay K forms, and the normally opened contact of described relay K then is connected in series mutually with resistance R 1.
Described booster circuit is by resistance R 2 and the storage capacitor C of mutual serial connection, and one end be connected to bidirectional trigger diode DB between resistance R 2 and the storage capacitor C and diode D2 forms, the output of described XOR gate integrated chip U1 and XOR gate integrated chip U2 then is connected with the two ends of resistance R 2 respectively.
In order to realize preferably the utility model, the impedance of described resistance R 1 equates with the impedance of resistance R 2.
The utility model compared with prior art has the following advantages and beneficial effect:
(1) not only overall structure is very simple for the utility model, and its cost of manufacture and maintenance cost are very cheap, and the utility model can also thoroughly solve the ubiquitous defective that does not have reversal connection protection function of traditional NOR gate circuit.
(2) the utlity model has boost function, can guarantee when voltage is not high, also can normally use, thereby enlarge the scope of application.
Description of drawings
Fig. 1 is electrical block diagram of the present utility model.
Embodiment
Below in conjunction with embodiment the utility model is described in further detail, but execution mode of the present utility model is not limited to this.
Embodiment
As shown in Figure 1; the XOR circuit structure of boosting of the present utility model is mainly by two interconnective XOR gate integrated chip U1 and XOR gate integrated chip U2; the resistance R 1 that all is connected with the input of XOR gate integrated chip U1 and XOR gate integrated chip U2; the reverse-connection protection circuit that is in parallel with XOR gate integrated chip U1, and the booster circuit that is connected with the output of XOR gate integrated chip U1 and XOR gate integrated chip U2 forms.
As shown in the figure, this reverse-connection protection circuit is by an end and the input of XOR gate integrated chip U1 is connected, the other end is connected with the output of XOR gate integrated chip U1 after diode D3, relay K fuse F, and the diode D4 that is in parallel with relay K forms, and the normally opened contact of described relay K then is connected in series mutually with resistance R 1; This booster circuit is then by resistance R 2 and the storage capacitor C of mutual serial connection, and bidirectional trigger diode DB and diode D2 that an end is connected between resistance R 2 and the storage capacitor C form.
During connection, the output of XOR gate integrated chip U1 and XOR gate integrated chip U2 is connected with the two ends of resistance R 2 respectively, and namely resistance R 2 is between the output of XOR gate integrated chip U1 and XOR gate integrated chip U2.In order to ensure result of use, the impedance of this resistance R 1 equates that with the impedance of resistance R 2 its optimum impedance is 5.6K Ω.
As mentioned above, just can realize preferably the utility model.
Claims (4)
1. XOR circuit structure of boosting; it is characterized in that; mainly by two interconnective XOR gate integrated chip U1 and XOR gate integrated chip U2; the resistance R 1 that all is connected with the input of XOR gate integrated chip U1 and XOR gate integrated chip U2; the reverse-connection protection circuit that is in parallel with XOR gate integrated chip U1, and the booster circuit that is connected with the output of XOR gate integrated chip U1 and XOR gate integrated chip U2 forms.
2. a kind of XOR circuit structure of boosting according to claim 1; it is characterized in that; described reverse-connection protection circuit is by an end and the input of XOR gate integrated chip U1 is connected, the other end is connected with the output of XOR gate integrated chip U1 after diode D3, relay K fuse F; and the diode D4 that is in parallel with relay K forms, and the normally opened contact of described relay K then is connected in series mutually with resistance R 1.
3. a kind of XOR circuit structure of boosting according to claim 2, it is characterized in that, described booster circuit is by resistance R 2 and the storage capacitor C of mutual serial connection, and one end be connected to bidirectional trigger diode DB between resistance R 2 and the storage capacitor C and diode D2 forms, the output of described XOR gate integrated chip U1 and XOR gate integrated chip U2 then is connected with the two ends of resistance R 2 respectively.
4. a kind of XOR circuit structure of boosting according to claim 3 is characterized in that the impedance of described resistance R 1 equates with the impedance of resistance R 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220424264 CN202798666U (en) | 2012-08-25 | 2012-08-25 | Boosted exclusive OR circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220424264 CN202798666U (en) | 2012-08-25 | 2012-08-25 | Boosted exclusive OR circuit structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202798666U true CN202798666U (en) | 2013-03-13 |
Family
ID=47825835
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220424264 Expired - Fee Related CN202798666U (en) | 2012-08-25 | 2012-08-25 | Boosted exclusive OR circuit structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202798666U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104883182A (en) * | 2015-05-26 | 2015-09-02 | 孙景春 | Boost exclusive OR circuit structure |
-
2012
- 2012-08-25 CN CN 201220424264 patent/CN202798666U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104883182A (en) * | 2015-05-26 | 2015-09-02 | 孙景春 | Boost exclusive OR circuit structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130313 Termination date: 20130825 |