CN202794422U - Recommended standard (RS) 422 interface loop test jig - Google Patents
Recommended standard (RS) 422 interface loop test jig Download PDFInfo
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- CN202794422U CN202794422U CN 201220453369 CN201220453369U CN202794422U CN 202794422 U CN202794422 U CN 202794422U CN 201220453369 CN201220453369 CN 201220453369 CN 201220453369 U CN201220453369 U CN 201220453369U CN 202794422 U CN202794422 U CN 202794422U
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- measurement jig
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Abstract
The utility model discloses a recommended standard (RS) 422 interface loop test jig which comprises a jib body, a first pin to a ninth pin and a first diode to a fourth diode. The jib body corresponds to a RS 422 interface. The first pin to the ninth pin respectively correspond to corresponding pins arranged on the RS 422 interface. The anode of the first diode is connected with the first pin, the cathode of the first diode is connected with the fourth pin, the anode of the second diode is connected with the second pin, the cathode of the second diode is connected with the third pin, the anode of the third diode is connected with the sixth pin, the cathode of the third diode is connected with the ninth pin, the anode of the fourth diode is connected with the seventh pin, and the cathode of the fourth diode is connected with the eighth pin. Therefore, a loop is formed between the pins of the test jig, transmitted signals cannot obtain a correct result when the sequence of the pins of the RS 422 interface of a corresponding electronic device is wrong, and further whether the sequence of the pins of the RS 422 interface is correct can be tested.
Description
[technical field]
The utility model relates to a kind of loop-around test tool, particularly relates to a kind of RS422 interface loop measurement jig.
[background technology]
RS-422 standard full name is " electrical specification of balanced voltage digital interface circuit ", and it has defined the characteristic of interface circuit.
For being provided with the RS-422 interface on the electronic installations such as PC (notebook computer and desktop computer), and when its each pin tested, usually can use measurement jig as shown in Figure 1.
See also Fig. 1, Fig. 1 illustrates and is prior art RS-422 interface loop measurement jig structural representation.Described RS-422 interface loop measurement jig comprises: the first pin 1(Transmit-, TX-; Send negative), the second pin 2(Transmit+, TX+; Just send), the 3rd pin 3(Receive+, RX+; Just receive), the 4th pin 4(Receive-, RX-; Receive negative), the 5th pin 5(Signal ground, GND; Signal ground), the 6th pin 6(Request to send-, RTS-; Request sends negative), the 7th pin 7(Request to send+, RTS+; Request just sends), the 8th pin 8(Clear to send+, CTS+; Just allow to send), the 9th pin 9((Clear to send-, CTS-; Allow to send negative).
More than each pin be connected respectively respective pins on the electronic installation RS-422 interface.Wherein, above-mentioned the first pin 1, the 4th pin 4 link to each other with wire; Above-mentioned the second pin 2, the 3rd pin 3 link to each other with wire; Above-mentioned the 6th pin 6, the 9th pin 9 link to each other with wire; Above-mentioned the 7th pin 7, the 8th pin 8 link to each other with wire; The 5th pin 5 ground connection.
Yet, when adopting above-mentioned measurement jig to test, if two pins order each other of the first pin 1 of corresponding described measurement jig, the 4th pin 4 is wrong on the electronic installation RS-422 interface; Perhaps two pins order each other of the second pin 2 of corresponding described measurement jig, the 3rd pin 3 is wrong on the electronic installation RS-422 interface; Perhaps two pins order each other of the 6th pin 6 of corresponding described measurement jig, the 9th pin 9 is wrong on the electronic installation RS-422 interface; Two pins order each other of the 7th pin 7 of corresponding described measurement jig, the 8th pin 8 is wrong again or on the electronic installation RS-422 interface.If loop itself is normal, its demonstration result when loop-around test still passes through for test.
Therefore, when adopting above-mentioned RS422 interface loop measurement jig to test, can't reach whether the position of each pin in the loop is correctly tested.
In view of this, be necessary to develop a kind of RS422 interface loop measurement jig in fact, to address the above problem.
[summary of the invention]
Therefore, the purpose of this utility model provides a kind of RS422 interface loop measurement jig, and whether the position that can't judge each pin in the loop when solving test correct problem.
In order to achieve the above object, the RS422 interface loop measurement jig that the utility model provides, described measurement jig comprises:
The tool body, its corresponding described RS422 interface;
The first to the 9th pin, the respective pins on its corresponding described RS422 interface;
First to fourth diode, described the first diode cathode connects described the first pin, negative pole connects described the 4th pin, described the second diode cathode connects described the second pin, negative pole connects described the 3rd pin, described the 3rd diode cathode connects described the 6th pin, negative pole connects described the 9th pin, and described the 4th diode cathode connects described the 7th pin, negative pole connects described the 8th pin.
Wherein, described the first pin for send negative pin, the second pin for send positive pin, the 3rd pin for receive positive pin, the 4th pin for receive negative pin, the 5th pin be signal ground pin, the 6th pin for request sends negative pin, the 7th pin for request sends positive pin, the 8th pin sends positive pin, the 9th pin for allowing to send negative pin for allowing.
Compared to prior art, utilize RS422 interface loop measurement jig of the present utility model, because between described the first pin and described the 4th pin, between described the second pin and described the 3rd pin, between described the 6th pin and described the 9th pin, all be provided with diode between described the 7th pin and described the 8th pin.Thereby so that the loop that forms between the pin of above-mentioned measurement jig, when the pin order of the RS422 interface of the electronic installation that it is corresponding makes a mistake, the signal of transmission can not obtain correct result, therefore can reach RS422 interface pin order correctness is tested.
[description of drawings]
Fig. 1 illustrates and is prior art RS422 interface loop measurement jig structural representation.
Fig. 2 illustrates the structural representation into RS422 interface loop measurement jig of the present utility model one preferred embodiment.
[embodiment]
See also Fig. 2, Fig. 2 illustrates the structural representation into RS422 interface loop measurement jig of the present utility model one preferred embodiment.
In order to achieve the above object, the RS422 interface loop measurement jig that the utility model provides, in present embodiment, described measurement jig comprises:
The first to the 9th pin (1～～9), the respective pins on its corresponding described RS422 interface;
First to fourth diode (21～～24), described the first diode 21 positive poles connect described the first pin 1, negative pole connects described the 4th pin 4, described the second diode 22 positive poles connect described the second pin 2, negative pole connects described the 3rd pin 3, described the 3rd diode 23 positive poles connect described the 6th pin 6, negative pole connects described the 9th pin 9, and described the 4th diode 24 positive poles connect described the 7th pin 7, negative pole connects described the 8th pin 8.
Wherein, described the first pin 1 for send negative pin, the second pin 2 for send positive pin, the 3rd pin 3 for receive positive pin, the 4th pin 4 for receive negative pin, the 5th pin 5 be signal ground pin, the 6th pin 6 for request sends negative pin, the 7th pin 7 bear pin for allowing to send positive pin, the 9th pin 9 for allowing to send for request sends positive pin, the 8th pin 8.
When test, because between described the first pin 1 and described the 4th pin 4, between described the second pin 2 and described the 3rd pin 3, between described the 6th pin 6 and described the 9th pin 9, all be provided with diode (being respectively 21～～24) between described the 7th pin 7 and described the 8th pin 8.Thereby so that the loop that forms between the pin of above-mentioned measurement jig, the pin of the RS-422 interface of the electronic installation that it is corresponding, when if order makes a mistake, behind the transmitted test signal, because the forward conduction characteristic of diode, thereby can not obtain feeding back correct result, thereby can reach RS-422 interface pin order correctness is tested.
More than take the RS-422 interface as example, certainly, similarly interface also can adopt this kind loop-around test tool to test when doing loop-around test, just does on the line corresponding adjustment and gets final product.
Claims (2)
1. RS422 interface loop measurement jig is characterized in that described measurement jig comprises:
The tool body, its corresponding described RS422 interface;
The first to the 9th pin, the respective pins on its corresponding described RS422 interface;
First to fourth diode, described the first diode cathode connects described the first pin, negative pole connects described the 4th pin, described the second diode cathode connects described the second pin, negative pole connects described the 3rd pin, described the 3rd diode cathode connects described the 6th pin, negative pole connects described the 9th pin, and described the 4th diode cathode connects described the 7th pin, negative pole connects described the 8th pin.
2. RS422 interface loop measurement jig as claimed in claim 1, it is characterized in that, described the first pin for send negative pin, the second pin for send positive pin, the 3rd pin for receive positive pin, the 4th pin for receive negative pin, the 5th pin be signal ground pin, the 6th pin for request sends negative pin, the 7th pin for request sends positive pin, the 8th pin sends positive pin, the 9th pin for allowing to send negative pin for allowing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220453369 CN202794422U (en) | 2012-09-07 | 2012-09-07 | Recommended standard (RS) 422 interface loop test jig |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220453369 CN202794422U (en) | 2012-09-07 | 2012-09-07 | Recommended standard (RS) 422 interface loop test jig |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202794422U true CN202794422U (en) | 2013-03-13 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220453369 Withdrawn - After Issue CN202794422U (en) | 2012-09-07 | 2012-09-07 | Recommended standard (RS) 422 interface loop test jig |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202794422U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103675568A (en) * | 2012-09-07 | 2014-03-26 | 神讯电脑(昆山)有限公司 | Test fixture for RS422 interface loop |
| CN106291211A (en) * | 2015-06-01 | 2017-01-04 | 神讯电脑(昆山)有限公司 | Power-supply adapter test circuit |
-
2012
- 2012-09-07 CN CN 201220453369 patent/CN202794422U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103675568A (en) * | 2012-09-07 | 2014-03-26 | 神讯电脑(昆山)有限公司 | Test fixture for RS422 interface loop |
| CN103675568B (en) * | 2012-09-07 | 2017-04-26 | 神讯电脑(昆山)有限公司 | Test fixture for RS422 interface loop |
| CN106291211A (en) * | 2015-06-01 | 2017-01-04 | 神讯电脑(昆山)有限公司 | Power-supply adapter test circuit |
| CN106291211B (en) * | 2015-06-01 | 2018-06-22 | 神讯电脑(昆山)有限公司 | Power-supply adapter test circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20130313 Effective date of abandoning: 20170426 |