CN202735949U

CN202735949U - Dual-CPU stability preset device for MCR controller

Info

Publication number: CN202735949U
Application number: CN 201220381700
Authority: CN
Inventors: 陈亚亮; 王笋; 魏学良
Original assignee: BEIJING DONGZHAN KEBO ELECTRONIC Co Ltd
Current assignee: BEIJING DONGZHAN KEBO ELECTRONIC Co Ltd
Priority date: 2012-08-03
Filing date: 2012-08-03
Publication date: 2013-02-13
Anticipated expiration: 2022-08-03

Abstract

The utility model discloses a dual-CPU stability preset device for an MCR (Magnetic Control Reactor). The dual-CPU stability preset device comprises a dual-CPU control unit, a CPLD (Complex Programmable Logic Device) connected with the dual-CPU control unit, and a watch dog timer respectively connected with the CPU control unit and the CPLD. The dual-CPU stability preset device for the MCR controller can overcome defects in the prior art, including low reliability and safety, large loss and the like, and has the advantages of high reliability, good safety and small loss.

Description

A kind of MCR controller is stablized resetting means with two CPU

Technical field

The utility model relates to magnet controlled reactor (magnetic control reactor is called for short MCR) control technology field, particularly, relates to a kind of MCR controller and stablizes resetting means with two CPU.

Background technology

In the prior art, the software issue of two CPU of MCR (DSP and arm processor) control system is not well solved.

For example, after the program of CPU was absorbed in endless loop, generalized case was to adopt whole system power-off restoration function, like this controller hardware circuit of MCR has been caused certain infringement.If program does not solve after being absorbed in endless loop fast, may cause in this high-pressure system can't anticipated losses.

In realizing process of the present utility model, the defective such as the inventor finds to exist at least in the prior art that reliability is low, poor stability and loss are large.

Summary of the invention

The purpose of this utility model is, for the problems referred to above, proposes a kind of MCR controller and stablizes resetting means with two CPU, to realize that reliability is high, security is good and lose little advantage.

For achieving the above object, the technical solution adopted in the utility model is: a kind of MCR controller is stablized resetting means with two CPU, comprise two CPU control modules, the CPLD that is connected with described pair of CPU control module (Complex Programmable Logic Device, CPLD), the WatchDog Timer that is connected with CPLD with described pair of CPU control module and respectively.

Further, described pair of CPU control module, comprise the digital signal processing (Digital Signal Processing is called for short DSP) and ARM (the Advanced RISC Machines) processor that are connected with each other and are connected with WatchDog Timer with CPLD respectively.

Further, described WatchDog Timer is the WatchDog Timer on the master control borad that is installed in described pair of CPU control module.

The MCR controller of each embodiment of the utility model stablize resetting means with two CPU, owing to comprise pair CPU control modules, and the CPLD that is connected with two CPU control modules, and the WatchDog Timer that is connected with CPLD with two CPU control modules respectively; Can solve two CPU control module softwares " race flies " problem, can make the safety of controller reach a higher degree, make the MCR normal operation, safe and reliable; Thereby can overcome in the prior art that reliability is low, poor stability and the large defective of loss, to realize that reliability is high, security is good and lose little advantage.

Other features and advantages of the utility model will be set forth in the following description, and, partly from instructions, become apparent, perhaps understand by implementing the utility model.

Below by drawings and Examples, the technical solution of the utility model is described in further detail.

Description of drawings

Accompanying drawing is used to provide further understanding of the present utility model, and consists of the part of instructions, is used from explanation the utility model with embodiment one of the present utility model, does not consist of restriction of the present utility model.In the accompanying drawings:

Fig. 1 is the principle schematic that resets of WatchDog Timer;

Fig. 2 is the utility model MCR controller is stablized resetting means with two CPU principle of work (i.e. two cpu reset principles) synoptic diagram.

Embodiment

Below in conjunction with accompanying drawing preferred embodiment of the present utility model is described, should be appreciated that preferred embodiment described herein only is used for description and interpretation the utility model, and be not used in restriction the utility model.

According to the utility model embodiment, provide a kind of MCR controller to stablize resetting means with two CPU.As depicted in figs. 1 and 2, present embodiment comprises two CPU control modules, the CPLD that is connected with two CPU control modules, and the WatchDog Timer that is connected with CPLD with two CPU control modules respectively.

Particularly, above-mentioned pair of CPU control module comprises the DSP and the arm processor that are connected with each other and are connected with WatchDog Timer with CPLD respectively.This WatchDog Timer is the WatchDog Timer on the master control borad that is installed in two CPU control modules.

The MCR controller of above-described embodiment is stablized resetting means with two CPU, is applied in the MCR controller, has solved two CPU control module softwares " race flies " problem, can make the safety of controller reach a higher degree, makes the MCR normal operation, and is safe and reliable.

In the above-described embodiments, the MCR controller comprises that mainly information acquisition, information output and display screen control several parts, DSP and arm processor are distributed on the master control borad, and two CPU (being DSP and arm processor) carry out data communication and control information exchange by HPI bus and I/O mouth.Wherein, DSP processes reception and the transmission of data by CPLD expansion control; Arm processor receives the data that DSP processed by the HPI interface, sends to data on the display screen or user instruction is sent on the DSP to process.

The MCR controller of above-described embodiment is stablized resetting means with two CPU, increases WatchDog Timer by the master control borad at the MCR controller.WatchDog Timer divides hardware watchdog timer and software watchdog timer, the hardware watchdog timer is to utilize a timer circuit, its timing output is connected to the reset terminal of circuit, program (is commonly called as " feeding dog " to the WatchDog Timer zero clearing in the certain hour scope, kicking the dog or service the dog), when therefore program worked, WatchDog Timer always can not overflow, and also just can not produce reset signal.If program breaks down, the WatchDog Timer that do not reset in timing cycle just produces the reset signal starting system (such as Fig. 1) of laying equal stress on so that WatchDog Timer overflows.The same on the software watchdog timer principle, just the timer internal of the timer on the hardware circuit with processor replaced, can simplify hardware circuit design like this, but be not so good as hardware timer aspect reliability, self breaking down such as the internal system timer just can't detect.Certainly also have by dual timer to monitor that mutually this not only strengthens system overhead, can not solve whole issue, cause timer to interrupt losing efficacy such as the interrupt system fault.

WatchDog Timer itself is not the problem that resolution system occurs, and the fault of finding in debug process should be looked into the mistake that changes design itself.Add the WatchDog Timer purpose and be to the factors such as some program latent faults and rugged surroundings interference cause system in case of system halt and in unmanned intervention situation the automatic recovery system normal operating conditions.The loss that WatchDog Timer can not avoid fault to cause fully is after all from finding that fault slows down in system reset recovers normally during this period of time.DSP and ARM send to CPLD with feeding-dog signal, then carry out logic control by CPLD, and overall feeding-dog signal is sent to WatchDog Timer.The concrete operations principle: the DSP feeding-dog signal changes, and waits for that the ARM feeding-dog signal changes; If change, then WDO changes, the replacement WatchDog Timer count cycle; If DSP and ARM feeding-dog signal one do not change, then WDO can not change, and surpasses the WatchDog Timer count cycle will restart CPU.So when one of them CPU generation endless loop can't be fed dog, CPLD will have an effect WatchDog Timer by feeding-dog signal, thereby send reset signal with whole cpu resets (as shown in Figure 2).The monitoring time of WatchDog Timer is generally below the 2S, can well prevent from not solved fast when software issue appears in CPU, has reduced the impact of MCR on electric system.

It should be noted that at last: the above only is preferred embodiment of the present utility model, be not limited to the utility model, although with reference to previous embodiment the utility model is had been described in detail, for a person skilled in the art, it still can be made amendment to the technical scheme that aforementioned each embodiment puts down in writing, and perhaps part technical characterictic wherein is equal to replacement.All within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.

Claims

1. a MCR controller stablize resetting means with two CPU, it is characterized in that, comprises pair CPU control modules, the CPLD that is connected with described pair of CPU control module, and the WatchDog Timer that is connected with CPLD with described pair of CPU control module respectively.

2. MCR controller according to claim 1 is stablized resetting means with two CPU, it is characterized in that described pair of CPU control module comprises the DSP and the arm processor that are connected with each other and are connected with WatchDog Timer with CPLD respectively.

3. MCR controller according to claim 1 and 2 is stablized resetting means with two CPU, it is characterized in that described WatchDog Timer is the WatchDog Timer on the master control borad that is installed in described pair of CPU control module.