CN202721772U

CN202721772U - Integrated IP input SDI output decoder

Info

Publication number: CN202721772U
Application number: CN 201220427323
Authority: CN
Inventors: 王涛; 雷方燕
Original assignee: Individual
Current assignee: Individual
Priority date: 2012-08-27
Filing date: 2012-08-27
Publication date: 2013-02-06
Anticipated expiration: 2022-08-27

Abstract

The utility model discloses an integrated IP input SDI (serial digital interface) output decoder. The decoder solves problems of high cost and increased time delay because in the prior art, only by using two devices in cooperation, required functions can be achieved. The decoder comprises a physical interface transceiver, a parallel-serial converter, a FPGA which is embedded with an RTP/UDP/IP parsing module through an input end of the FPGA, and a MPEG2/H.264 decoder which is connected with an output end of the physical interface transceiver. An output of the MPEG2/H.264 decoder is connected with an input end of the parallel-serial converter through the FPGA. The integrated IP input SDI output decoder is reasonable in overall arrangement, and is convenient in use. Through transformation of the FPGA and decoding transmission of the MPEG2/H.264 decoder, integrated input and output of IP signals and SDI signals is realized. The integrated IP input SDI output decoder not only reduces cost, improves work efficiency, but also ensures output images have high quality, and time delay is reduce. Therefore, the integrated IP input SDI output decoder has high practical value and promotional value. The utility model discloses an integrated IP input SDI (serial digital interface) output decoder. The decoder solves problems of high cost and increased time delay because in the prior art, only by using two devices in cooperation, required functions can be achieved. The decoder comprises a physical interface transceiver, a parallel-serial converter, a FPGA which is embedded with an RTP/UDP/IP parsing module through an input end of the FPGA, and a MPEG2/H.264 decoder which is connected with an output end of the physical interface transceiver. An output of the MPEG2/H.264 decoder is connected with an input end of the parallel-serial converter through the FPGA. The integrated IP input SDI output decoder is reasonable in overall arrangement, and is convenient in use. Through transformation of the FPGA and decoding transmission of the MPEG2/H.264 decoder, integrated input and output of IP signals and SDI signals is realized. The integrated IP input SDI output decoder not only reduces cost, improves work efficiency, but also ensures output images have high quality, and time delay is reduce. Therefore, the integrated IP input SDI output decoder has high practical value and promotional value.

Description

Integral type IP input SDI output decoder

Technical field

The utility model relates to a kind of decoder, specifically, relates to integral type IP input SDI output decoder.

Background technology

SDI is the acronym of digital serial (serial digital interface), and its sdi signal is exported by the SDI interface.Digital serial interface is that each bit of data word and corresponding data communication device are crossed the interface that single channel sequentially transmits.Because the data transfer rate of digital serial signal is very high, and the SDI interface can not directly transmit compressed digital video signals, after the compressed signal of the equipment records such as digital VTR, hard disk is reset, must just can enter the SDI system through decompress(ion) and through the output of SDI interface, therefore, must be through processing before transmission.

At present, the decoder of output sdi signal has a lot, but all is by the signal of reception from ASI interface or radio frequency interface, and the decoder of the type does not have the ability of direct reception IP data.To be that SDI output all needs two equipment just can finish usually with the IP decoding video stream, wherein one be used for to receive IP and will carry out successively after IP packet header, UDP packet header and RTP packet header resolves it, export after isolating TS stream, other one then is to receive this TS stream and be converted into the laggard line output of SDI.

Although this kind will be inputted the purpose that technological means that IP is converted to SDI output can reach IP input SDI output, but it could realize specific function owing to needing two equipment to be used in conjunction with, any equipment is all indispensable, therefore its cost that need to drop into is higher, and two equipment are used in conjunction with the increase that also can cause delaying time.Therefore, existing mode of operation can't satisfy user's demand, must improve for existing technology.

The utility model content

The purpose of this utility model is to provide a kind of integral type IP input SDI output decoder, mainly solves prior art and could realize that owing to needing two equipment to be used in conjunction with the function that needs causes the problem that cost is high, time-delay increases.

To achieve these goals, the technical solution adopted in the utility model is as follows:

Integral type IP input SDI output decoder, comprise physical interface transceiver and parallel to serial converter, comprise also that input is embedded with the RTP/UDP/IP parsing module by inside FPGA links to each other with the output of described physical interface transceiver and MPEG2/H.264 decoder that output also links to each other with the input of parallel to serial converter by this FPGA.

Further, described FPGA also comprises respectively the 10/100/1000M triple speed Ethernet media access controller that links to each other with the RTP/UDP/IP parsing module with the physical interface transceiver, the ARP server that links to each other with the RTP/UDP/IP parsing module, and input and the output of MPEG2/H.264 decoder links to each other, output links to each other with the input of parallel to serial converter audio frequency embedding device; The input of described MPEG2/H.264 decoder links to each other with the RTP/UDP/IP parsing module.

Again further, in order to realize the utility model input IP signal and to export the function of sdi signal, described MPEG2/H.264 decoder comprises for the MPEG2/H.264 decoding chip that the output signal of FPGA is decoded, and the digital visual interface and the audio interface that are used for the output signal of MPEG2/H.264 decoding chip is transferred to audio frequency embedding device.

Specifically, described digital visual interface is the DVO digital visual interface, and described audio interface then is pcm interface.

For ease of the real time information of display video programs, this information is arranged and screens according to self needs for the user, the utility model also comprises the display controller that links to each other with described MPEG2/H.264 decoder.

Operation principle of the present utility model is: the IP network transmitting terminal sends the ARP request to the utility model, the APR server sends the MAC Address of the machine to the IP network transmitting terminal according to request, then the IP network transmitting terminal is according to the MAC Address that receives, the transport stream of the FPGA transmission compressed digital video in the utility model; The transport stream of this compressed digital video transfers to RTP/UDP/IP parsing module among the FPGA with the form of TS OVER IP transport stream, after this RTP/UDP/IP parsing module carries out IP packet header, UDP packet header and the parsing of RTP packet header successively to the TS OVER IP transport stream that receives, isolate TS stream, then it is delivered in the MPEG2/H.264 decoder and decodes; After the decoding, the vision signal of the digital video of MPEG2/H.264 decoder after by the audio frequency embedding device output decompress(ion) of DVO digital visual interface in the FPGA, the audio signal by the digital video of pcm interface behind the audio frequency embedding device output decompress(ion) simultaneously, vision signal and audio signal transmission are to audio frequency embedding device, and this audio frequency embedding device carries out the audio frequency embedding to vision signal to be processed; Video signal transmission after will processing is again at last carried out parallel serial conversion formation sdi signal, then output in parallel to serial converter.

Compared with prior art, the utlity model has following beneficial effect:

(1) the utility model layout is clear, reasonable in design, by the physical interface transceiver, FPGA, MPEG2/H.264 decoder and parallel to serial converter, just the compressed digital video transport stream that receives from IP network can be separated, and decode and obtain digital video and audio signal, then digital video is carried out the audio frequency embedding, at last the digital video after this audio frequency embedding is carried out exporting sdi signal behind the parallel serial conversion, whole process is integrated with IP input and SDI output, do not need fully by two equipment the IP signal to be received, and by after wherein a device parses obtains TS stream, be sent to again and convert sdi signal output in another equipment to, the utility model is not only swift to operate, convenient, save time and save trouble, and high efficiency, and can guarantee the high-quality of image, high-quality, reduced simultaneously time-delay.

(2) the utility model is provided with the ARP server, by the ARP request of ARP server response transmitting terminal, and the MAC Address of answer the machine, can guarantee that just the utility model can accurately receive the TS transport stream from the IP signal.

(3) the utility model is provided with display controller, not only is convenient to the real time information of display video programs, and makes things convenient for the user according to self needs the utility model to be arranged and regulates.

(4) the utility model is simple in structure, easy to use, and be convenient to make and produce, and can effectively reduce cost, compare and utilize existing technological means to realize IP input SDI output, the utlity model has substantial characteristics and progress, have very high practical value and promotional value in market.

Description of drawings

Fig. 1 is system block diagram of the present utility model.

Embodiment

The utility model is described in further detail below in conjunction with drawings and Examples, and execution mode of the present utility model includes but not limited to the following example.

Embodiment

As shown in Figure 1, the utility model (is called for short: PHY), FPGA, MPEG2/H.264 decoder, parallel to serial converter and display controller five parts form by the physical interface transceiver, wherein, the input of MPEG2/H.264 decoder links to each other with the output of PHY by FPGA and output also links to each other with the input of parallel to serial converter by this FPGA, and display controller then links to each other with the MPEG2/H.264 decoder.

FPGA of the present utility model is embedded with the RTP/UDP/IP parsing module, and the model of this FPGA is XC3S700A.In addition, described FPGA also comprises respectively and (being called for short: Ethernet three fast MAC) with the 10/100/1000M triple speed Ethernet media access controller that PHY links to each other with the RTP/UDP/IP parsing module, the ARP server that links to each other with the RTP/UDP/IP parsing module, and input links to each other with the output of MPEG2/H.264 decoder and audio frequency embedding device that output links to each other with the input of parallel to serial converter; The input of described MPEG2/H.264 decoder links to each other with the RTP/UDP/IP parsing module.

Specifically, described MPEG2/H.264 decoder comprises the MPEG2/H.264 decoding chip of decoding for the signal of FPGA transmission, be used for the signal of FPGA transmission is input to the TS router interface of MPEG2/H.264 decoding chip, be used for the digital visual interface to audio frequency embedding device outputting video signal after the decoding of MPEG2/H.264 decoding chip, and the rear audio interface that is used for to audio frequency embedding device output audio signal of MPEG2/H.264 decoding chip decoding, specifically, described digital visual interface is the DVO digital visual interface, and described audio interface then is pcm interface.The MPEG2/H.264 decoder is prior art, and the model of its MPEG2/H.264 decoding chip is Sti7105.

Workflow of the present utility model is as follows:

At first be that the IP network transmitting terminal sends the ARP request to the utility model, ARP server in the utility model is replied the MAC Address of the machine by the ARP request of RTP/UDP/IP parsing module, Ethernet three fast MAC and PHY response IP network transmitting terminal and to it, the IP network transmitting terminal is according to the MAC Address that receives, to the transport stream of the utility model transmission compressed digital video.The transport stream of this compressed digital video is passed through PHY, Ethernet three fast MAC transfer to the RTP/UDP/IP parsing module with the form of TS OVER IP transport stream, the RTP/UDP/IP parsing module carries out IP packet header successively to the TS OVER IP transport stream that receives, after resolve in UDP packet header and RTP packet header, isolate TS stream, then by TS router interface it is sent into the MPEG2/H.264 decoding chip, utilize the MPEG2/H.264 decoding chip that this TS stream is carried out the decoding of compressed digital video, the codec format of the MPEG2/H.264 decoder in the utility model is MPEG2 and two kinds of forms of high standard definition H.264.After the decoding, the MPEG2/H.264 decoder is by the vision signal of the digital video of DVO digital visual interface behind the audio frequency embedding device output decompress(ion), simultaneously the audio signal by the digital video of pcm interface behind the audio frequency embedding device output decompress(ion).Vision signal and audio signal transmission are to audio frequency embedding device, this audio frequency embedding device carries out the audio frequency embedding to vision signal to be processed, audio frequency embedding device of the present utility model can be identified the digital video of multiple format automatically, it comprises 1080i@50Hz, 1080i@60Hz, 720P@50Hz, 720P@60Hz, 576i@50Hz and 480i@49.98Hz, and according to user's needs, real-time demonstration by display controller, setting by the user, after selecting and regulating, with what insert, and the audio signal that needs for the user keeps, and unwanted other audio signals are carried out blanking.The form of this audio frequency embedding device discriminating digit video and this digital video carried out the audio frequency embedding after, it is transferred to carries out parallel serial conversion in the parallel to serial converter and form sdi signal, at last with its output.Parallel to serial converter in the utility model is prior art, therefore no longer its course of work is described in detail at this.

The utility model is installed in the 1U cabinet, repertoire all can be realized in this 1U cabinet, therefore, the utlity model has the characteristics of fast operating, easy to use and high efficiency, can satisfy to a great extent user's demand, the utility model has very high practical value and promotional value compared to prior art.

According to above-described embodiment, just can realize well the utility model.

Claims

1. integral type IP inputs the SDI output decoder, comprise physical interface transceiver and parallel to serial converter, it is characterized in that: comprise that also input is embedded with the MPEG2/H.264 decoder that FPGA links to each other with the output of described physical interface transceiver, output then links to each other with the input of described parallel to serial converter by this FPGA of RTP/UDP/IP parsing module by inside.

2. integral type IP according to claim 1 inputs the SDI output decoder, it is characterized in that: described FPGA also comprises respectively the 10/100/1000M triple speed Ethernet media access controller that links to each other with the RTP/UDP/IP parsing module with the physical interface transceiver, the ARP server that links to each other with the RTP/UDP/IP parsing module, and input and the output of MPEG2/H.264 decoder links to each other, output links to each other with the input of parallel to serial converter audio frequency embedding device; The input of described MPEG2/H.264 decoder links to each other with the RTP/UDP/IP parsing module.

3. integral type IP according to claim 2 inputs the SDI output decoder, it is characterized in that: described MPEG2/H.264 decoder comprises for the MPEG2/H.264 decoding chip that the output signal of FPGA is decoded, and the digital visual interface and the audio interface that are used for the output signal of MPEG2/H.264 decoding chip is transferred to audio frequency embedding device.

4. integral type IP according to claim 3 inputs the SDI output decoder, and it is characterized in that: described digital visual interface is the DVO digital visual interface, and described audio interface then is pcm interface.

5. it is characterized in that: also comprise the display controller that links to each other with described MPEG2/H.264 decoder according to claim 3 or 4 described integral type IP input SDI output decoders.