CN202551242U - Novel multi-path multi-resolution video decoder - Google Patents

Abstract

The utility model discloses a novel multi-path multi-resolution compatible digital video decoder which comprises a first composite video broadcast signal (CVBS) output interface, a second CVBS output interface, a video graphics array (VGA) output interface, a first digital/analog (D/A) conversion unit, a second D/A conversion unit, a digital signal change-over switch, a central processor unit comprising a core chip, and a network unit, wherein the output end of the network unit is connected with the input end of the central processor unit; the output end of the central processor unit is connected with the digital signal change-over switch; the digital signal change-over switch is simultaneously connected with the input ends of the first and second D/A conversion units; the output end of the first D/A conversion unit is connected with the first CVBS output interface; and the output end of the second D/A conversion unit is connected with the second CVBS output interface and the VGA output interface. Compared with the prior art, the novel multi-path multi-resolution compatible digital video decoder has the advantages that by virtue of a simple mode, a system can be compatible with multi-path multi-resolution video output, and the various requirements of video monitoring are met.

Description

A kind of novel multichannel is counted the Video Decoder of multiresolution

Technical field

The utility model relates to video decode and monitoring field, the particularly a kind of novel multichannel and the Video Decoder of compatible multiresolution.

Background technology

Like Fig. 1 and Fig. 2, the structure of traditional Video Decoder can be divided into the Video Decoder of high definition and the Video Decoder of SD according to the video resolution that can decode.Generally comprise CVBS interface or VGA interface, D/A converting unit, central processor unit, NE.In the time of concrete the use; Video Decoder for SD; Video Decoder obtains the video code flow that has encoded from NE, through central processing unit video code flow is decoded accordingly, just can obtain can be used for the original video data of D/A conversion.Central processing unit is passed to the D/A conversion chip with these original video data through the BT.656 interface, through the conversion of D/A chip, can obtain the vision signal (being the CVBS signal) of SD simulation, and the outside can connect monitor and watch video.For the Video Decoder of high definition, Video Decoder obtains the video code flow that has encoded from NE, through central processing unit video code flow is decoded accordingly, just can obtain can be used for the original video data of D/A conversion.Central processing unit is passed to the D/A conversion chip with these original video data through the BT.1120 interface, through the conversion of D/A chip, can obtain the vision signal (being the VGA signal) of high definition simulation, and the outside can connect monitor and watch video.

Though above-mentioned traditional DVS has accomplished the processing and the decoding work of video, there is also problem: be exactly that function ratio is more single, the Video Decoder of SD and the Video Decoder of high definition can not be compatible in same equipment the inside.Under the plurality of applications occasion, can't meet the demands.

The utility model content

In order to overcome the defective of prior art; The utility model discloses a kind of novel multichannel and the Video Decoder of compatible multiresolution; It makes the video output that system can the multiple resolution of compatible multichannel number in a simple manner, satisfies the multiple demand of people to video monitoring.

The utility model is with minimum cost, makes the system the inside can compatible SD and the video decode of high definition.

The technical scheme of the utility model is following:

A kind of novel multichannel is counted the Video Decoder of multiresolution, comprising: a CVBS output interface, the 2nd CVBS output interface, VGA output interface, a D/A converting unit, the 2nd D/A converting unit, digital signal diverter switch, the central processor unit that comprises acp chip, NE;

The output of said NE is connected with the input of central processor unit;

The output of said central processor unit is connected with the digital signal diverter switch;

Said digital signal diverter switch is connected with the input of a D/A converting unit, the 2nd D/A converting unit again simultaneously;

The output of the one D/A converting unit is connected with a CVBS output interface;

The output of the 2nd D/A converting unit connects the 2nd CVBS output interface and VGA output interface.

Compared with prior art, the beneficial effect of the utility model is following:

The utility model increases a digital signal shift switch between CPU and D/A converting unit on the existing product basis.Through the function of digital signal diverter switch, get final product the compatibility of compatible SD video decode and high definition video decoding.Accomplish the compatibility of SD output and high definition output with very low cost.

Description of drawings

Fig. 1 is the system construction drawing one of traditional DVS;

Fig. 2 is the system construction drawing two of traditional DVS;

Fig. 3 is the system construction drawing that a kind of novel multichannel of the utility model specific embodiment is counted the Video Decoder of multiresolution.

Embodiment

The below combines accompanying drawing and specific embodiment that the utility model is done further description.

Embodiment

Like Fig. 3; A kind of novel multichannel is counted the Video Decoder of multiresolution, comprising: a CVBS output interface 60, the 2nd CVBS output interface 70, VGA output interface 80, a D/A converting unit 40, the 2nd D/A converting unit 50, digital signal diverter switch 30, the central processor unit 20 that comprises acp chip, NE 10.

Wherein, the output of NE 10 is connected with the input of central processor unit 20.The output of central processor unit 20 is connected with digital signal diverter switch 30.Digital signal diverter switch 30 is connected with the input of a D/A converting unit 40, the 2nd D/A converting unit 50 again simultaneously.The output of the one D/A converting unit 40 is connected with a CVBS output interface 60; The output of the 2nd D/A converting unit 50 connects the 2nd CVBS output interface 70 and VGA output interface 80.

In the present embodiment; Central processor unit 20 is to link to each other with the D/A converting unit through digital signal diverter switch 30; Thereby realize that a system can export and the output of 1 road VGA high definition by compatible 2 road CVBS SDs; And 2 kinds of outputs can be selected arbitrarily to switch, and the CVBS output interface can be exported D1 resolution, and VGA can export the resolution up to 1080P.VGA can export the video image of single channel simultaneously, also can use the mode of picture-in-picture, the video image that output multichannel low resolution splices out.

Central processor unit adopts TMS320DM6467T as its acp chip, carries out obtaining video code flow through NE, and carries out video decode work, converts video code flow to original video data.And according to the resolution of video code flow, the control figure signal shift switch, coming to select automatically is the D/A conversion chip of connecting SD or high definition, thus original video data is delivered to suitable to the D/A conversion chip.The D/A conversion chip converts initial data to analog video signal, can be on monitor display video.

During concrete the use, the central processing unit of the utility model obtains video code flow through NE from Ethernet.Then the video code flow that gets access to is decoded accordingly, be reduced into original video data to video code flow.The resolution of the code stream that the central processing unit basis is obtained, automatic control figure signal shift switch, thereby entering corresponding D/A conversion chip that the control original video data can be correct.The D/A conversion chip converts original video data to analog signal, can deliver to monitor and show.So far, the utility model has been accomplished the decoding and the demonstration work of vision signal.

The utility model preferred embodiment just is used for helping to set forth the utility model.Preferred embodiment does not have all details of detailed descriptionthe, does not limit this utility model yet and is merely described embodiment.Obviously, according to the content of this specification, can do a lot of modifications and variation.These embodiment are chosen and specifically described to this specification, is principle and practical application in order to explain the utility model better, thereby person skilled can be utilized the utility model well under making.The utility model only receives the restriction of claims and four corner and equivalent.More than the disclosed several specific embodiments that are merely the application, but the application is not limited thereto, any those skilled in the art can think variation, all should drop in the application's the protection range.

Claims (1)

1. a novel multichannel is counted the Video Decoder of multiresolution; It is characterized in that, comprising: a CVBS output interface, the 2nd CVBS output interface, VGA output interface, a D/A converting unit, the 2nd D/A converting unit, digital signal diverter switch, the central processor unit that comprises acp chip, NE;

The output of said NE is connected with the input of central processor unit;

The output of said central processor unit is connected with the digital signal diverter switch;

Said digital signal diverter switch is connected with the input of a D/A converting unit, the 2nd D/A converting unit again simultaneously;

The output of the one D/A converting unit is connected with a CVBS output interface;

The output of the 2nd D/A converting unit connects the 2nd CVBS output interface and VGA output interface.

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