CN202488484U - Super Nyquist application device - Google Patents
Super Nyquist application device Download PDFInfo
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- CN202488484U CN202488484U CN2012201033672U CN201220103367U CN202488484U CN 202488484 U CN202488484 U CN 202488484U CN 2012201033672 U CN2012201033672 U CN 2012201033672U CN 201220103367 U CN201220103367 U CN 201220103367U CN 202488484 U CN202488484 U CN 202488484U
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Abstract
The utility model discloses a super Nyquist application device. A baseband signal is output to a DDS (Direct Digital Synthesis) circuit by a baseband signal receiving circuit; a clock signal of a frequency reference source is received by a differential LVPECL (Low-Voltage Positive-Referenced Emitter Coupled Logic) transmitter; a reference frequency is provided for the DDS circuit; a DDS internal register is configured to a singlechip; when the received signal is a low level, a frequency content of a Profile0 register is used as an output of the DDS circuit, and when the received signal is a high level, a frequency content of a Profile1 register is used as the output of the DDS circuit; and an out-of-band frequency component of the output of the DDS circuit is filtered out by a band-pass filter so as to obtain a 2CPFSK (2 Continuous Phase Frequency Shift Keying) modulating signal with the required frequency. According to the utility model, the direct output frequency can reach an L wave band or a higher wave band; the bandwidth and the transmission rate are improved; the up-conversion times of a common 2CPFSK signal transmitting device are reduced; and the size of the transmitting device is reduced.
Description
Technical field
The utility model relates to Digital Signal Processing, especially about realize the device of high speed 2CPFSK digital modulation based on DDS technology in the super Nyquist interval.
Background technology
At present; In the known unmanned plane data chainning system; The output of 2CPFSK digital modulation device is intermediate frequency 70MHz; Lower intermediate frequency has limited the bandwidth and the transmission rate of 2CPFSK digital modulation device, and the output frequency of the 2CPFSK modulator that for example in document " application of AD9854 in the unmanned aerial vehicle radio TT&C system ", provides is 70MHz, and the baseband signal bit rate is 2.048Mbps.Secondly, because the low up-conversion increased frequency that makes the 2CPFSK sender unit of intermediate frequency, the volume of emitter increases, the miniaturization Design of serious confining device limits its range of application, especially the narrow and small unmanned aerial vehicle onboard environment in space.
Summary of the invention
In order to overcome the deficiency that frequency is low, transmission rate is low of prior art 2CPFSK modulating device output; The high speed 2CPFSK digital modulation device that the utility model provides a kind of DDS of application technology to realize; This device is used the super Nyquist frequency signal of DDS, and directly output frequency can reach L-band (or higher), and improves bandwidth and transmission rate; Reduce the up-conversion number of times of the 2CPFSK sender unit of known intermediate frequency 70MHz, reduced the size of its emitter.
The utility model solves the technical scheme that its technical problem adopted: comprise baseband signal receiving circuit, DDS circuit, frequency reference source, difference LVPECL reflector, single-chip microcomputer and band pass filter.Said baseband signal receiving circuit is high speed signal receivers such as RS-422, RS-485, can also be the high-speed interface change-over circuit, requires the level of the port that baseband signal receiving circuit output port and DDS circuit connect compatible mutually.Baseband signal gets into the baseband signal receiving circuit, and the DDS circuit is received in the output of baseband signal receiving circuit.
The output in described frequency reference source connects difference LVPECL reflector, and the clock signal in difference LVPECL transmitter receipt frequency reference source also converts the output of difference LVPECL level to.Described difference LVPECL reflector connects the DDS circuit, for the DDS circuit provides reference frequency, in the DDS circuit, arrives the reference frequency frequency multiplication smaller or equal to the system clock of 1GHz frequency as the DDS circuit.Described DDS circuit is selected the special-purpose DDS integrated chip AD9957 of ADI company for use, the integrated 1GSPS sample rate of this DDS chip internal DAC.Described single-chip microcomputer is to be used for disposing DDS inner Profile0 register and Profile1 register; Single-chip microcomputer disposes the DDS chip operation in the single audio frequency pattern, and writes the hexadecimal data that 2CPFSK modulates two required frequencies respectively at Profile0 register and Profile1 register.The signal of described DDS circuit receiving baseband signal receiving circuit is selected the output of the frequency content of Profile0 register as the DDS circuit when receiving signal for low level; When receiving signal, select of the output of the frequency content of Profile1 register as the DDS circuit for high level.The input of described DDS circuit output tape splicing bandpass filter, the DDS circuit output signal of the outer frequency content of process band pass filter filtering band is the 2CPFSK modulation signal of required frequency.
The beneficial effect of the utility model is: owing to adopted system clock is the DDS chip of 1GHz, can in the Nyquist interval of DAC, realize the 2CPFSK modulation signal up to 400MHz; And can realize the 2CPFSK modulation signal of L-band (or higher) in the super Nyquist interval of DAC.The utility model has overcome the deficiency that intermediate frequency is low, transmission rate is low of prior art 2CPFSK modulating device output.
Description of drawings
Fig. 1 is the sketch map of the utility model;
Fig. 2 is that code check 33.6Mbps baseband signal is at the 2CPFSK of fundamental frequency 350MHz modulation spectrum figure;
Fig. 3 is the 2CPFSK modulation spectrum figure of code check 33.6Mbps baseband signal at the first image frequency 630MHz;
Fig. 4 is the 2CPFSK modulation spectrum figure of code check 33.6Mbps baseband signal at the second image frequency 1330MHz;
Fig. 5 is the 2CPFSK modulation spectrum figure of code check 33.6Mbps baseband signal at the 3rd image frequency 1610MHz;
Fig. 6 is that code check 67.2Mbps baseband signal is at the 2CPFSK of fundamental frequency 350MHz modulation spectrum figure;
Among Fig. 1,1-baseband signal, 2-baseband signal receiving circuit, 3-DDS circuit, 4-frequency reference source, 5-difference LVPECL reflector, 6-single-chip microcomputer, 7-band pass filter, 8-2CPFSK modulation signal.
Embodiment
The utility model solves the technical scheme that its technical problem adopted: comprise baseband signal receiving circuit, DDS circuit, frequency reference source, difference LVPECL reflector, single-chip microcomputer and band pass filter.Said baseband signal receiving circuit is high speed signal receivers such as RS-422, RS-485, can also be the high-speed interface change-over circuit, requires the level of the port that baseband signal receiving circuit output port and DDS circuit connect compatible mutually.Baseband signal gets into the baseband signal receiving circuit, and the DDS circuit is received in the output of baseband signal receiving circuit.
The output in described frequency reference source connects difference LVPECL reflector, and the clock signal in difference LVPECL transmitter receipt frequency reference source also converts the output of difference LVPECL level to.Described difference LVPECL reflector connects the DDS circuit, for the DDS circuit provides reference frequency, in the DDS circuit, arrives the reference frequency frequency multiplication smaller or equal to the system clock of 1GHz frequency as the DDS circuit.Described DDS circuit is selected the special-purpose DDS integrated chip AD9957 of ADI company for use, the integrated 1GSPS sample rate of this DDS chip internal DAC.Described single-chip microcomputer is to be used for disposing the DDS internal register, and single-chip microcomputer disposes the DDS chip operation in the single audio frequency pattern, and writes the hexadecimal data that 2CPFSK modulates two required frequencies respectively at Profile0 register and Profile1 register.The signal of described DDS circuit receiving baseband signal receiving circuit is selected the output of the frequency content of Profile0 register as the DDS circuit when receiving signal for low level; When receiving signal, select of the output of the frequency content of Profile1 register as the DDS circuit for high level.The input of described DDS circuit output tape splicing bandpass filter, the DDS circuit output signal of the outer frequency content of process band pass filter filtering band is the 2CPFSK modulation signal of required frequency.
Below in conjunction with accompanying drawing and embodiment the utility model is further specified.
Device embodiment: with reference to Fig. 1, the device of the utility model comprises baseband signal receiving circuit 2, DDS circuit 3, frequency reference source 4, difference LVPECL reflector 5, single-chip microcomputer 6, band pass filter 7.
Said baseband signal receiving circuit 2 connects DDS circuit 3.Described DDS circuit 3 connects difference LVPECL reflector 5, single-chip microcomputer 6 and band pass filter 7.Described difference LVPECL reflector 5 connects frequency reference source 4.
Described DDS circuit 3 is selected special-purpose DDS integrated chip AD9957 for use.Single-chip microcomputer 6 disposes the DDS chip operations in the single audio frequency pattern, and writes the hexadecimal data that 2CPFSK modulates two required frequencies respectively at Profile0 register and Profile1 register, and disposing AD9957 output center frequency here is 350MHz.The signal of DDS circuit 3 receiving baseband signal receiving circuits 2 is selected the output of the frequency content of Profile0 register as the DDS circuit when receiving signal for low level; When receiving signal, select of the output of the frequency content of Profile1 register as the DDS circuit for high level.Output tape splicing bandpass filter 7 inputs of DDS circuit 3, band pass filter 7 outputs are the 2CPFSK modulation signal 8 of required frequency.
Can know that by known DDS technology digital signal becomes analog signal through the DAC digital to analog converter at last.The signal frequency of DAC output is f
i=mf
s± f
o, (m=0,1,2 ...), f
sBe the sample rate of DAC, f
iBe the output frequency of expectation, f
oBe fundamental frequency.Require fundamental frequency less than 0.5f in theory
s, otherwise fundamental frequency and image frequency can be overlapping; On practical applications, consider the realization difficulty of image frequency rejects trap, general maximum fundamental frequency is chosen 0.4f
sf
s-f
oBe first image frequency, f
s+ f
oBe second image frequency, 2f
s-f
oBe the 3rd image frequency, by that analogy.Work as f
sBe 980MHz, when fundamental frequency was 350MHz, output spectrum modulation signal figure result saw Fig. 2～5.Fig. 2～5 have verified that output frequency has reached L-band, and Fig. 2～5 are respectively the 2CPFSK spectrum modulation signal figure of fundamental frequency 350MHz, the first image frequency 630MHz, the second image frequency 1330MHz and the 3rd image frequency 1610MHz, far above 70MHz.Fig. 6 be code check 67.2Mbps baseband signal at the 2CPFSK of fundamental frequency 350MHz spectrum modulation signal figure, verified the high speed transmission abilities of 2CPFSK digital modulation device.
Claims (3)
1. super Nyquist application apparatus; Comprise baseband signal receiving circuit, DDS circuit, frequency reference source, difference LVPECL reflector, single-chip microcomputer and band pass filter; It is characterized in that: baseband signal outputs to the DDS circuit through the baseband signal receiving circuit; The clock signal in difference LVPECL transmitter receipt frequency reference source also converts the output of difference LVPECL level to; For the DDS circuit provides reference frequency, in the DDS circuit, arrive the reference frequency frequency multiplication smaller or equal to the system clock of 1GHz frequency as the DDS circuit; Inner Profile0 register and the Profile1 register of single-chip microcomputer configuration DDS is operated in the single audio frequency pattern; And write the hexadecimal data of two required frequencies of 2CPFSK modulation respectively at Profile0 register and Profile1 register; When receiving signal, select of the output of the frequency content of Profile0 register, when receiving signal, select of the output of the frequency content of Profile1 register as the DDS circuit for high level as the DDS circuit for low level; The output of DDS circuit is the 2CPFSK modulation signal of required frequency through the outer frequency content of band pass filter filtering band.
2. super Nyquist application apparatus according to claim 1; It is characterized in that: described baseband signal receiving circuit is RS-422, RS-485 high speed signal receiver or high-speed interface change-over circuit, and baseband signal receiving circuit output port is compatible mutually with the level of the port that the DDS circuit connects.
3. super Nyquist application apparatus according to claim 1 is characterized in that: described DDS circuit is selected the special-purpose DDS integrated chip AD9957 of ADI company for use, the integrated 1GSPS sample rate of this DDS chip internal DAC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012201033672U CN202488484U (en) | 2012-03-19 | 2012-03-19 | Super Nyquist application device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012201033672U CN202488484U (en) | 2012-03-19 | 2012-03-19 | Super Nyquist application device |
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| Publication Number | Publication Date |
|---|---|
| CN202488484U true CN202488484U (en) | 2012-10-10 |
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|---|---|---|---|
| CN2012201033672U Expired - Fee Related CN202488484U (en) | 2012-03-19 | 2012-03-19 | Super Nyquist application device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102638428A (en) * | 2012-03-19 | 2012-08-15 | 西北工业大学 | 2CPFSK (continuous-phase frequency-shift keying) digital-modulation super-Nyquist application device |
-
2012
- 2012-03-19 CN CN2012201033672U patent/CN202488484U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102638428A (en) * | 2012-03-19 | 2012-08-15 | 西北工业大学 | 2CPFSK (continuous-phase frequency-shift keying) digital-modulation super-Nyquist application device |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121010 Termination date: 20150319 |
|
| EXPY | Termination of patent right or utility model |