CN202488484U - A kind of super Nyquist application device - Google Patents

Abstract

The utility model discloses a super Nyquist application device. A baseband signal is output to a DDS (Direct Digital Synthesis) circuit by a baseband signal receiving circuit; a clock signal of a frequency reference source is received by a differential LVPECL (Low-Voltage Positive-Referenced Emitter Coupled Logic) transmitter; a reference frequency is provided for the DDS circuit; a DDS internal register is configured to a singlechip; when the received signal is a low level, a frequency content of a Profile0 register is used as an output of the DDS circuit, and when the received signal is a high level, a frequency content of a Profile1 register is used as the output of the DDS circuit; and an out-of-band frequency component of the output of the DDS circuit is filtered out by a band-pass filter so as to obtain a 2CPFSK (2 Continuous Phase Frequency Shift Keying) modulating signal with the required frequency. According to the utility model, the direct output frequency can reach an L wave band or a higher wave band; the bandwidth and the transmission rate are improved; the up-conversion times of a common 2CPFSK signal transmitting device are reduced; and the size of the transmitting device is reduced.

Description

A kind of super Nyquist application device

technical field

The utility model relates to digital signal processing technology, in particular to a device for realizing high-speed 2CPFSK digital modulation based on DDS technology in the super Nyquist interval.

Background technique

At present, in the known UAV data link system, the output of the 2CPFSK digital modulation device is an intermediate frequency of 70MHz, and the lower intermediate frequency limits the bandwidth and transmission rate of the 2CPFSK digital modulation device. The output frequency of the 2CPFSK modulator given in "Application" is 70MHz, and the code rate of the baseband signal is 2.048Mbps. Secondly, due to the low intermediate frequency, the number of up-conversion times of the 2CPFSK signal transmitting device increases, and the volume of the transmitting device increases, which seriously restricts the miniaturization design of the device and limits its application range, especially in the UAV airborne environment with small space.

Contents of the invention

In order to overcome the shortcomings of the low output frequency and low transmission rate of the 2CPFSK modulation device in the prior art, the utility model provides a high-speed 2CPFSK digital modulation device realized by using DDS technology. The device uses the super-Nyquist frequency signal of DDS to directly The output frequency can reach the L band (or higher), and the bandwidth and the transmission rate are increased, the number of up-conversion times of the known 2CPFSK signal transmitting device with an intermediate frequency of 70MHz is reduced, and the size of the transmitting device is reduced.

The technical scheme adopted by the utility model to solve the technical problem is: comprising a baseband signal receiving circuit, a DDS circuit, a frequency reference source, a differential LVPECL transmitter, a single-chip microcomputer and a band-pass filter. The baseband signal receiving circuit is a high-speed signal receiver such as RS-422, RS-485, or a high-speed interface conversion circuit, which requires that the output port of the baseband signal receiving circuit is compatible with the level of the port connected to the DDS circuit. The baseband signal enters the baseband signal receiving circuit, and the output of the baseband signal receiving circuit is connected to the DDS circuit.

The output of the frequency reference source is connected to a differential LVPECL transmitter, and the differential LVPECL transmitter receives the clock signal of the frequency reference source and converts it into a differential LVPECL level output. The differential LVPECL transmitter is connected to the DDS circuit to provide a reference frequency for the DDS circuit, and the reference frequency is multiplied to a frequency less than or equal to 1 GHz in the DDS circuit as a system clock of the DDS circuit. The DDS circuit is selected as the special-purpose DDS integrated chip AD9957 of ADI Company, and the DDS chip integrates a DAC with a sampling rate of 1GSPS. The single-chip microcomputer is used to configure the Profile0 register and the Profile1 register inside the DDS. The single-chip microcomputer configures the DDS chip to work in the single audio mode, and writes the hexadecimal numbers of the two frequencies required for 2CPFSK modulation in the Profile0 register and the Profile1 register respectively. data. The DDS circuit receives the signal of the baseband signal receiving circuit, and when the received signal is a low level, the frequency content of the Profile0 register is selected as the output of the DDS circuit; when the received signal is a high level, the frequency content of the Profile1 register is selected as the output of the DDS circuit . The output of the DDS circuit is connected to the input of the band-pass filter, and the output signal of the DDS circuit after the out-of-band frequency components are filtered out by the band-pass filter is the 2CPFSK modulation signal of the required frequency.

The beneficial effect of the utility model is: because adopting the DDS chip that the system clock is 1GHz, can realize the 2CPFSK modulation signal up to 400MHz in the Nyquist interval of DAC; Band (or higher) 2CPFSK modulated signal. The utility model overcomes the shortcomings of low intermediate frequency and low transmission rate output by the 2CPFSK modulation device in the prior art.

Description of drawings

Fig. 1 is the schematic diagram of the utility model;

Fig. 2 is a 2CPFSK modulation spectrum diagram of a code rate 33.6Mbps baseband signal at a base frequency of 350MHz;

Fig. 3 is the 2CPFSK modulation spectrum diagram of the code rate 33.6Mbps baseband signal at the first image frequency 630MHz;

Fig. 4 is the 2CPFSK modulation spectrum diagram of the code rate 33.6Mbps baseband signal at the second image frequency 1330MHz;

Fig. 5 is the 2CPFSK modulation spectrum diagram of the code rate 33.6Mbps baseband signal at the third image frequency 1610MHz;

Fig. 6 is a 2CPFSK modulation spectrum diagram of a code rate 67.2Mbps baseband signal at a base frequency of 350MHz;

In Figure 1, 1-baseband signal, 2-baseband signal receiving circuit, 3-DDS circuit, 4-frequency reference source, 5-differential LVPECL transmitter, 6-microcontroller, 7-bandpass filter, 8-2CPFSK modulation signal .

Detailed ways

The technical scheme adopted by the utility model to solve the technical problem is: comprising a baseband signal receiving circuit, a DDS circuit, a frequency reference source, a differential LVPECL transmitter, a single-chip microcomputer and a band-pass filter. The baseband signal receiving circuit is a high-speed signal receiver such as RS-422, RS-485, or a high-speed interface conversion circuit, which requires that the output port of the baseband signal receiving circuit is compatible with the level of the port connected to the DDS circuit. The baseband signal enters the baseband signal receiving circuit, and the output of the baseband signal receiving circuit is connected to the DDS circuit.

The output of the frequency reference source is connected to a differential LVPECL transmitter, and the differential LVPECL transmitter receives the clock signal of the frequency reference source and converts it into a differential LVPECL level output. The differential LVPECL transmitter is connected to the DDS circuit to provide a reference frequency for the DDS circuit, and the reference frequency is multiplied to a frequency less than or equal to 1 GHz in the DDS circuit as a system clock of the DDS circuit. The DDS circuit is selected as the special-purpose DDS integrated chip AD9957 of ADI Company, and the DDS chip integrates a DAC with a sampling rate of 1GSPS. Described single-chip microcomputer is used for disposing DDS internal register, and single-chip microcomputer configuration DDS chip works in monotone mode, and writes the hexadecimal data of two frequencies required for 2CPFSK modulation in Profile0 register and Profile1 register respectively. The DDS circuit receives the signal of the baseband signal receiving circuit, and when the received signal is a low level, the frequency content of the Profile0 register is selected as the output of the DDS circuit; when the received signal is a high level, the frequency content of the Profile1 register is selected as the output of the DDS circuit . The output of the DDS circuit is connected to the input of the band-pass filter, and the output signal of the DDS circuit after the out-of-band frequency components are filtered out by the band-pass filter is the 2CPFSK modulation signal of the required frequency.

Below in conjunction with accompanying drawing and embodiment the utility model is further described.

Device embodiment: with reference to Fig. 1, the device of the present utility model comprises baseband signal receiving circuit 2, DDS circuit 3, frequency reference source 4, differential LVPECL transmitter 5, single-chip microcomputer 6, band-pass filter 7.

The baseband signal receiving circuit 2 is connected to the DDS circuit 3 . The DDS circuit 3 is connected to a differential LVPECL transmitter 5 , a single-chip microcomputer 6 and a bandpass filter 7 . The differential LVPECL transmitter 5 is connected to the frequency reference source 4 .

The baseband signal 1 enters the receiving end of the baseband signal receiving circuit 2, and the output terminal of the baseband signal receiving circuit 2 is connected to the Pin 54 of the DDS circuit 3. The Pin 79 of the DDS circuit 3 is terminated with a 24.9 ohm resistor, and the Pin 80 is connected to the band-pass filter 7; the function of the band-pass filter 7 is to select the required fundamental frequency or mirror frequency and suppress other frequency components . The output frequency of the frequency reference source 4 is 20MHz, and the output waveform is 3.3V HCMOS level. The differential LVPECL transmitter 5 receives the clock signal of the frequency reference source 4, and the differential LVPECL output terminal of the differential LVPECL transmitter 5 is connected to the Pin 90 and Pin 91 pins of the DDS circuit 3 to provide the reference frequency for the DDS circuit 3, and in The DDS circuit multiplies the frequency within 3 to 980MHz as the system clock. The single-chip microcomputer 6 completes the internal register configuration of the DDS circuit 3 .

Described DDS circuit 3 selects special-purpose DDS integrated chip AD9957 for use. Single-chip microcomputer 6 configures the DDS chip to work in single audio mode, and writes the hexadecimal data of the two frequencies required for 2CPFSK modulation in the Profile0 register and Profile1 register respectively. Here, the AD9957 output center frequency is configured as 350MHz. The DDS circuit 3 receives the signal of the baseband signal receiving circuit 2, and when the received signal is low, selects the frequency content of the Profile0 register as the output of the DDS circuit; when the received signal is high, selects the frequency content of the Profile1 register as the output of the DDS circuit. The output of the DDS circuit 3 is connected to the input of the band-pass filter 7, and the output of the band-pass filter 7 is the 2CPFSK modulation signal 8 of the required frequency.

According to the known DDS technology, the digital signal is finally converted into an analog signal through a DAC digital-to-analog converter. The signal frequency output by the DAC is f _i =mf _s ±f _o , (m=0, 1, 2,...), f _s is the sampling rate of the DAC, f _i is the desired output frequency, and f _o is the fundamental frequency . Theoretically, the fundamental frequency is required to be less than 0.5f _s , otherwise the fundamental frequency and the image frequency will overlap; in engineering applications, considering the difficulty of realizing the image frequency suppression filter, generally the maximum fundamental frequency is selected as 0.4f _s . f _s -f _o is the first mirror frequency, f _s +f _o is the second mirror frequency, 2f _s -f _o is the third mirror frequency, and so on. When f _s is 980MHz and the fundamental frequency is 350MHz, the output modulation signal spectrum results are shown in Fig. 2-5. Figures 2 to 5 verify that the output frequency has reached the L-band. Figures 2 to 5 are the spectrum diagrams of 2CPFSK modulation signals with a base frequency of 350MHz, a first image frequency of 630MHz, a second image frequency of 1330MHz, and a third image frequency of 1610MHz, which are much higher than 70MHz. Fig. 6 is a spectrum diagram of a 2CPFSK modulation signal with a code rate of 67.2Mbps baseband signal at a base frequency of 350MHz, which verifies the high-speed transmission capability of the 2CPFSK digital modulation device.

Claims (3)

1. super Nyquist application apparatus; Comprise baseband signal receiving circuit, DDS circuit, frequency reference source, difference LVPECL reflector, single-chip microcomputer and band pass filter; It is characterized in that: baseband signal outputs to the DDS circuit through the baseband signal receiving circuit; The clock signal in difference LVPECL transmitter receipt frequency reference source also converts the output of difference LVPECL level to; For the DDS circuit provides reference frequency, in the DDS circuit, arrive the reference frequency frequency multiplication smaller or equal to the system clock of 1GHz frequency as the DDS circuit; Inner Profile0 register and the Profile1 register of single-chip microcomputer configuration DDS is operated in the single audio frequency pattern; And write the hexadecimal data of two required frequencies of 2CPFSK modulation respectively at Profile0 register and Profile1 register; When receiving signal, select of the output of the frequency content of Profile0 register, when receiving signal, select of the output of the frequency content of Profile1 register as the DDS circuit for high level as the DDS circuit for low level; The output of DDS circuit is the 2CPFSK modulation signal of required frequency through the outer frequency content of band pass filter filtering band.

2. super Nyquist application apparatus according to claim 1; It is characterized in that: described baseband signal receiving circuit is RS-422, RS-485 high speed signal receiver or high-speed interface change-over circuit, and baseband signal receiving circuit output port is compatible mutually with the level of the port that the DDS circuit connects.

3. super Nyquist application apparatus according to claim 1 is characterized in that: described DDS circuit is selected the special-purpose DDS integrated chip AD9957 of ADI company for use, the integrated 1GSPS sample rate of this DDS chip internal DAC.

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