CN202473905U - Wafer level columnar bump packaging structure - Google Patents
Wafer level columnar bump packaging structure Download PDFInfo
- Publication number
- CN202473905U CN202473905U CN 201120535131 CN201120535131U CN202473905U CN 202473905 U CN202473905 U CN 202473905U CN 201120535131 CN201120535131 CN 201120535131 CN 201120535131 U CN201120535131 U CN 201120535131U CN 202473905 U CN202473905 U CN 202473905U
- Authority
- CN
- China
- Prior art keywords
- layer
- wafer level
- chip
- metal
- salient point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A wafer level columnar bump packaging structure comprises a chip, a connecting layer and a solder bump; wherein, an upper surface of the chip is provided with a pad and a passivation layer, the passivation layer is covered on the upper surface of the chip except for the pad; a bottom of the connecting layer is arranged on the pad of the chip, a top of the connecting layer is provided with the solder bump; the connecting layer comprises a heatproof metal layer, a metal soakage layer, an adhesive layer and a barrier layer successively from bottom to top; the material of the adhesive layer is copper, and the material of the barrier layer is nickel. The wafer level columnar bump packaging structure of the utility model raises electrical performance and reliability of a product, and is suitable for the chip level package with the characteristics of pad close interval and multiple output functions.
Description
Technical field
The present invention relates to the semiconductor packages field, relate in particular to the encapsulation of wafer level size (Wafer Level chip Scale Package, encapsulating structure WLCSP).
Background technology
In recent years, because the microcircuit of chip is made towards the high integration development, therefore, its Chip Packaging also needs to develop to high power, high density, direction frivolous and microminiaturization.Chip Packaging is exactly after chip manufacturing is accomplished, with materials such as plastic cement or Tao Ci, chip to be wrapped in wherein, to reach the protection chip, makes chip not damaged by extraneous steam and mechanicalness.The main function of Chip Packaging has electric energy to transmit (Power Distribution) respectively, signal transmits (Signal Distribution), heat abstraction (Heat Dissipation) and protection support (Protection and Support).
Because the requirement of electronic product now is compact and high integration, therefore can makes and the production of integrated circuits miniaturization cause the logic that comprises in the chip to increase; And further make chip I/O (input/output) pin number increase; And be to cooperate these demands, produced many different packaged types, for example; BGA Package (Ball grid array; BGA), chip size packages (Chip Scale Package, CSP), multi-chip module encapsulation (Multi Chip Module package, MCM package), flip-over type encapsulation (Flip Chip Package), coil type encapsulation (Tape Carrier Package; TCP) and wafer level packaging (Wafer Level Package, WLP) etc.
No matter with the method for packing of which kind of form, most method for packing all is disk to be separated into independently accomplish the program that encapsulates again behind the chip.And wafer level packaging is a trend in the method for packaging semiconductor; Wafer level packaging is an encapsulated object with the full wafer disk; Thereby packaging and testing all need do not cutting the preceding completion of disk as yet; Be the encapsulation technology that a kind of height is integrated, so can save making such as filler, assembling, glutinous crystalline substance and routing, therefore can reduce cost of labor in a large number and shorten manufacturing time.
Application number is the formation method that 200410049093.3 Chinese patent has been introduced a kind of solder bump.Figure 1A-Fig. 1 F is existing solder bump forming process sketch map.Shown in Figure 1A, form one deck passivation layer 106 on the substrate 102 of pad 104.Then, deposit one deck heat resistant metal layer 108 (being generally chromium Cr or titanium Ti) and metal are invaded profit layer 110 (being generally copper Cu) in succession on passivation layer 106 surfaces of pad 104, shown in Figure 1B.Be coated with photoresist 112 and patterning photoresist then and form opening 114 in the pad relevant position, shown in Fig. 1 C.Then, shown in Fig. 1 D, packing material is the scolder of tin (Sn) or tin silver (SnAg) in opening 114, just formed the mushroom-shaped solder bump 120 shown in Fig. 1 E after removing photoresist 112.Etching heat resistant metal layer 108 is invaded profit layer 110 with metal afterwards, through the termination electrode reflux technique solder bump is melted the ball-type solder bump 120 shown in Fig. 1 F at last.
In the wafer level packaging process that prior art forms, contact because the solder bump material is directly invaded the profit layer with metal, metal is invaded the copper-base that moistens layer and is prone to be diffused in the tin of solder bump and forms signal bronze, influences welding quality.Simultaneously, metal invade form scolder on the profit layer before, exposed invade the oxidation and the solder bump performance of follow-up formation and reliability are reduced easily of profit layer.
The utility model content
The problem that the utility model solves provides a kind of wafer level column salient point encapsulating structure, prevents that chip electrical property and reliability from reducing.
For addressing the above problem, the utility model provides a kind of wafer level column salient point encapsulating structure, comprises chip, articulamentum and solder bump; The upper surface of said chip is provided with pad and passivation layer, and said passivation layer is overlying on the upper surface beyond the chip bonding pad; The bottom of said articulamentum places on the bonding pads, and the top of articulamentum is provided with solder bump; Said articulamentum comprises successively up that from the bottom heat resistant metal layer, metal invade profit layer, adhesion layer and barrier layer; The material of said adhesion layer is a copper, and the material on said barrier layer is a nickel.
Alternatively, the material of said heat resistant metal layer is titanium, chromium or tantalum.
Alternatively, to invade the material of profit layer be copper, aluminium or nickel to said metal.
Alternatively, the material of said adhesion layer is a copper.
Alternatively, the thickness of said copper adhesion layer is 5-60 μ m.
Alternatively, the material on said barrier layer is a nickel.
Alternatively, the thickness on said nickel barrier layer is 1.5-3 μ m.
Alternatively, be formed with solder cream on the said barrier layer, the material of said solder cream is pure tin or ashbury metal.
Alternatively, the thickness of said solder cream is 5-70 μ m.
Adhesion layer (Cu) spatially provides enough material space, solder bump can be placed on the adhesion layer securely and can not depart from; Also just because of the column structure of adhesion layer makes the size of solder bump be able to dwindle; In guaranteeing the final products welding process under the prerequisite of physical connection reliability; Promote the function number outbound port number in the unit space, more can satisfy the close spacing of chip bonding pad, the many package requirements of function output.
The suitable barrier layer (Ni) of thickness can avoid self because of diffusion effect and disappearance on the one hand, and then stops scolder and metal to invade between the profit layer hole that the formation because of intermetallic compound produces effectively; Be unlikely to simultaneously to cause resistivity to rise again and influence the electric heating property of product because of the nickel barrier layer is blocked up.
Description of drawings
Figure 1A to Fig. 1 F is existing solder bump forming process sketch map;
Fig. 2 is the sketch map of the utility model wafer level column salient point encapsulating structure;
Fig. 3 is the embodiment flow chart that the utility model forms wafer level column salient point encapsulating structure;
Fig. 4 A to Fig. 4 G is the process schematic representation that the utility model forms the embodiment of wafer level column salient point encapsulating structure.
Embodiment
Below in conjunction with accompanying drawing the embodiment of the utility model is done detailed explanation.
Fig. 2 is the sketch map of wafer level column salient point encapsulating structure of the present invention, and said encapsulating structure comprises: chip 300, articulamentum and solder bump 308b; The upper surface of said chip 300 is provided with pad 301 and passivation layer 302, and said passivation layer 302 is overlying on the upper surface beyond chip 300 pads 301; The bottom of said articulamentum places on the pad 301 of chip 300, and the top of articulamentum is provided with solder bump 308b; Said articulamentum up comprises heat resistant metal layer 303, metal infiltrating layer 304, adhesion layer 306 and barrier layer 307 successively from the bottom; The material of said heat resistant metal layer 303 is titanium, chromium, tantalum or their combination; The material of said metal infiltrating layer 304 is copper, aluminium, nickel or their combination; Said adhesion layer 306 is the copper layer of 5～60 μ m for thickness; Said barrier layer 307 is the nickel dam of 1.5～3 μ m for thickness; The thickness of said solder bump 308b is 5～70 μ m, and the material of solder bump 308b is pure tin or ashbury metal, like sn-ag alloy, gun-metal, SAC alloy etc.
In the above-mentioned encapsulating structure, articulamentum spatially provides enough material space, solder bump can be placed on the articulamentum securely and can not depart from; Also just because of the column structure of articulamentum makes the size of solder bump be able to dwindle; In guaranteeing the final products welding process under the prerequisite of physical connection reliability; Promote the function number outbound port number in the unit space, more can satisfy the close spacing of chip bonding pad, the many package requirements of function output.
In the articulamentum then can avoid self disappearing because of diffusion effect in the suitable nickel barrier layer of thickness, and then the hole that stops between scolder and the metal infiltrating layer formation because of intermetallic compound to produce effectively; Be unlikely to simultaneously to cause resistivity to rise again and influence the electric heating property of product because of the nickel barrier layer is blocked up.
For further specifying the advantage of encapsulating structure of the present invention, encapsulating structure of the present invention is done further to introduce below in conjunction with a concrete method for packing embodiment.
As shown in Figure 3, in one embodiment of the invention, a kind of wafer level column salient point method for packing is provided, comprise step:
S101 forms heat resistant metal layer and metal infiltrating layer successively on bonding pads and passivation layer;
S102 forms photoresist on metal infiltrating layer, said photoresist is provided with the metal infiltrating layer that opening exposes the chip bonding pad top;
S103 forms adhesion layer and barrier layer on the metal infiltrating layer in above-mentioned opening;
S104 forms solder cream on the barrier layer;
S105 removes photoresist;
S106, heat resistant metal layer on the etch passivation layer and metal infiltrating layer to passivation layer is exposed;
S107, reflux solder cream forms solder bump.
At first execution in step S101 forms heat resistant metal layer and metal infiltrating layer successively on bonding pads and passivation layer, forms the structure shown in Fig. 4 A.
In this step, chip 300 is provided with pad 301 and passivation layer 302, and pad 301 is function lead-out terminals of chip 300, and finally realizes the conduction transition of electrical functionality through the column salient point of follow-up formation; The material of passivation layer 302 comprises dielectric material or their mixtures such as silica, silicon nitride, silicon oxynitride, polyimides, benzene three polybutene, is used for protecting the circuit of chip 300.
Need to prove that said bonding pads and passivation layer can be the initial pad and the initial passivation of chip, also can be transition pad, the passivation layer that forms according to circuit layout-design needs; The mode that forms transition pad, passivation layer mainly is to adopt the Wiring technique technology again, connects up through one or more layers again initial pad, passivation layer are reprinted on transition pad, the passivation layer.The said technology of Wiring technique again has been well known to those skilled in the art for existing maturation process, repeats no more at this.
In the present embodiment, the material of said heat resistant metal layer 303 can be constituting of titanium Ti, chromium Cr, tantalum Ta or they, and the present invention is preferably Ti.The material of said metal infiltrating layer 304 can be constituting of a kind of in copper Cu, aluminium Al, the nickel or they, and wherein more excellent metal infiltrating layer 304 is Cu.Heat resistant metal layer 303 constitutes the Seed Layer of final structure with metal infiltrating layer 304.The method of said heat resistant metal layer 303 and metal infiltrating layer 304 can adopt the method for existing evaporation or sputter or physical vapour deposition (PVD) equally, and wherein more excellent method is sputter.Certainly; Common practise according to those skilled in the art; The method that forms is not limited only to sputtering method, and other methods that are suitable for all can be applicable to the present invention, and the thickness of heat resistant metal layer 303 that forms and metal infiltrating layer 304 also is to decide according to the process requirements of reality.
Implementation step S102 forms photoresist on metal infiltrating layer then, and said photoresist is provided with the metal infiltrating layer that opening exposes the chip bonding pad top, forms the structure shown in Fig. 4 B.
In the present embodiment, the method that forms photoresist 305 can be a rotary coating, and the concrete steps of these methods are well known to those skilled in the art, repeat no more at this.After forming photoresist 305, specifically can define the shape of pad 301, make to form opening in the photoresist 305 to expose the metal infiltrating layer 304 on the pad 301 through existing photoetching development technology.
Implementation step S103 forms adhesion layer and barrier layer successively on the metal infiltrating layer in above-mentioned opening then, forms the structure shown in Fig. 4 C.
In this step, be mask with remaining photoresist 305 on the chip 300, in the opening of the photoresist 305 that in last step, formed, metal infiltrating layer 304 above, form adhesion layer 306 and barrier layer 307 successively, concrete technology can be through with the mode of electroplating.Certainly, according to those skilled in the art's common practise, the method for formation is not limited only to electroplate, and other methods that are suitable for all can be applicable to the present invention.The material of said adhesion layer 306 is copper Cu, and the material on barrier layer 307 is a nickel.
In the present embodiment, the thickness of adhesion layer 306 bronze medals is 5～60 μ m, and concrete thickness is 5 μ m, 10 μ m, 15 μ m, 20 μ m, 25 μ m, 30 μ m, 35 μ m, 40 μ m, 45 μ m, 50 μ m, 55 μ m or 60 μ m etc.Adhesion layer 306 is the column structure main body of column salient point for final electrically lead-out terminal.Adhesion layer 306 spatially provides enough material space; Guaranteed follow-uply can place securely on the adhesion layer 306 and can not depart from by the reflux solder bump 308b form of solder cream 308a, also improved simultaneously and solder bump 308b between adhesion.
In the present embodiment, the thickness of barrier layer 307 nickel is 1.5 μ m～3 μ m, and concrete thickness is 1.5 μ m, 2 μ m, 2.5 μ m or 3 μ m etc.Acting as in diffuse to the metal infiltrating layer 304 that prevents follow-up formation solder bump of barrier layer 307; When Ni layer thickness during less than 1.5 μ m; Ni finally can disappear because of the diffusion effect between adjacent metal, and then can't stop effectively that follow-up solder bump is diffused in the metal infiltrating layer 304; When Ni layer thickness during, can cause the resistivity rising because of the electric heating property of Ni metal itself is relatively poor, and then influence the electric heating property of final products greater than 3 μ m.
So far, promptly formed the articulamentum that is made up of heat resistant metal layer 303, metal infiltrating layer 304, adhesion layer 306 and barrier layer 307, articulamentum is the cylinder part in the final column bump structure, electrically connects pad 301 and solder bump 308b.
Implementation step S104 forms solder cream on the barrier layer then, forms the structure shown in Fig. 4 D.
In this step, be mask still with photoresist 305, on barrier layer 307, form solder cream 308a, the material that forms said solder cream 308a is pure tin or ashbury metal, like sn-ag alloy, gun-metal, SAC alloy etc.The method that forms solder cream 308a can be metallide, sputter, screen painting or directly implant prefabricated modes such as solder bump that the concrete steps of these methods are well known to those skilled in the art, repeat no more at this.Because the column structure that above-mentioned steps forms; Can significantly reduce the use amount of solder cream 308a; Practiced thrift material cost on the one hand; The more important thing is that the solder bump 308b size that a small amount of solder cream 308a refluxes is less, can satisfy the application demand of greater functionality output point in pad 301 close spacings or the same space.
Then implementation step S105 removes photoresist, forms the structure shown in Fig. 4 E.
After accomplishing above-mentioned operation, photoresist 305 can have been removed, and can use wet method or the mode peeled off is removed, and the concrete steps of these methods are well known to those skilled in the art, repeat no more at this.
Implementation step S106 then, heat resistant metal layer on the etch passivation layer and metal infiltrating layer to passivation layer is exposed, forms the structure shown in Fig. 4 F.
In the present embodiment, specifically can remove the metal infiltrating layer 304 and heat resistant metal layer 303 on chip 300 surfaces beyond the solder cream 308a, thereby expose passivation layer 302 through the method for spraying acid solution or wafer is soaked in the acid solution.
At last, implementation step S107, reflux solder cream forms solder bump, forms the wafer level column salient point encapsulating structure shown in Fig. 4 G.
In the present embodiment, the thickness of solder bump 308b is 5 μ m～70 μ m, and concrete thickness is 5 μ m, 10 μ m, 15 μ m, 20 μ m, 25 μ m, 30 μ m, 35 μ m, 40 μ m, 45 μ m, 50 μ m, 55 μ m, 60 μ m, 65 μ m or 70 μ m etc. for example.Form solder bump 308b through backflow heat fused solder cream 308a, finally realized the function pads 301 of chip 300 is drawn out to the encapsulation transition on the solder bump 308b.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (9)
1. a wafer level column salient point encapsulating structure is characterized in that: comprise chip, articulamentum and solder bump; The upper surface of said chip is provided with pad and passivation layer, and said passivation layer is overlying on the upper surface beyond the chip bonding pad; The bottom of said articulamentum places on the bonding pads, and the top of articulamentum is provided with solder bump; Said articulamentum comprises successively up that from the bottom heat resistant metal layer, metal invade profit layer, adhesion layer and barrier layer; The material of said adhesion layer is a copper, and the material on said barrier layer is a nickel.
2. a kind of wafer level column salient point encapsulating structure according to claim 1 is characterized in that the material of said heat resistant metal layer is titanium, chromium or tantalum.
3. a kind of wafer level column salient point encapsulating structure according to claim 1 is characterized in that, the material that said metal is invaded the profit layer is copper, aluminium or nickel.
4. a kind of wafer level column salient point encapsulating structure according to claim 1 is characterized in that the material of said adhesion layer is a copper.
5. a kind of wafer level column salient point encapsulating structure according to claim 4 is characterized in that the thickness of said copper adhesion layer is 5-60 μ m.
6. a kind of wafer level column salient point encapsulating structure according to claim 1 is characterized in that the material on said barrier layer is a nickel.
7. a kind of wafer level column salient point encapsulating structure according to claim 6 is characterized in that the thickness on said nickel barrier layer is 1.5-3 μ m.
8. a kind of wafer level column salient point encapsulating structure according to claim 1 is characterized in that be formed with solder cream on the said barrier layer, the material of said solder cream is pure tin or ashbury metal.
9. a kind of wafer level column salient point encapsulating structure according to claim 8 is characterized in that the thickness of said solder cream is 5-70 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120535131 CN202473905U (en) | 2011-12-19 | 2011-12-19 | Wafer level columnar bump packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120535131 CN202473905U (en) | 2011-12-19 | 2011-12-19 | Wafer level columnar bump packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202473905U true CN202473905U (en) | 2012-10-03 |
Family
ID=46922048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120535131 Expired - Lifetime CN202473905U (en) | 2011-12-19 | 2011-12-19 | Wafer level columnar bump packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202473905U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104992936A (en) * | 2015-05-19 | 2015-10-21 | 南通富士通微电子股份有限公司 | Wafer level chip packaging structure |
-
2011
- 2011-12-19 CN CN 201120535131 patent/CN202473905U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104992936A (en) * | 2015-05-19 | 2015-10-21 | 南通富士通微电子股份有限公司 | Wafer level chip packaging structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102496580B (en) | A kind of formation method of solder bump | |
| CN102201351B (en) | Semiconductor device and the method forming the double UBM structures connected for unleaded projection | |
| CN103515260B (en) | Encapsulation and forming method thereof in encapsulation | |
| CN102956590B (en) | For reducing the pseudo-inversed-chip lug of stress | |
| CN102496606B (en) | High-reliability wafer level cylindrical bump packaging structure | |
| CN102163561B (en) | Semiconducter device and use same vehicle form the method for TMV and TSV in WLCSP | |
| CN102130101B (en) | Form district around projection and form semiconductor device and the method for the projection cube structure with multilamellar UBM | |
| US10043768B2 (en) | Semiconductor device and method of manufacture thereof | |
| CN103915353B (en) | Semiconductor devices and the method for forming embedded wafer-level chip scale package using standard carriers | |
| TWI313037B (en) | Chip scale package structure and method for fabricating the same | |
| CN102437066A (en) | High-reliability wafer-level columnar bump packaging method | |
| CN100587931C (en) | Redistribution layer for wafer-level chip scale package and method therefor | |
| CN107039337A (en) | With the method and semiconductor devices of the semiconductor element formation DCALGA encapsulation for having microtrabeculae | |
| CN102543766A (en) | Columnar bump packaging process | |
| TW201125073A (en) | Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate | |
| KR20020044590A (en) | Metal redistribution layer having solderable pads and wire bondable pads | |
| CN102496604A (en) | High-reliability chip-scale packaging structure | |
| CN102437065A (en) | High-reliability chip scale packaging method | |
| CN102456650A (en) | Conductive feature for semiconductor substrate and method of manufacture | |
| CN102446780A (en) | Wafer-level packaging method | |
| KR100842921B1 (en) | Method for fabricating of semiconductor package | |
| CN102437135A (en) | Wafer-level columnar bump packaging structure | |
| CN102543898A (en) | Cylindrical bump packaging structure | |
| US7518211B2 (en) | Chip and package structure | |
| CN202502990U (en) | Highly reliable chip-level package structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information |
Inventor after: Shi Lei Inventor before: Ding Wanchun |
|
| COR | Change of bibliographic data | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee after: Tongfu Microelectronics Co., Ltd. Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288 Patentee before: Fujitsu Microelectronics Co., Ltd., Nantong |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121003 |