CN202473897U - System integrated circuit packaging structure - Google Patents
System integrated circuit packaging structure Download PDFInfo
- Publication number
- CN202473897U CN202473897U CN 201220061366 CN201220061366U CN202473897U CN 202473897 U CN202473897 U CN 202473897U CN 201220061366 CN201220061366 CN 201220061366 CN 201220061366 U CN201220061366 U CN 201220061366U CN 202473897 U CN202473897 U CN 202473897U
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- Prior art keywords
- ceramic substrate
- integrated circuit
- socket
- underframe
- system integrated
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Abstract
The utility model discloses a system integrated circuit packaging structure which comprises a ceramic substrate, an upper frame, an upper plate, a lower frame, a lower cover plate and a socket, wherein the ceramic substrate is a multi-layer ceramic substrate in which metal conduction bands are arranged to serve as interconnection lines of the circuit; the upper and the lower frames are respectively welded on the upper surface and the lower surface of the ceramic substrate; and the socket is welded on the upper surface or the lower surface of the ceramic substrate, and is positioned on the outer side of the upper frame or the lower frame. According to the system integrated circuit packaging structure, the ceramic substrate is integrally packaged, both a double-faced cavity and miniature socket I/O (Input/Output) pins are arranged, the purposes of high integration and multi-pin packaging of the system are achieved, and the problems that system integration circuit is big in integration and the number of the I/O pins is large are solved.
Description
Technical field
The utility model belongs to microelectronic, relates to a kind of system integrated circuit encapsulating structure, especially a kind of hybrid-intergated-circuit technique that relates to bare chip, hybrid integration technology, process materials.
Background technology
A distinguishing feature of the system integration is that integrated scale is big, and integration density is high, shows as many, the integrated a large amount of ultra-large and large scale integrated chips of component number, and the thing followed is that the I/O pin number of circuit also is multiplied.System integrated circuit all is a special circuit generally, does not have standard packaging, need make the system integration demonstrate the diversity and the complexity of encapsulating structure according to concrete integrated Demand Design encapsulation.The encapsulation of the system integration (SiP) circuit of high density, big cavity, multilead is the difficult point that the system integration (SiP) circuit design is made always.
The utility model content
The purpose of the utility model is to overcome the shortcoming and defect of above-mentioned prior art, and a kind of system integrated circuit encapsulating structure is provided, and has solved the problem that the system integrated circuit integrated level is big, the I/O pin number is many.
The purpose of the utility model solves through following technical scheme:
A kind of system integrated circuit encapsulating structure comprises ceramic substrate, upper frame, upper cover plate, underframe, lower cover and socket, and said ceramic substrate is a multilayer ceramic substrate, and there is the interconnection line of metal conduction band as circuit ceramic substrate inside; The ceramic substrate upper surface is welded with upper frame, the ceramic substrate lower surface is welded with underframe, and the upper surface or the lower surface of ceramic substrate are welded with socket, and socket is positioned at the outside of upper frame or underframe; Said upper frame is provided with upper cover plate, and upper surface, upper frame and upper cover plate form airtight upper cavity; Said underframe is provided with lower cover, and lower surface, underframe and lower cover form airtight lower chamber.
Said ceramic substrate is LTCC (LTCC) substrate.
The components and parts bare chip is installed in said upper cavity and the lower chamber.
Said upper frame, upper cover plate, underframe and lower cover employing can be cut down material and process, and it has close thermal coefficient of expansion with the ceramic substrate that uses.
Welding together of said socket and ceramic substrate, each contact pin is connected with inside circuit according to design on the standard socket, forms the input and output pin of circuit.
The system integrated circuit encapsulating structure of the utility model, make ceramic substrate encapsulation integrated, have two-sided cavity and mini jack I/O pin, reached that system high-density is integrated, the encapsulation of many pins.
Description of drawings
Fig. 1 is the structural representation of the system integration encapsulating structure of the utility model;
Fig. 2 is the system integration encapsulating structure left view of the utility model;
Fig. 3 is the system integration encapsulating structure upward view of the utility model;
Fig. 4 is the standard socket structural representation of the utility model.
Wherein: 1 is upper frame; 2 is ceramic substrate; 3 is underframe; 4 is upper cover plate; 5 is lower cover; 6 is standard socket.
Embodiment
Below in conjunction with accompanying drawing the utility model is done and to be described in further detail:
Referring to Fig. 1-4, the system integration encapsulating structure of the utility model mainly contains ceramic substrate, upper frame, upper cover plate, underframe, lower cover, socket composition.
Ceramic substrate is LTCC (LTCC), is multilayer ceramic substrate, and there is the interconnection line of metal conduction band as circuit ceramic substrate inside; The framework of metal is gone up in the welding up and down of ceramic substrate, forms two cavitys up and down, supplies to install the components and parts bare chip; Two cavitys are furnished with suitable cover plate, seal behind the components and parts of the intact inside cavity of assembly and adjustment again, make it to become the hermetic cavity body.It is to cut down material that metal framework and cover plate adopt, and makes it and the ceramic substrate that uses has close thermal coefficient of expansion.
What input and output (I/O) pin adopted is the mini jack of standard, and welds together with reflow welding between the ceramic substrate, and each contact pin is connected with inside circuit according to design, forms the I/O pin of circuit.The overall dimension of the utility model is 70mm * 53mm * 12mm.
Based on the SiP computer module circuit of homemade CPU, the system integrated circuit encapsulating structure that adopts the utility model is integrated in the main components and parts of the computer form with bare chip in the packaging body, and integrated component number has 12 of VLSI chips in the circuit; 17 of middle small scale integrated circuit chips; Optocoupler 9 tunnel, 95 of passive devices, the mini jack of employing standard; I/O quantity 160 lines, package dimension 70 * 53 * 12 (mm
3).The reliability of circuit has reached the GJB2438H level.
The above; It only is the preferred embodiment of the utility model; Not being that the utility model is done any pro forma restriction, though the utility model with the preferred embodiment exposure as above, yet is not in order to limit the utility model; Anyly be familiar with the professional and technical personnel; In not breaking away from the utility model technical scheme scope, make a little change or be modified to the equivalent embodiment of equivalent variations when the method for above-mentioned announcement capable of using and technology contents, be the content that does not break away from the utility model technical scheme in every case;, still belong in the scope of the utility model technical scheme any simple modification, equivalent variations and modification that above embodiment did according to the technical spirit of the utility model.
Claims (5)
1. a system integrated circuit encapsulating structure comprises ceramic substrate, upper frame, upper cover plate, underframe, lower cover and socket, it is characterized in that:
Said ceramic substrate is a multilager base plate, and there is the interconnection line of metal conduction band as circuit substrate inside; The ceramic substrate upper surface is welded with upper frame, the ceramic substrate lower surface is welded with underframe, and the upper surface or the lower surface of ceramic substrate are welded with socket, and socket is positioned at the outside of upper frame or underframe; Said upper frame is provided with upper cover plate, and upper surface, upper frame and upper cover plate form airtight upper cavity; Said underframe is provided with lower cover, and lower surface, underframe and lower cover form airtight lower chamber.
2. system integrated circuit encapsulating structure according to claim 1, it is characterized in that: said ceramic substrate is a low-temperature co-fired ceramic substrate.
3. system integrated circuit encapsulating structure according to claim 1 is characterized in that: the components and parts bare chip is installed in said upper cavity and the lower chamber.
4. system integrated circuit encapsulating structure according to claim 1 is characterized in that: said upper frame, upper cover plate, underframe and lower cover adopt and can cut down material and process, and it has close thermal coefficient of expansion with the ceramic substrate that uses.
5. system integrated circuit encapsulating structure according to claim 1, it is characterized in that: weld together with reflow welding between said socket and the substrate, each contact pin is connected with inside circuit according to design on the socket, the input and output pin of formation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220061366 CN202473897U (en) | 2012-02-23 | 2012-02-23 | System integrated circuit packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220061366 CN202473897U (en) | 2012-02-23 | 2012-02-23 | System integrated circuit packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202473897U true CN202473897U (en) | 2012-10-03 |
Family
ID=46922040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220061366 Expired - Lifetime CN202473897U (en) | 2012-02-23 | 2012-02-23 | System integrated circuit packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202473897U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104766833A (en) * | 2015-04-10 | 2015-07-08 | 中国工程物理研究院电子工程研究所 | Microwave circuit three-dimensional encapsulation structure with circuits arranged on front-back surface of LTCC base plate |
| CN105789141A (en) * | 2016-05-05 | 2016-07-20 | 中国工程物理研究院电子工程研究所 | Micro-assembling miniaturized three-dimensional microwave circuit structure |
| CN108428672A (en) * | 2018-04-17 | 2018-08-21 | 中国电子科技集团公司第二十九研究所 | The two-sided three-dimensionally integrated framework of ceramics and packaging method of ultra-wide band radio-frequency micro-system |
-
2012
- 2012-02-23 CN CN 201220061366 patent/CN202473897U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104766833A (en) * | 2015-04-10 | 2015-07-08 | 中国工程物理研究院电子工程研究所 | Microwave circuit three-dimensional encapsulation structure with circuits arranged on front-back surface of LTCC base plate |
| CN104766833B (en) * | 2015-04-10 | 2017-11-14 | 中国工程物理研究院电子工程研究所 | A kind of microwave circuit three-dimension packaging structure of ltcc substrate positive and negative cloth circuits |
| CN105789141A (en) * | 2016-05-05 | 2016-07-20 | 中国工程物理研究院电子工程研究所 | Micro-assembling miniaturized three-dimensional microwave circuit structure |
| CN108428672A (en) * | 2018-04-17 | 2018-08-21 | 中国电子科技集团公司第二十九研究所 | The two-sided three-dimensionally integrated framework of ceramics and packaging method of ultra-wide band radio-frequency micro-system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121003 |
|
| CX01 | Expiry of patent term |