Diversity drives DAS system power voltage analog signal conditioning module
Technical field
The utility model relates to a kind of signal processing technology, and particularly a kind of diversity based on the FPGA technology drives DAS system power voltage analog signal conditioning module.
Background technology
In third generation digitlization AP1000 control systems of nuclear power plant,, adopt two different platforms of safe level and non-safe level to realize the security control function according to different nuclear safety classifications.The safe level platform promptly protects and safety detecting system (protection and safety monitoring system, PMS), the function of realization response heap protection system; Non-safe level platform is that (plant control system PLS), realizes nuclear island/conventional island/power plant's auxiliary facility (balance of plant, BoP) most controlled function to control system of power plant.These safety functions that possibly receive common cause fault influence are grouped together, just formed the diversity drive system (dispersive actuation system, DAS).DAS is independent of a PMS and an outer isolated system of PLS.When protection during with the extremely low common cause fault of safety detecting system probability of occurrence, the DAS system is used for triggering reactor scram and halt turbines, and the probability of reduction core meltdown and containment superpressure plays the effect of PMS and PLS back-up system.
Because the DAS system is the subsequent use property system of protection and safety detecting system PMS and control system of power plant PLS; Therefore it adopts structure, the hardware and software that is different from PMS and PLS, and this also is the important measures of AP1000 control systems of nuclear power plant aspect the raising security measures.The DAS system is a complete hardware based system, does not have software control, and master chip adopts FPGA (field programmable gate array), and hardware description language is selected VHDL and Verilog HDL for use.All communication and data processing function all are in FPGA, to realize.
Current/voltage analog signal conditioner module plays the input current voltage analog signal in the DAS system, and changes, and through RS485 or optical fiber output fixed-point number engineering value, gives the intrasystem definite value module of DAS, display module or communication module.The calibration value k that the current/voltage conditioning module can also the received communication module sends, the linear conversion A of b and quantities, B value.
Summary of the invention
The utility model is to DAS system and safety detecting system PMS, the incompatible problem of control system of power plant PLS; Propose a species diversity and driven DAS system power voltage analog signal conditioning module; Adopt FPGA replaced C PU, can become the engineering value to analog signal conversion rapidly and accurately based on the FPGA technology.
The technical scheme of the utility model is: a species diversity drives DAS system power voltage analog signal conditioning module; Comprise with FPGA being FPGA processing module, analog signal conditioner module, AD sampling module, Flash module, RS485 communication module, optical fiber communication module and the power circuit of core; The curtage analog signal is that 0V~5V voltage signal is sent into the AD sampling module and carried out analog-to-digital conversion through the analog signal conditioner module with analog signal conversion at first; The output digital signal gets into the FPGA processing module; Read the calibration value of Flash module memory storage simultaneously, the FPGA processing module outputs to optic module and RS485 module through the two holding wire CE and the TXD of UART port; Optic module is a light signal with the conversion of signals that CE and TXD holding wire get, and sends to remote display modules or definite value module; The RS485 module becomes differential signal with CE with the conversion of signals that the TXD holding wire gets, and sends to communication module or local display module.
Said AD sampling module converts 24 true forms into after with the analog signal that receives, and sends to the FPGA processing module with the SPI serial communication mode of isolating.
The true form that said FPGA processing module is changed out with the AD sampling module through the SPI transceiver module converts parallel data to from serial data and preserves; High 16 that get in 24 are carried out the code value conversion; Read the calibration value k and the b of the storage of Flash module memory simultaneously, complement code is carried out the demarcation computing of kx+b, calibrated data are carried out the 40ms/80ms digital filtering and are handled; Carry out the computing of Ax+B linear transformation once more through filtered data; Operation result is put into the UART sending module, and the UART sending module sends to data the UART output port of FPGA processing module according to serial communication protocol.
Said optic module becomes serial signal with CE with the conversion of signals that the TXD holding wire gets, and gets into optical fiber again and drives, and becomes light signal.
The signal that said RS485 module gets CE and TXD holding wire gets into RS485 and drives through the magnetic isolating chip, becomes differential signal.
Said FPGA processing module receives nominal data and the linear transformation coefficient of sending from communication module through the RS485 module, and saves the data in the fixed address of Flash module.
The beneficial effect of the utility model is: the utility model diversity drives DAS system power voltage analog signal conditioning module; Adopt and nuclear power protection and safety monitoring system, the diverse design of nuclear power plant's control system, help improving the safe class of AP1000 nuclear power system; Adopt hardware circuit and FPGA design, avoided software design V&V authentication, accelerated development progress; Conditioning module adopts RS485 communication or the optical fiber communication of isolating, and has improved system reliability; Conditioning module electric current and voltage signal precision index are high, and response speed is fast.
Description of drawings
Fig. 1 drives DAS system power voltage analog signal conditioning module theory diagram for the utility model diversity.
Embodiment
Diversity based on the FPGA technology as shown in Figure 1 drives DAS system power voltage conditioning module theory diagram, comprises with FPGA being FPGA processing module 1, analog signal conditioner module 7, AD sampling module 2, Flash module 3, RS485 communication module 4, optical fiber communication module 5 and the power circuit 6 of core;
Embodiment one-current analog signal conditioning functions:
When 4mA~20mA current analog signal gets into this fastener; Through analog signal conditioner module 7, be analog that 0V~5V voltage signal is sent into AD sampling module 2 at first, receive analog signal after the AD chip be converted into 24 true forms; SPI serial communication mode to isolate sends to FPGA processing module 1; The magnetic coupling is adopted in the isolation of SPI, has guaranteed that on-site signal and control circuit isolate each other, and is separate.The true form that FPGA processing module 1 is come out 2 conversions of AD sampling module through the SPI transceiver module converts parallel data to from serial data and preserves, and high 16 that get in 24 are carried out the code value conversion, guarantee precision; Convert complement code into from true form; Make things convenient for data operation, read the calibration value k and the b of Flash module 3 stored simultaneously, complement code is carried out the demarcation computing of kx+b; Calibrated data are carried out the 40ms/80ms digital filtering and are handled the increase data stability.Owing to be linear relation between current signal code value and the quantities; Therefore carry out the computing of Ax+B linear transformation once more through filtered data; Obtain the actual engineering value of 2 byte lengths, the fixed point position of filling 1 byte at last, wherein current signal engineering value is 2 decimal points.The definition of decimal point byte sees the following form:
The decimal point byte |
Scale |
00000001 |
No decimal point |
00000010 |
1 decimal point |
00000100 |
2 decimal points |
So the decimal point byte of current signal is 0x04, also organized the diagnosis sign indicating number of a byte in the last FPGA processing module 1, put into the UART sending module together with 2 byte engineering values and 1 byte decimal point position.The UART sending module sends to these data the UART output port of FPGA according to serial communication protocol.The UART port one of FPGA processing module 1 has two holding wires, and CE and TXD get into optic module 5 and RS485 module 4 respectively.In optic module 5, pass through earlier and the string conversion, convert CE and TXD to serial signal, get into optical fiber again and drive, become light signal, send to remote display modules or definite value module; In RS485 module 4, CE and TXD get into RS485 and drive through the magnetic isolating chip, become differential signal, send to communication module or local display module.
FPGA processing module 1 can also receive nominal data and the linear transformation coefficient of sending from communication module through RS485 module 4; And these data are kept in the fixed address of Flash module 3; Keep supplying the computing of AD sampled data for the first time of electricity back, realize the hot plug function of conditioning module.
Embodiment two-voltage analog signal conditioning functions:
When 1V~10V voltage analog signal gets into this fastener; Through analog signal conditioner module 7, be analog that 0V~5V voltage signal is sent into AD sampling module 2 at first, receive analog signal after the AD chip be converted into 24 true forms; SPI serial communication mode to isolate sends to FPGA processing module 1; The magnetic coupling is adopted in the isolation of SPI, has guaranteed that on-site signal and control circuit isolate each other, and is separate.The true form that FPGA processing module 1 is changed out with the AD chip through the SPI transceiver module converts parallel data to from serial data and preserves, and high 16 that get in 24 are carried out the code value conversion, guarantee precision; Convert complement code into from true form; Make things convenient for data operation, read the calibration value k and the b of Flash module 3 stored simultaneously, complement code is carried out the demarcation computing of kx+b; Calibrated data are carried out the 40ms/80ms digital filtering and are handled the increase data stability.Owing to be linear relation between voltage signal code value and the quantities; Therefore carry out the Ax+B computing once more through filtered data; Obtain the actual engineering value of 2 byte lengths, the fixed point position of filling 1 byte at last, wherein voltage signal engineering value is 1 decimal point.The definition of decimal point byte sees the following form:
The decimal point byte |
Scale |
00000001 |
No decimal point |
00000010 |
1 decimal point |
00000100 |
2 decimal points |
So the decimal point byte of voltage signal is 0x02, also organized the diagnosis sign indicating number of a byte in the last FPGA processing module 1, put into the UART sending module together with 2 byte engineering values and 1 byte decimal point position.The UART sending module sends to these data the UART output port of FPGA processing module 1 according to serial communication protocol.The UART port one of FPGA processing module 1 has two holding wires, and CE and TXD get into optic module 5 and RS485 module 4 respectively.In optic module 5, pass through earlier and the string conversion, convert CE and TXD to serial signal, get into optical fiber again and drive, become light signal, send to remote display modules or definite value module; In RS485 module 4, CE and TXD get into RS485 and drive through the magnetic isolating chip, become differential signal, send to communication module or local display module.
FPGA processing module 1 can also receive nominal data and the linear transformation coefficient of sending from communication module through the RS485 module; And these data are kept in the fixed address of Flash module 3; Keep supplying the computing of AD sampled data for the first time of electricity back, realize the hot plug function of conditioning module.