CN202422217U - Infrared target acquisition and recognition tracker - Google Patents
Infrared target acquisition and recognition tracker Download PDFInfo
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- CN202422217U CN202422217U CN 201120536503 CN201120536503U CN202422217U CN 202422217 U CN202422217 U CN 202422217U CN 201120536503 CN201120536503 CN 201120536503 CN 201120536503 U CN201120536503 U CN 201120536503U CN 202422217 U CN202422217 U CN 202422217U
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Abstract
The utility model relates to an infrared target acquisition and recognition tracker which comprises a video image digital acquisition circuit, an embedded core processing system, a servo system, an image detection result output display circuit and a peripheral auxiliary circuit, wherein the video image digital acquisition circuit comprises a signal conditioning and A/D (analog/digital) converting circuit, an image input storage, a synchronous separation circuit and a video acquisition control module, the embedded core processing system comprises a digital signal processor, a program storage, a data and parameter storage, a logic control circuit, a sequence generation circuit and a reset circuit, the servo system is used for tracking a recognized target, the image detection result output display circuit comprises a mark superposition control module, a video superposition circuit, a tracking result output and external data input module and a monitor, and the peripheral auxiliary circuit comprises a secondary power supply and a monitoring circuit thereof. The infrared target acquisition and recognition tracker is high in integration degree and universality, fast in image processing speed, high in target tracking instantaneity and applicable to various industries and departments including the civil industry, the medical industry, the military department and the like.
Description
Technical field
The utility model relates to a kind of device that is used to discern figure, specifically a kind of infrared target acquisition, recognition and tracking device.
Background technology
The Target Recognition tracking technique is a kind of recognition and tracking technology that is directed to the low latitude fast-moving target, mainly comprises target search, Target Recognition and real-time follow-up.The major function of acquisition, recognition and tracking device is to convert the analog image that detector collects into data image signal, and the target in the image is searched for automatically, discerned and follows the tracks of, and exports testing result and demonstration then.It is in civilian industry and medical industry, and especially military service etc. all earns widespread respect.More existing Target Recognition tracking means mainly are to carry out under the specific objective background that is directed against in some specific application area with technology, and its versatility is not strong, and integrated degree is not high.
The utility model content
The purpose of the utility model just provides a kind of infrared target acquisition, recognition and tracking device, with functions such as the control signal output of collection, Flame Image Process and the Target Recognition that can accomplish the image detection signal, Control Servo System, the outputs of Target Recognition composite video signal.
The utility model is achieved in that a kind of infrared target acquisition, recognition and tracking device, includes:
The video image digital collection circuit of forming by signal condition and A/D translation circuit, image input store, synchronizing separator circuit and video acquisition control module;
The embedded core processing system of forming by digital signal processor, program storage, data and parameter storage, logic control circuit, timing generator circuit and reset circuit;
Servo-drive system according to the steering order control signal output of said embedded core processing system, is followed the tracks of the target of being discerned;
The image detection result who is made up of sign superposing control module, video superimpose circuit, tracking results output and external data load module and monitor exports display circuit; And
The peripheral auxiliary circuits of forming by secondary power supply and observation circuit thereof;
The output of said synchronizing separator circuit connects said video acquisition control module; The two-way output said signal condition of tap and the A/D translation circuit and the said image input store of said video acquisition control module, said image input store, said program storage, said data and parameter storage, said timing generator circuit, said logic control circuit join with said digital signal processor respectively.
Said logic control circuit in the utility model, timing generator circuit, reset circuit, sign superposing control module, video superimpose circuit and tracking results output and external data load module are integrated in a slice fpga chip jointly; Improve the integrated of system thus, also reduced the number of chips in the system simultaneously.
The function of video image digital collection circuit; It is the row field signal of the incoming video signal sent here according to synchronizing separator circuit; A/D transducer in control signal conditioning and the A/D translation circuit converts the analog video input signal into digital image stream, is sent to digital signal processor DSP.The image input store adopts table tennis formula storage organization storage digital image information.This part circuit mainly comprises signal condition and A/D translation circuit, image input store, synchronizing separator circuit and video acquisition control module.Signal condition and A/D translation circuit comprise signal conditioning circuit and A/D transducer.Signal conditioning circuit mainly is a prime amplifier; It can suitably amplify the vision signal of input; The dynamic range of vision signal and the full scale of A/D transducer are complementary, thereby reduce loss because of the signal data number of significant digit that noise caused of A/D transducer itself.
The row field signal of the incoming video signal that the video acquisition control module is sent here according to synchronizing separator circuit, the duty of control A/D transducer, and provide the major clock of A/D chip to accomplish of the conversion of A/D transducer to analog video signal.Meanwhile, the video acquisition control module produces logic control signals such as address and read-write, the sheet choosing of image input store, the digital picture gray-scale value of gathering is write the storage space of relevant position.
The design of embedded core processing system is the design key of the utility model, require not only to have stronger data throughput capabilities, but also should have that speed is fast, precision is high, characteristics such as good reliability, function are strong.According to these requirements, the utility model is chosen the TMS320C6418 data processing chip of technical grade as the digital signal processor DSP in the embedded core processing system.Digital signal processor is according to the target of program setting or manual intervention setting, and the target in the digital picture of being imported is searched for automatically and discerned.
Embedded core processing system can be realized high instruction level parallelism treatment effeciency, can realize the fast processing of data.Addressing mode and communication mechanism can satisfy the program of high-speed high capacity and expand and data storage flexibly.Data and parameter storage are selected the SDRAM chip (MT48LC4M32) of high-speed high capacity for use, are used to store intermediate treatment result and view data.According to the size of program and required stored parameters, the FLASH MEMORY chip of selecting respective model for use is deposited the working routine of embedded core processing system as program storage.System power on or system reset after, the boot that resets according to digital signal processor DSP guides to the executive routine in the program storage in the internal storage of digital signal processor DSP automatically.
The function of timing generator circuit is the required various clocks of generation system, comprising: dsp processor clock, A/D conversion major clock etc.Timing sequencer in the timing generator circuit adopts the FPGA technology to realize; All clock signals all obtain from the oscillating clock signal frequency division that a crystal oscillator produces; Phase mutual interference with regard to having avoided causing owing to difference frequency between the different clocks signal like this, thus make system's synchronous working better.
The function of logic control circuit is the logic control signals such as read/write signal, output enable and sheet choosing of each chip in the generation system; And the address wire and the read-write control line of digital signal processor DSP deciphered, to produce the required various control signals in each memory block.Consider the read or write speed of digital signal processor DSP and the volume of circuit board, logic control circuit also realizes on fpga chip, and the chip in so also can the minimizing system is provided with quantity.
Reset circuit is accomplished the logical combination and the signal condition of the reset signals such as electrification reset, hand-reset and watchdog reset of system, produces unified reset signal, starts with the reliable reset of the each several part that guarantees total system.The setting of watchdog reset circuit wherein mainly is to run for prophylactic procedures to fly or system in case of system halt.
Image detection result exports the function of display circuit; Be the capable field sync signal of sending here according to synchronizing separator circuit by sign superposing control module, in conjunction with counter regularly, confirm the position of video pixel point; The control of video supercircuit; Corresponding picture element and sign are added on the video input signals, and the vision signal after the stack send monitor to show, to observe synthetic target video output signal in real time;
The vision signal that the monitor of the utility model is imported is not the vision signal that the detector of original input is sent here, but the utility model that superposeed is handled the vision signal that has various parameter signs that obtains behind the image.All logical operations of sign stack are accomplished by sign superposing control module: sign superposing control module utilizes internal RAM to expand the external memory interface of a part of storage unit to digital signal processor DSP; So just can receive the various parameters after digital signal processor DSP is handled image; Thereby confirm position or concrete data in the video image of various parameters after stack, and send it to sign superposing control module; The capable field sync signal that sign superposing control module in the fpga chip is sent here according to synchronizing separator circuit; The counter of connecting inner definition regularly; To confirm the position of corresponding video pixel point; The control of video supercircuit is with corresponding picture element and indicate that on the raw video signal of the detector conveying that is added to, the vision signal after stack is accomplished is sent to monitor and shows, thereby can observe the various running statuses of the utility model in real time.
The utility model is in the process of detection and tracking target; Can export size, target strength (signal to noise ratio (S/N ratio)) and tracker that whether this two field picture detect position in the visual field of target, target, target and handle the time information such as (information delays) of this two field picture; These information are not only to be presented on the monitor for observation through sign stack and display circuit stack; Can also be sent to servo or control computer, carry out follow-up servo action or carry out control decision.So the utility model must be expanded the interface circuit with servo or control computer, the output of tracking results that Here it is.In addition; Under the situation of some complex backgrounds, the utility model automatically carries out Target Recognition possibly have big difficulty, and at this time manual work is intervened in the loop and indicated with regard to needs; Just need be from system's outside importation parameter; The subsidiary book utility model is accomplished Target Recognition, and makes the utility model get into full-automatic target following state, on fpga chip, has expanded tracking results output and external data load module for this reason.
Secondary power supply in the utility model can be system three cover low-tension supplies is provided, and observation circuit can be used for carrying out the real-time monitoring of low-tension supply, and the assurance system is normal to be started and operation.
The secondary power supply is set; Be because digital signal processor DSP and fpga chip need use+1.2V ,+2.5V ,+3.3V etc. three overlaps low-tension supplies; Wherein+1.2V and+2.5V two cover low-tension supplies must provide prior to+3.3V low-tension supply; So the utility model need be equipped with the secondary power supply of oneself, to guarantee the operate as normal of system.The effect of electric source monitoring circuit is to ensure to the supply voltage of digital signal processor power supply when not meeting the requirements of level, uncontrolled state can not occur, thus the normal startup and the running of the system of assurance.
The advantage of the utility model is: (1) with video acquisition, target recognition and tracking organic integration in one; Improved the integrated and universalization degree of device; Particularly pass through the integrated design of video signal collective and target identification processing circuit and the design of signal conditioning circuit prime amplifier; Not only improve the universalization degree of system, and improved the antijamming capability in the signal data transmission course, and eliminated the loss of the signal number of significant digit that is caused because of A/D transducer itself; Improved the accuracy that echo signal detects, integrated degree also significantly improves thus; (2) input/output module design flexibly; The image that can satisfy under the different target background is followed the tracks of, and according to the different target background, tracker both can be at unmanned automatic recognition and tracking under the loop is intervened; Also can be through external data input interface input data; Carry out the people and intervene Target Recognition down in the loop and follow the tracks of, thereby realize the universalization of tracker, and be convenient to programme and upgrade; (3) use of the image input store of high speed digital signal processor, the FPGA device of supporting high speed operation and table tennis formula storage organization has improved image processing speed, thereby can realize the real-time follow-up of image object; (4) secondary power supply, power sense circuit and reset circuit etc. are that the work system of this tracker necessarily requires in this special environment for use of photoelectric guidance system and special applications object; With under the abnormal situation of voltage; Make system's complete machine of this tracker not controlled situation can not occur; Guarantee that whole information handling system can normal starting and running, effectively prevent program fleet etc.
The principal feature of the utility model is integrated degree height, highly versatile, image processing speed is fast and target following is real-time; Make that the recognition speed of system is fast; Real-time; Can satisfy the limit identification of multiple threat object under the complicated ground background, the specific (special) requirements that follow the tracks of on the limit, also be applicable to multiple applications such as civilian industry, medical industry and military service simultaneously.
Description of drawings
Fig. 1 is the hardware block diagram of the utility model.
Fig. 2 is the table tennis formula storage organization synoptic diagram of image input store.
Embodiment
As shown in Figure 1, the utility model includes video image digital collection circuit, embedded core processing system, servo-drive system, image detection result and exports display circuit and peripheral auxiliary circuits etc.
Wherein, video image digital collection circuit includes signal condition and A/D translation circuit 14, image input store 2, synchronizing separator circuit 13 and video acquisition control module 9 etc.Signal condition and A/D translation circuit 14 include signal conditioning circuit and A/D transducer.The row field signal of the incoming video signal that video acquisition control module 9 is sent here according to synchronizing separator circuit 13; A/D transducer in control signal conditioning and the A/D translation circuit 14 converts the analog video input signal into digital image stream, and image input store 2 adopts table tennis formula storage organizations storage digital image informations.
Embedded core processing system includes digital signal processor 6, program storage 4, data and parameter storage 3, RS232 interface 5, logic control circuit 16, timing generator circuit 15 and reset circuit 7 etc.Digital signal processor 6 is searched for automatically and is discerned the target in the digital picture of being imported according to the target of program setting or manual intervention setting.
Servo-drive system is a conventional structure, according to the steering order control signal output of embedded core processing system, the target of being discerned is followed the tracks of.
Image detection result exports display circuit and includes sign superposing control module 10, video superimpose circuit 12, tracking results output and external data load module 8 and monitor 11 etc.The capable field sync signal that sign superposing control module 10 is sent here according to synchronizing separator circuit 13 in conjunction with the counter timing, is confirmed the position of video pixel point, and control of video supercircuit 12 is added to corresponding picture element and sign on the video input signals; Vision signal after the stack send monitor 11 to show, to observe the output of synthetic target video in real time.
Peripheral auxiliary circuits includes secondary power supply and observation circuit 1 thereof etc.The secondary power supply be system provide digital signal processor DSP and the required use+1.2V of fpga chip ,+2.5V ,+three cover low-tension supplies such as 3.3V, wherein+1.2V and+2.5V two cover low-tension supplies must provide prior to+3.3V low-tension supply.Observation circuit carries out the real-time monitoring of low-tension supply, to guarantee the normal startup and the operation of system.
As shown in Figure 1, the logic control circuit 16 in the utility model, timing generator circuit 15, reset circuit 7, sign superposing control module 10, video superimpose circuit 12 are integrated in a slice fpga chip with tracking results output and external data load module 8 etc. jointly.
Consider that image input store 2 is expansion asynchronous memories outside digital signal processor 6; Operating speed is not high; The directly operation of the asynchronous memory outside sheet when if digital signal processor DSP is handled; With the processing speed that influences digital signal processor, therefore should the digital picture of gathering in time be moved in the data and parameter memory of rapid speed.The utility model is filled with in the image input store after the delegation of video image, promptly by fpga chip to digital signal processor DSP application EDMA, data are moved rapidly in the data and parameter memory SDRAM of rapid speed.For overlapping phenomenon not occurring between the forward and backward frame of the image that digital signal processor DSP is read in, the image input store of memory image can adopt table tennis formula storage organization.Its concrete mode is as shown in Figure 2; Promptly under the cooperation of sequential control and handshake (FPGA); DSP data-moving (EDMA) part is to 0# image working area moving data the time; Explain that video image digital collection circuit carries out digitizing to the even field signal of incoming video signal, and the odd field signal of front has been accomplished digital collection and moved 1# image working area, digital signal processor DSP can be moved into it fast and carry out Flame Image Process in the on-chip memory.
The utility model and external system adopt RS232 serial interface communication mode to communicate.Because digital signal processor DSP itself does not have special-purpose RS232 serial ports,, adopt an asynchronous data bus that data width is 16Bit therefore in order to realize the RS232 serial port function.Output of the tracking results of the utility model and external data input etc. are all accomplished through data bus thus.The tracking results of system's output and the external data of input system can be mapped in the different address space.The utility model can utilize the internal RAM of fpga chip to make the 16Bit dual-ported memory with certain depth, to realize the storage of above-mentioned data.One termination digital signal processor DSP of this dual-ported memory is used for digital signal processor DSP output tracking result and reads external data; Another termination external interface is realized and the outside is servo or control getting in touch of turntable computing machine.
Claims (2)
1. an infrared target acquisition, recognition and tracking device is characterized in that, includes:
The video image digital collection circuit of forming by signal condition and A/D translation circuit (14), image input store (2), synchronizing separator circuit (13) and video acquisition control module (9); The row field signal of the incoming video signal of sending here according to synchronizing separator circuit; Control said signal condition and the A/D translation circuit converts the analog video input signal into digital image stream, be sent to digital signal processor;
By the embedded core processing system that digital signal processor (6), program storage (4), data and parameter storage (3), logic control circuit (16), timing generator circuit (15) and reset circuit (7) are formed, the target in the digital picture of being imported is searched for automatically and discerned;
Servo-drive system according to the steering order control signal output of said embedded core processing system, is followed the tracks of the target of being discerned;
The image detection result who is made up of sign superposing control module (10), video superimpose circuit (12), tracking results output and external data load module (8) and monitor (11) exports display circuit; The capable field sync signal of sending here according to synchronizing separator circuit; Confirm the position of video pixel point; Control said video superimpose circuit, corresponding picture element and sign are added on the video input signals, send said monitor to show; And
By the peripheral auxiliary circuits that secondary power supply and observation circuit (1) thereof are formed, for system provides three cover low-tension supplies and carries out the real-time monitoring of low-tension supply, the assurance system is normal to be started and operation;
The output of said synchronizing separator circuit (13) connects said video acquisition control module (9); The two-way output said signal condition of tap and the A/D translation circuit (14) and the said image input store (2) of said video acquisition control module (9), said image input store (2), said program storage (4), said data and parameter storage (3), said timing generator circuit (15), said logic control circuit (16) join with said digital signal processor (6) respectively.
2. infrared target acquisition, recognition and tracking device according to claim 1; It is characterized in that said logic control circuit (16), timing generator circuit (15), reset circuit (7), sign superposing control module (10), video superimpose circuit (12) are integrated in a slice fpga chip with tracking results output and external data load module (8) jointly.
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| CN 201120536503 CN202422217U (en) | 2011-12-20 | 2011-12-20 | Infrared target acquisition and recognition tracker |
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| CN 201120536503 CN202422217U (en) | 2011-12-20 | 2011-12-20 | Infrared target acquisition and recognition tracker |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065864A (en) * | 2013-03-19 | 2014-09-24 | 成都凯智科技有限公司 | Image acquisition processing system based on DSP and FPGA |
| CN107945215A (en) * | 2017-12-14 | 2018-04-20 | 湖南华南光电(集团)有限责任公司 | High-precision infrared image tracker and a kind of target fast tracking method |
| CN108230228A (en) * | 2016-12-12 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | Miniaturization real-time modeling method processing system based on probability density statistics |
-
2011
- 2011-12-20 CN CN 201120536503 patent/CN202422217U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065864A (en) * | 2013-03-19 | 2014-09-24 | 成都凯智科技有限公司 | Image acquisition processing system based on DSP and FPGA |
| CN108230228A (en) * | 2016-12-12 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | Miniaturization real-time modeling method processing system based on probability density statistics |
| CN108230228B (en) * | 2016-12-12 | 2023-02-10 | 中国航空工业集团公司西安航空计算技术研究所 | Miniaturized real-time target tracking processing system based on probability density statistics |
| CN107945215A (en) * | 2017-12-14 | 2018-04-20 | 湖南华南光电(集团)有限责任公司 | High-precision infrared image tracker and a kind of target fast tracking method |
| CN107945215B (en) * | 2017-12-14 | 2021-07-23 | 湖南华南光电(集团)有限责任公司 | High-precision infrared image tracker and target rapid tracking method |
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Granted publication date: 20120905 Termination date: 20121220 |