CN202421932U - Gps central management host - Google Patents

Gps central management host Download PDF

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Publication number
CN202421932U
CN202421932U CN2011202865949U CN201120286594U CN202421932U CN 202421932 U CN202421932 U CN 202421932U CN 2011202865949 U CN2011202865949 U CN 2011202865949U CN 201120286594 U CN201120286594 U CN 201120286594U CN 202421932 U CN202421932 U CN 202421932U
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China
Prior art keywords
module
links
power supply
processor
gps
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Expired - Fee Related
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CN2011202865949U
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Chinese (zh)
Inventor
尹浩林
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DONGGUAN YIHAO ELECTRONICS TECHNOLOGY Co Ltd
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Individual
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Priority to CN2011202865949U priority Critical patent/CN202421932U/en
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Abstract

The utility model discloses a GPS (Global Positioning System) central management host. The GPS central management host can be subjected to data exchange with other police-service systems and can be networked with a vehicle management system to inquire relevant information of vehicles and share violation information with other systems. The GPS central management host is characterized by comprising a processor, a display module, an information detection module, a memory module, a networking module, a CPLD (Complex Programmable Logic Devices) module, a power supply monitoring module and a power supply module, wherein a data wire MP0-MP1 of the display module is connected with a VP0D2-VP0D9 of a port VP1; a data wire YOUT0-YOUT7 of the information detection module is connected with a VP1D2-VP1D9 of a port VP1; an SCLK (Synthesizer Clock) is connected with a VPICLKO of the port VP1; an INTREQ (Interrupt Request) is connected with a VPICTL of the port VP1; two 32-bit chips are applied to an SDRAM (Synchronous Dynamic Random Access Memory) in the memory module; a data wire D0-D31 of one 32-bit chip is connected with TED0-TED31 of a DSP (Digital Signal Processor); and a data wire D0-D31 of another 32-bit chip is connected with TED32-TED63 of the DSP. Due to the adoption of the scheme, the benefits of favorable monitoring and distributing real-time property and strong data transmission function by adopting a GSP mode are achieved.

Description

GPS centre management main frame
Technical field
The utility model relates to a kind of GPS centre management main frame.
Background technology
Existing GPS centre management main frame is based upon in the LAN system that satisfies Ministry of Public Security's network security requirement, does further information extraction, processing and storage and corresponding service processing through the photo violating the regulations that many service servers and workstation pass back front end is set.Adopt the B/S mode, query interface externally is provided, can handle the hall the traffic police touch screen query terminal is set, set up information issue window with the mode of client.System can set up the WEB application server; Support to adopt the mode of WEB to carry out information issue, inquiry; And support to adopt satisfy Ministry of Public Security's network security requirement mode with material upload to the INTERNET net, supply public's inquiry or the message search mode be provided through the Short Message Service Gateway interface.But the prior art real system comes into operation, and real-time is poor, data-transformation facility a little less than, can not satisfy the demands when needing the transmission of big data quantity; It is relatively poor to utilize the GPS mode to monitor the allotment real-time simultaneously.
Summary of the invention
The purpose of the utility model is: a kind of GPS centre management main frame is provided; To solve the problem that exists in the background technology; Can carry out exchanges data with other police system, can with vehicle management system online query vehicle relevant information, and violation information shared to other system.
Reach the purpose of the utility model; The technical scheme of taking is: a kind of GPS centre management main frame is characterized in that: comprise processor, display module, information detection module, storage module, networking module, CPLD module, power supply monitoring module, power module; The data line MP0-MP1 of display module links to each other with the VP0D2-VP0D9 of VP0 mouth; The data line YOUT0-YOUT7 of information detection module links to each other with the VP1D2-VP1D9 of VP1 mouth, and SCLK links to each other with the VPICLKO of VP1 mouth, and LNTREQ links to each other with the VPICTL of VP1 mouth; SDRAM adopts two 32 chips in the storage module; The data line D0-D31 of a slice links to each other with the TED0-TED31 of DSP; The data line D0-D31 of another sheet links to each other with the TED32-TED63 of DSP; Be combined into 64 position datawires, the low 19 bit address bus A0-A18 of FLASH link to each other with the low 19 bit address bus TEA3-TEA21 of processor in the storage module, the THE of processor and TWE direct with FLASH /OE links to each other with TWE; Networking module is formed the MII interface that EMAC has by EMAC and MDIO two parts, with the network interface seamless link of processor; The CPLD module provides the page or leaf selection signal of FLSAH in the storage module; The power supply of power supply monitoring module supervision pin links to each other with main power pins, and the GPIO pin of processor is linked to each other with the house dog input pin WDI of power supply monitoring module.This main frame also comprises, power light, network state lamp, jtag interface, I/O extended pin; Wherein power light is connected on the power supply through resistance, and the network state lamp is connected between network chip power pins and the ground, and jtag interface is the emulation pin of connection processing device respectively, comprises TRST, TDI, TDO, TCK, TMS, EMU0, EMU1.
The beneficial effect that the utility model reaches is: the utility model has reached and has utilized the GPS mode to monitor the allotment beneficial effect that real-time is good, data-transformation facility is strong.
Description of drawings
Accompanying drawing 1 is the functional block diagram of the utility model embodiment.
Accompanying drawing 2 is the CPU structural drawing of the utility model embodiment.
Accompanying drawing 3 is the video acquisition module schematic diagram of the utility model embodiment.
Accompanying drawing 4 is the video display module schematic diagram of the utility model embodiment.
Accompanying drawing 5 is the storage module schematic diagram of the utility model embodiment.
Accompanying drawing 6 is the CPLD logical diagram of the utility model embodiment.
Accompanying drawing 7 is the networking module schematic diagram of the utility model embodiment.
Accompanying drawing 8 is the power supply monitoring module principle figure of the utility model embodiment.
Accompanying drawing 9 is the power module schematic diagram of the utility model embodiment.
Embodiment
Combine accompanying drawing to get off, the embodiment of the utility model is specified.
With reference to accompanying drawing 1; 2, the utility model embodiment comprises that embedded place buries device 1, display module 2, information detection module 3, storage module 4, networking module 5, CPLD module 6, power supply monitoring module 7, power module 8; Also comprise power light in addition; The network state lamp, jtag interface, I/O expansion.
With reference to accompanying drawing 3, display module data line MP0-MP1 links to each other with the VPOD2-VPOD9 of VP0 mouth in the embodiment of the utility model, and display module directly extracts synchronizing signal from the BT.656 data stream of VPO mouth output.
With reference to accompanying drawing 4, the data line YOUT0-YOUT7 of information detection module links to each other with the VP1D2-VP1D9 of VP1 mouth in the embodiment of the utility model, and SCLK links to each other with the VPICLKO of VP1 mouth, to the VP1 mouth clock signal is provided.INTREQ links to each other with the VPICTLO of VP1 mouth, to obtain the collection enable signal.
With reference to accompanying drawing 5; SDRAM adopts two 32 chip designs in the embodiment of the utility model; Wherein the data line D0-D31 of a slice links to each other with the TED0-TED31 of DSP; The data line D0-D31 of another sheet links to each other with the TED32-TED63 of DSP, is combined into 64 position datawires, and the clock signal clk of SDRAM is provided by the AECLKOUT1 of DSP.In the storage module the low 19 bit address bus A0-A18 of FLASH link to each other with the low 19 bit address bus TEA3-TEA21 of processor THE and the TWE of processor direct with FLASH /OE links to each other with TWE, and the read-write gating signal is provided.The TCE1 of processor and TEA22 form the chip selection signal of FLASH jointly through CPLD.
With reference to accompanying drawing 6,7, networking module is made up of EMAC and MDIO two parts in the embodiment of the utility model, and the MII interface that EMAC has is with the network interface seamless link of processor.The CPLD module provides the page or leaf selection signal of FLSAH in the storage module.
With reference to accompanying drawing 8,9, the power supply of power supply monitoring module supervision pin links to each other with main power pins in the embodiment of the utility model, and the GPIO pin of processor is linked to each other with the house dog input pin WDI of power supply monitoring module.I.8V power module provides and two kinds of electric source modes of 3.3V.
More than being merely a preferred embodiments of the utility model, is not the qualification to the utility model.

Claims (2)

1. a GPS centre management main frame is characterized in that: comprise processor, display module, information detection module, storage module, networking module, CPLD module, power supply monitoring module, power module; The data line MP0-MP1 of display module links to each other with the VP0D2-VP0D9 of VP0 mouth; The data line YOUT0-YOUT7 of information detection module links to each other with the VP1D2-VP1D9 of VP1 mouth, and SCLK links to each other with the VPICLKO of VP1 mouth, and LNTREQ links to each other with the VPICTL of VP1 mouth; SDRAM adopts two 32 chips in the storage module; The data line D0-D31 of a slice links to each other with the TED0-TED31 of DSP; The data line D0-D31 of another sheet links to each other with the TED32-TED63 of DSP; Be combined into 64 position datawires, the low 19 bit address bus A0-A18 of FLASH link to each other with the low 19 bit address bus TEA3-TEA21 of processor in the storage module, the THE of processor and TWE direct with FLASH /OE links to each other with TWE; Networking module is made up of EMAC and MDIO two parts, and the MII interface that EMAC has is with the network interface seamless link of processor; The CPLD module provides the page or leaf selection signal of FLSAH in the storage module; The power supply of power supply monitoring module supervision pin links to each other with main power pins, and the GPIO pin of processor is linked to each other with the house dog input pin WDI of power supply monitoring module.
2. a kind of GPS centre management main frame according to claim 1, its characteristic also comprises: power light, network state lamp, jtag interface, I/O extended pin; Wherein power light is connected on the power supply through resistance, and the network state lamp is connected between network chip power pins and the ground, and jtag interface is the emulation pin of connection processing device respectively, comprises TRST, TDI, TDO, TCK, TMS, EMU0, EMU1.
CN2011202865949U 2011-08-08 2011-08-08 Gps central management host Expired - Fee Related CN202421932U (en)

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Application Number Priority Date Filing Date Title
CN2011202865949U CN202421932U (en) 2011-08-08 2011-08-08 Gps central management host

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Application Number Priority Date Filing Date Title
CN2011202865949U CN202421932U (en) 2011-08-08 2011-08-08 Gps central management host

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107111932A (en) * 2015-01-14 2017-08-29 欧姆龙株式会社 Violation information screening system, circular receiving system and violation information screening technique

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107111932A (en) * 2015-01-14 2017-08-29 欧姆龙株式会社 Violation information screening system, circular receiving system and violation information screening technique

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: DONGGUAN YIHAO ELECTRONICS TECHNOLOGY CO., LTD.

Free format text: FORMER OWNER: YIN HAOLIN

Effective date: 20130118

C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20130118

Address after: 518109 Guangdong province Dongguan city Dalang Town Water Park Avenue, Tianyuan Road No. 6 Dalang Creative Industry Park B101

Patentee after: Dongguan Yihao Electronics Technology Co., Ltd.

Address before: 518109 Guangdong province Dongguan city Dalang town water Tianyuan Avenue Xinyuan Road No. 6

Patentee before: Yin Haolin

C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120905

Termination date: 20130808