CN202404236U - Binary channel radio frequency receiver of multiplexing analog-to-digital conversion output - Google Patents
Binary channel radio frequency receiver of multiplexing analog-to-digital conversion output Download PDFInfo
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- CN202404236U CN202404236U CN2011204161199U CN201120416119U CN202404236U CN 202404236 U CN202404236 U CN 202404236U CN 2011204161199 U CN2011204161199 U CN 2011204161199U CN 201120416119 U CN201120416119 U CN 201120416119U CN 202404236 U CN202404236 U CN 202404236U
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Abstract
The utility model relates to a binary channel radio frequency receiver of multiplexing analog-to-digital conversion output. Two channels receive two GNSS (Global Navigation Satellite System) radio frequency signals for precise positioning; the two channels use a same sampling clock to respectively perform analog-to-digital conversion treatment; a common multiplexing switching module is used to perform transmultiplex treatment on binary channel analog-to-digital conversion data and to output multiplexing polarity and amplitude signals to the outside through a group of IO output pins which are completely consistent with a single channel navigation radio frequency receiver. The binary channel radio frequency receiver of the utility model can save chip packaging costs and is compatible with a single channel receiver. The multiplexing switching module meanwhile outputs a sampling output clock used for subsequent reduction of the two channel data from multiplexing output data.
Description
Technical field
The utility model relates to a kind of radio frequency chip of field of wireless communication, particularly a kind of binary channels radio-frequency transmitter of multiplexing analog to digital conversion output.
Background technology
The worldwide navigation Positioning System (GPS) has been widely used in vehicle mounted guidance, vehicle tracking, time synchronized, measurement mapping, ship or vehicle monitoring, geodata collection, space industry or the like.Up to the present, navigation positioning system maximum and maximum users are vehicle-mounted and hand-held navigation.At hand-held navigating instrument (PND; Portable Navigation Device) or similarly in using, because whole navigating instrument is through powered battery, so to this application; The chip power-consumption of navigational system has special meaning: power consumption is low more, and the time of use is just long more.On market, as the SiRF company of the U.S., all there has been very ripe navigation radio frequency chip in the MAXIM company of the Canadian SiGe company and the U.S. at present, and its product is most to be designed and make with SiGe technology, to reach low-power consumption, high performance purpose.
As shown in Figure 1; These products all are to adopt in the system architecture of traditional Low Medium Frequency navigation radio-frequency transmitter; 1575.42MHz navigation GPS rf modulated signal; Be received through the antenna (not shown) in the signalling channel of radio frequency, the low noise amplifier 10 (LNA) through front end amplifies.In order to filter out contiguous mobile phone or other communication undesired signal, need output to outside the chip through the radio frequency rf signal that amplifies, carry out Filtering Processing by the outer acoustic filter 20 (SAW FILTER) of sheet; After taking back further amplification of radio frequency prime amplifier 30 (RFA) work in the sheet again, (MixerI MixerQ) carries out the frequency down-converts of radio frequency to medium-frequency IF to output to quadrature down converter 40 and 50.For the ease of explanation, we are with cell frequency f
0=1.023MHz calculates radio frequency (1540f
0) and IF-FRE.In the navigation radio frequency chip, the IF-FRE of main flow is 4f
0Intermediate-frequency filter 60 (IF Filter) carries out channel to intermediate-freuqncy signal to be selected, and filtering out need be by the intermediate-freuqncy signal of demodulation in bandwidth, and outer any signal or the noise of bandwidth can be filtered fully.The bandwidth of navigation GPS is 2f
0, the bandwidth ratio 2f of general intermediate-frequency filter
0High slightly.This intermediate-freuqncy signal is after variable gain amplifier 70 (VGA) amplifies; The signal intensity that appropriateness is provided is to analog to digital converter 80 (ADC); Thereby convert analog intermediate frequency signal to comprise polarity S IGN and amplitude MAG two digits signal, these digital signals are exported to the digital baseband (not shown) and are done follow-up signal Processing at last.In Low Medium Frequency navigation radio-frequency transmitter system architecture; Because radio frequency chip needs independently to become a single-chip; So the amplitude MAG signal of analog to digital converter 80 outputs also feeds back to variable gain amplifier 70 through variable gain amplifier control circuit 90 (VGA Controller); As the detection of its signal intensity, so that this variable gain amplifier 70 can provide constant signal output for analog to digital converter 80.
Wherein, carry out the quadrature down converter 40 and 50 of radio frequency to medium-frequency IF down coversion, its local oscillator is provided by frequency synthesizer.No matter be integral frequency divisioil frequency synthesizer (Integer-N RFPLL) or fractional frequency division frequency synthesizer (Fractional-N RFPLL), frequency synthesizer phaselocked loop (RFPLL) generally comprises the backfeed loop that is connected to form by phase frequency detector 120 (PFD), charge pump 130 (CP), loop filter 140 (LPF), voltage controlled oscillator 150 (VCO), a set of division module.Wherein, phase frequency detector 120, (the navigation radio frequency chip is generally used 16f with feedback signal and canonical reference clock
0) compare; By the control of this comparative result, 130 pairs of loop filters of said charge pump 140 carry out charge or discharge, make the DC voltage after loop filter 140 output filterings, and the frequency of voltage controlled oscillator 150 is controlled.The local oscillation signal that voltage controlled oscillator 150 produces, after the frequency division processing via two-divider 160 (DIV2), pre-divider 170 (Prescaler), feedback divider 180 (Feedback Divider), feedback outputs to phase frequency detector 120; When the standard frequency of frequency of feeding back and reference equates; Phase frequency detector 120 these frequency synthesizer pll locks of control, the local frequency that this moment, voltage controlled oscillator 150 was exported are exactly N times (multiple N cooperates decision by said some frequency division modules 160,170,180) of reference clock.Because the system architecture of navigation radio frequency chip main flow is all selected the pressuring controlling oscillator frequency of two frequencys multiplication, i.e. 2 * 1536f
0, so the output of voltage controlled oscillator 150 exports said quadrature down converter 40 and 50 respectively to via two-divider 160 frequency divisions acquisition orthogonal local oscillation LOI and LOQ.
In general; In order to satisfy the high-precision requirement of navigation radio frequency chip to frequency; Crystal oscillator (TCXO by the outer temperature compensation of sheet; Do not draw) clock signal (TCXO_IN) that provides, after the shaping through clock isolation amplifier 100 (CLK BUF), be input into frequency synthesizer phaselocked loop (RFPLL) as the canonical reference clock.Meanwhile, this clock of clock isolation amplifier 100 outputs also offers analog to digital converter 80 as its sampling clock.This sampling clock finally also passes through the shaping of another one clock isolation amplifier 110 (CLK BUF), outputs to the outer navigation baseband chip of sheet and does the synchronous of data sampling.
Four Global Navigation System Global Navigation Satellite System (GNSS) are arranged at present in the world: the firstth, the GPS of USA navigational system; Its rf frequency is 1575.42MHz; Bandwidth is 2.046MHz, is containing the C/A sign indicating number of time and positional information in the bandwidth.The secondth, the GLONASS navigational system of Russia, its rf frequency is 1598.0625MHz to 1605.375MHz, bandwidth is 8MHz, is divided into 14 channels; Channel and channel be 0.5625MHz at interval, the bandwidth of each channel is 0.5625MHz; The 3rd is the Chinese Big Dipper COMPASS navigational system in two generations, and its rf frequency is 1561.098MHz, and bandwidth is 4.092MHz.The 4th is Galileo (Galileo) navigational system of European Union, and its rf frequency is 1575.42MHz, and bandwidth is 4.092MHz.
Use at present the most extensively, the navigational system of main flow is exactly the GPS of USA navigational system.By in February, 2011, there have been 22 GLONASS of the Russia Navsats that can run the sky.The COMPASS navigational system in two generations of the Big Dipper of China is more and more ripe, and there have been 9 Navsats the sky at present.The Big Dipper two generations expectation can cover the Asian-Pacific area and get into substantive operation in 2012.The Galileo of European Union (Galileo) navigational system speed of development is the most slowly.
Yet, no matter be government of Russia now, Chinese Government or European Union, it is unpractical that requirement and encourage consumer only use the navigational system of oneself.The first, number of satellite is insufficient, and the Glonass Navsat that just is Russia also is less than 24; The second, the ripe operation of Global Navigation System separately (GNSS) also needs more time.Referring to table 1; Therefore, if a twin-channel navigation radio-frequency transmitter is arranged, can receive the Glonass Navsat of GPS of America Navsat and Russia simultaneously on market; Or the while can receive the Big Dipper Compass Navsat of GPS of America Navsat and China; Or can receive simultaneously Galileo (Galileo) Navsat of GPS of America Navsat and European Union, it is comprehensively located will be more accurate, will have very high using value.
Table 1 is twin-channel maybe practical combination
As shown in Figure 2; In general; Twin-channel GNSS radio-frequency transmitter is provided with two separate signal passages and comes the corresponding two-way GNSS radiofrequency signal that receives; These two signalling channels are shared up to the first time RF front-end circuit during down-converted, for the first time down coversion frequency synthesizer phaselocked loop of local frequency is provided, and reference clock is provided and corresponds to the correlation module that analog-to-digital conversion process provides sampling clock to the frequency synthesizer phaselocked loop.
To pass through the intermediate-freuqncy signal of down-converted for the first time in the first passage; After converting the first intermediate frequency switching signal CH1_IF corresponding to first via radiofrequency signal; Be sent to variable gain amplifier 71 and amplify, outwards export the two digits signal that comprises polarity S IGN1, amplitude MAG1 by analog to digital converter 81 again; Variable gain amplifier control circuit 91 feeds back to the detection that variable gain amplifier 71 is used for signal intensity with amplitude MAG1 signal.
To pass through in the second channel for the first time, the intermediate-freuqncy signal of down-converted for the second time; After converting the second intermediate frequency switching signal CH2_IF corresponding to the second tunnel radiofrequency signal; Variable gain amplifier 72, analog to digital converter 82 through being provided with in addition in the second channel are handled, and obtain the digital signal of polarity S IGN2 and amplitude MAG2; Variable gain amplifier control circuit 92 feeds back to variable gain amplifier 72 with amplitude MAG2 signal.
Though the binary channels GNSS receiver of this framework; Can independent processing two-way radiofrequency signal; But follow-up digital signal through analog to digital conversion output also can be two covers independently, comprises polar signal SIGN1 and SIGN2; Range signal MAG1 and MAG2, and handle after two sampling clock CLK_OUT1 and CLK_OUT2 that clock isolation amplifier 101,102 is exported respectively by shared sampling clock module 11.Compare single pass framework, this binary channels GNSS radio-frequency transmitter can take the IO output pin of twice, needs bigger cost of manufacture, and also is difficult to compatibility with the single channel radio-frequency transmitter.
The utility model content
The purpose of the utility model provides a kind of binary channels radio-frequency transmitter of multiplexing analog to digital conversion output; This receiver can receive two-way GNSS radio frequency navigation signal simultaneously; After in signalling channel separately, carrying out data processing, the polarity, the range signal that obtain through analog to digital conversion in same set of these two passages of IO pin output, and analog-to-digital SF; Thereby it is the saving packaging cost, and compatible mutually with the output pin of single channel radio-frequency transmitter.
The technical scheme of the utility model provides a kind of binary channels radio-frequency transmitter of multiplexing analog to digital conversion output.
The binary channels radio-frequency transmitter of described multiplexing analog to digital conversion output; Be provided with first, second passage and come corresponding two-way radiofrequency signal RF1, the RF2 of receiving; Radiofrequency signal is converted to after corresponding first, second intermediate frequency switching signal CH1_IF, the CH2_IF separately, and the subsequent conditioning circuit in said two passages sends respectively;
In first, second passage; Be provided with variable gain amplifier and analog to digital converter separately; In these two passages, respectively first, second intermediate frequency switching signal CH1_IF, CH2_IF after amplifying are carried out analog to digital conversion; Obtain the polar signal SIGN1 and the range signal MAG1 of first passage, and the polar signal SIGN2 of second channel and range signal MAG2; Also be provided with the variable gain amplifier control circuit in first, second passage separately, range signal MAG1, MAG2 wherein fed back to the variable gain amplifier of correspondence;
Said two passages are also shared multiplexing handover module; Come the analog-digital conversion data of first, second passage is carried out multiplexing process; Obtain changing the polarity composite signal SIGN that forms, and change the amplitude composite signal MAG that forms by said two range signal MAG1, MAG2 by said two polar signal SIGN1, SIGN2;
When said two analog to digital converters carry out analog to digital conversion, use identical sampling clock CLK; Said multiplexing handover module also receives said sampling clock CLK, and is translated into the sampling output clock CLK_OUT that is used for data sync;
Said multiplexing handover module is provided with some IO output pins, comprises respectively that the digital baseband outside sheet sends said polarity composite signal SIGN, said amplitude composite signal MAG, and one group of port of said sampling output clock CLK_OUT.
Said two passages are shared RF front-end circuit carries out the down-converted first time to said two-way radiofrequency signal RF1, the RF2 that receives; Required local frequency LOI, the LOQ of down coversion provided by two shared frequency synthesizer phaselocked loops of passage for the first time;
In the said RF front-end circuit, comprise the outer acoustic filter of low noise amplifier, sheet, radio frequency prime amplifier and the quadrature down converter that connect successively;
In the said frequency synthesizer phaselocked loop, comprise the backfeed loop that connects and composes by phase frequency detector, charge pump, loop filter, voltage controlled oscillator, two-divider, pre-divider and feedback divider.
In said first passage; Also be included in the intermediate-frequency filter that is provided with after the said quadrature down converter; It carries out Filtering Processing to down coversion first time intermediate-freuqncy signal afterwards, obtains the corresponding first intermediate frequency switching signal CH1_IF with first via radiofrequency signal RF1;
In said second channel; Also be included in the double down converter and the intermediate-frequency filter that are provided with after the said quadrature down converter; To the intermediate-freuqncy signal after the first time down coversion carry out the second time down coversion and Filtering Processing after, obtain the second intermediate frequency switching signal CH2_IF corresponding with the second tunnel radiofrequency signal RF2.
Said two passages are also shared connect successively with lower module:
A clock isolation amplifier after its clock signal to the outside input is carried out shaping, is sent to said frequency synthesizer phaselocked loop with the reference clock Ref CLK that obtains;
A sampling clock module, it is according to the said reference clock Ref CLK that receives, and local frequency LOI, LOQ that said frequency synthesizer phaselocked loop is sent carry out the frequency division processing, obtain SF;
A clock isolation amplifier, its with the SF shaping after, send identical sampling clock CLK and give said two analog to digital converters and said multiplexing handover module.
Sampling clock CLK with input in said multiplexing handover module obtains delayed clock CLK_SEL after carrying out certain time-delay, setting and retention time when carry out multiplexing output and handle as said multiplexing handover module this time delay;
The multiplexing output information OUTPUT of said multiplexing handover module output comprises the analog-digital conversion data of first passage and second channel simultaneously;
And when said delayed clock CLK_SEL was high level, said multiplexing output information OUTPUT was the analog-digital conversion data of a passage in first passage or the second channel; When said delayed clock CLK_SEL was low level, said multiplexing output information OUTPUT was the analog-digital conversion data of another passage wherein.
The sampling output clock CLK_OUT of said multiplexing handover module output carries out obtaining after the certain time-delay to delayed clock CLK_SEL;
When sampling output clock CLK_OUT rising edge triggered, the sheet external circuit restored the analog-digital conversion data of a passage in first passage or the second channel from said multiplexing output information OUTPUT; When sampling output clock CLK_OUT negative edge triggers, restore the wherein analog-digital conversion data of another passage.
Said delayed clock CLK_SEL forms 1/4 all after date of sampling clock CLK time-delay; When delayed clock CLK_SEL was high level, said multiplexing output information OUTPUT was the analog-digital conversion data of first passage; When delayed clock CLK_SEL was low level, said multiplexing output information OUTPUT was the analog-digital conversion data of second channel;
Said sampling output clock CLK_OUT formed said 1/4 cycle of delayed clock CLK_SEL time-delay, and, said sampling output clock CLK_OUT be said sampling clock CLK through 1 grade the clock after reverse;
When said sampling output clock CLK_OUT rising edge triggered, from said multiplexing output information OUTPUT, reduction obtained the data after the analog-digital conversion data time-delay half period of first passage; When sampling output clock CLK_OUT is a negative edge when triggering, reduction obtains the data after the analog-digital conversion data time-delay half period of second channel.
Compared with prior art, the binary channels radio-frequency transmitter of the said multiplexing analog to digital conversion output of the utility model, its advantage is:
Parameters such as the bandwidth that the utility model is selected through reference clock, local frequency, sampling clock, the channel of controlling first passage and second channel respectively, intermediate-freuqncy signal; Make first passage carry out the down coversion first time; Second channel carries out for the first time, for the second time after the down-converted; Can correspondingly receive two-way GNSS radio frequency navigation signal, thereby improve the accuracy of navigator fix.Simultaneously, owing to shared RF front-end module and frequency synthesizer phaselocked loop etc., this binary channels navigation radio-frequency transmitter system architecture can be saved power consumption, reduces cost, and has good application value.
After using identical sampling clock to carry out analog-to-digital conversion process separately in two passages of the utility model; Multiplexing handover module by shared carries out multiplexing conversion process to the double-channel analog/digital translation data; And with multiplexing polar signal, range signal, and the sampling output clock that is used for data sync, through outwards exporting with the on all four one group of IO output pin of single channel navigation radio-frequency transmitter; Saved the Chip Packaging cost, can also be compatible with single-channel receiver.
The utility model based on first, second passage to analog-to-digital output timing requirement; 1/4 cycle formed delayed clock CLK_SEL through delaying time; According to the difference of this delayed clock CLK_SEL high-low level, the multiplexing output information OUTPUT that multiplexing handover module is exported corresponds to the analog-digital conversion data of first passage or second channel.Form sampling output clock CLK_OUT through 1/4 cycle of time-delay again,, from multiplexing output information OUTPUT, restore the analog-digital conversion data of these two passages by the sheet external circuit according to this sampling output clock CLK_OUT.The described data processing method of the utility model is easy to realize that reliability is high.
Description of drawings
Fig. 1 is the synoptic diagram of existing a kind of single pass navigation radio-frequency transmitter chip architecture;
Fig. 2 is the synoptic diagram of existing a kind of twin-channel navigation radio-frequency transmitter chip architecture;
Fig. 3 is the chip architecture synoptic diagram of the binary channels navigation radio-frequency transmitter of the said multiplexing analog to digital conversion output of the utility model;
Fig. 4 is the sequential synoptic diagram of the said navigation radio-frequency transmitter of the utility model multiplexing analog-digital conversion data in GPS and the twin-channel embodiment of GLN;
Fig. 5 is the signal Processing synoptic diagram of the said navigation radio-frequency transmitter of the utility model handover module in GPS and the twin-channel embodiment of GLN;
Fig. 6 be the said navigation radio-frequency transmitter of the utility model in GPS and the twin-channel embodiment of GLN from the output signal of handover module the reduction double-channel signal synoptic diagram.
Embodiment
Embodiment below in conjunction with description of drawings the utility model.
As shown in Figure 3, the binary channels navigation radio-frequency transmitter of the said multiplexing analog to digital conversion output of the utility model is provided with first, second passage and comes the corresponding two-way GNSS radiofrequency signal that receives.Described two-way GNSS radiofrequency signal can be the combination of any one double-channel signal in the table 1.
At first, receive the GNSS rf modulated signal, and accomplish the down-converted first time this signal by the shared RF front-end circuit of first, second passage; Carry out required local frequency LOI, the LOQ of down coversion for the first time, a frequency synthesizer phaselocked loop (RFPLL) shared by first, second passage provides.In the said RF front-end circuit, comprise successively the outer acoustic filter 2 (SAW FILTER) of low noise amplifier 1 (LNA), sheet, radio frequency prime amplifier 3 (RFA) and the quadrature down converter 4 and 5 that connect (MixerI, MixerQ).In the said frequency synthesizer phaselocked loop, comprise the backfeed loop that connects and composes by phase frequency detector 12 (PFD), charge pump 13 (CP), loop filter 14 (LPF), voltage controlled oscillator 15 (VCO), two-divider 16 (DIV2), pre-divider 17 (Prescaler), feedback divider 18 (Feedback Divider).Respective modules basically identical in the circuit framework of these modules and signal processing and existing single channel or the binary channels radio-frequency transmitter.
In addition; With basically identical in the existing binary channels radio-frequency transmitter; The intermediate-freuqncy signal that the first time, down-converted obtained in the utility model is handled through intermediate-frequency filter 61 in first passage, obtains the first intermediate frequency switching signal CH1_IF corresponding with first via radiofrequency signal.The intermediate-freuqncy signal of down-converted via after double down converter 52 and intermediate-frequency filter 62 processing, obtains the second intermediate frequency switching signal CH2_IF corresponding with the second tunnel radiofrequency signal in second channel for the first time.Described intermediate frequency switching signal CH1_IF and CH2_IF are respectively in first, second passage; After the variable gain amplifier that is provided with respectively 71,72 amplifications; Each free analog to digital converter 81,82 is handled and is obtained the two digits signal again; That is, the polar signal SIGN1 of first passage and range signal MAG1, the polar signal SIGN2 of second channel and range signal MAG2.Variable gain amplifier control circuit 91,92 is again with range signal MAG1, the MAG2 of correspondence, and the variable gain amplifier 71,72 of passage is used for the detection of signal intensity under feeding back to respectively.
As shown in table 2 is more common several kinds of double-channel signals combination, for example be GPS of America respectively with Russian Glonass, the Chinese Big Dipper or European Union's Galileo in a kind of composition binary channels.The intermediate frequency planning that provides for each passage and the frequency scheme of analog to digital conversion SF have been provided according to different reference clocks in the table 2.
The twin-channel reference clock of table 2, intermediate frequency, bandwidth and ADC clock
Can know that by last table in each binary channels combination, the sampling clock CLK that said two analog to digital converters 81,82 use is identical.This sampling clock CLK provides after being handled successively by a shared sampling clock module 11 of first, second passage (ADC CLK GEN) and a clock isolation amplifier 101 (CLK BUF).After local frequency LOI, the LOQ that said sampling clock module 11 is exported according to the frequency synthesizer phaselocked loop carries out frequency division to reference clock Ref CLK; Carry out shaping by clock isolation amplifier 101 again and handle, the sampling clock CLK that obtains thus is sent to 81,82 and multiplexing handover modules 103 of described two analog to digital converters (ADC MUX) simultaneously.Said reference clock Ref CLK is the clock signal (TCXO_IN) of the outer input of sheet, via what obtain after another clock isolation amplifier 10 shapings.
Described multiplexing handover module 103 is also shared by first, second passage; It is to two the polar signal SIGN1 and the SIGN2 of 81,82 outputs of said two analog to digital converters; Reach two range signal MAG1 and MAG2 and carry out conversion processing; And with polarity composite signal SIGN that obtains and amplitude composite signal MAG, wherein two ports of the same set of IO output pin through this multiplexing handover module 103, the digital baseband outside sheet sends.Said multiplexing handover module 103 also is provided with the 3rd port, and the sampling clock CLK that analog to digital conversion is used carries out obtaining sampling output clock CLK_OUT after the certain time-delay, and should sample and export clock CLK_OUT and outside sheet, send, and is used as data sync.
Because in first passage, analog-to-digital output timing required be, when sampling clock CLK carries out data output during for high level; Carry out data during for low level and keep the data consistent when making its polar signal SIGN1 and range signal MAG1 and high level.On the contrary, in second channel, its analog-to-digital output timing requires to be output data when sampling clock CLK is low level; Keep data, the data consistent when making its polar signal SIGN2 and range signal MAG2 and low level during for high level.
Therefore, can in said multiplexing handover module 103, pass through the high-low level of CLK_SEL (CLK is through certain delay), final polarity composite signal SIGN and the amplitude composite signal MAG that on the IO output pin, outwards exports of decision.For example, when CLK_SEL is low level, select final signal to be output as the polar signal SIGN2 and the range signal MAG2 of second channel; And when sampling output clock CLK_SEL was high level, selecting final output signal was the polar signal SIGN1 and the range signal MAG1 of first passage.And because when finally being output as the first passage data, the data of second channel are maintained and can not omit; Same, when finally being output as the second channel data, the data of first passage can not omitted yet.In addition, can also in multiplexing handover module 103, carry out certain delay, guarantee to export the required time of setting (setup) sampling clock CLK.
It below is concrete elaboration to the above-mentioned implementation process of the utility model binary channels radio-frequency transmitter; Wherein all will receive and handle GPS of America signal (being designated hereinafter simply as the GPS passage) with first passage; Second channel receives Russian Glonass signal (following replace Glonass with GLN, and abbreviate the GLN passage as) and describes for example.Hereinafter also with the data message of exporting in the GPS passage, promptly the SIGN1 of first passage and MAG1 signal abbreviate gps data as; And with the data message of exporting in the GLN passage, promptly the SIGN2 of second channel and MAG2 signal abbreviate the GLN data as.
As shown in Figure 4 be the GPS passage with the GLN passage in the sequential of analog-digital conversion data is required: GPS passage and the identical sampling clock CLK of GLN passage use.When sampling clock CLK for high level time output gps data, at this moment, the GLN data remain on the state of CLK when being low level.When sampling clock CLK for low level time output GLN data, at this moment, gps data remains on the state of CLK when being high level.
On the basis of Fig. 4, cooperate referring to shown in Figure 5, the multiplexing process process of 103 pairs of signals of multiplexing handover module is described.Wherein, delayed clock CLK_SEL carries out forming after the time-delay in 1/4 cycle to the sampling clock CLK that imports multiplexing handover module 103.The benefit of doing like this is when on GPS and GLN passage, carrying out intelligence sample, setting (setup) time and maintenance (hold) time about 1/4 cycle to have been arranged.
When delayed clock CLK_SEL was high level, by the multiplexing output information OUTPUT (being polarity composite signal SIGN and amplitude composite signal MAG, down together) that multiplexing handover module 103 sends outside sheet, essence was gps data; When delayed clock CLK_SEL was low level, multiplexing output information OUTPUT essence was the GLN data.In OUTPUT curve shown in Figure 5, N representes to be output as the GLN data, and S representes to be output as gps data.It is thus clear that the high-low level control through delayed clock CLK_SEL can comprise the data message of GPS and GLN passage simultaneously in multiplexing output information OUTPUT.
On the basis of Fig. 4, Fig. 5; Further cooperate referring to shown in Figure 6; The sampling output clock CLK_OUT that multiplexing handover module 103 is sent to sheet in addition; On the basis of delayed clock CLK_SEL, postponing for 1/4 cycle again forms, thereby this sampling output clock CLK_OUT is the equal of said sampling clock CLK through 1 grade of clock after oppositely.At this moment, in the said binary channels of the utility model navigation radio-frequency transmitter, handle the data message that obtains through multiplexing handover module 103, can be compatible fully with the data-signal that obtains in the single channel GPS navigation radio-frequency transmitter.
That is to say that the high-low level according to said sampling output clock CLK_OUT can restore wherein GPS and GLN data from multiplexing output information OUTPUT.In Fig. 6; By sampling output clock CLK_OUT; Multiplexing output information OUTPUT is carried out rising edge trigger, just can obtain a new data message GPS ', these data GPS ' carries out the delay of half period to the gps data that first passage is exported; In addition, data GPS ' and gps data basically identical.Likewise, by sampling output clock CLK_OUT, multiplexing output information OUTPUT is carried out negative edge trigger, the data message that obtains is GLN ', is equivalent to the GLN data of second channel output have been carried out the delay of half period.
In addition, to the multiplex process of analog to digital conversion output, can be extended to other binary channels combinations in table 1 for example or the table 2 among above-mentioned use GPS of the utility model and the twin-channel embodiment of GLN.Therefore; With the binary channels radio-frequency transmitter that uses the said framework of the utility model; Through first passage, the corresponding demodulation of accomplishing the two-way radiofrequency signal of second channel; And the data processing method of in said multiplexing handover module 103, two channel multiplexing analog to digital conversion being exported afterwards, be summarised as following step:
In first passage, output data when sampling clock CLK is high level; Keep data, the data consistent when making its polar signal SIGN1 and range signal MAG1 and high level during for low level;
In second channel, output data when sampling clock CLK is low level; Keep data, the data consistent when making its polar signal SIGN2 and range signal MAG2 and low level during for high level.
Step 2, the sampling clock CLK that imports multiplexing handover module 103 is carried out certain delay, obtain a delayed clock CLK_SEL, setting and the retention time of this time-delay during as multiplexing output;
According to this delayed clock CLK_SEL, the analog-digital conversion data to two passages in said multiplexing handover module 103 transforms, and with polarity composite signal SIGN that obtains and amplitude composite signal MAG, exports outside sheet as its multiplexing output information OUTPUT;
To the above embodiments, when delayed clock CLK_SEL was high level, the multiplexing output information OUTPUT of transmission was the polar signal SIGN1 and the range signal MAG1 of first passage; When delayed clock CLK_SEL was low level, multiplexing output information OUTPUT was the polar signal SIGN2 and the range signal MAG2 of second channel.
In the time of the above-mentioned multiplexing output information OUTPUT of step 3, output,, use when supplying the data message of two passages among the said multiplexing output information OUTPUT of follow-up reduction by multiplexing handover module 103 outputs one sampling output clock CLK_OUT;
Said sampling output clock CLK_OUT obtains after delayed clock CLK_SEL is further postponed, thereby makes this sampling output clock CLK_OUT be equivalent to the clock that obtains behind the reverse and delay some cycles of said sampling clock CLK;
Thereby; Same to the above embodiments; Exporting clock CLK_OUT according to said sampling; In the process that multiplexing output information OUTPUT is reduced, when sampling output clock CLK_OUT negative edge triggered, the information that obtains was the polar signal SIGN2 and the range signal MAG2 of the second channel after the corresponding delay; And when sampling output clock CLK_OUT was the rising edge triggering, the signal that obtains was the polar signal SIGN1 and the range signal MAG1 of the first passage after the corresponding delay.
Need to prove, above-mentioned when setting delayed clock CLK_SEL or sampling output clock CLK_OUT, also can set other time delay.For example, when forming described delayed clock CLK_SEL, can be sampling clock CLK to be postponed (a+1/4) individual cycle (a for more than or equal to 0 integer), come control setting (setup) time and maintenance (hold) time.Perhaps; When the described sampling output of formation clock CLK_OUT; Can be delayed clock CLK_SEL to be postponed (b+1/4) individual cycle (b is the integer more than or equal to 0), thereby make sampling output clock CLK_OUT become the clock that said sampling clock CLK is reverse and postpone respective cycle.Or; Can also be when the described sampling output of formation clock CLK_OUT; Delayed clock CLK_SEL is postponed (c+3/4) individual cycle (c be the integer more than or equal to 0), thereby make sampling output clock CLK_OUT become said sampling clock CLK in the same way and the clock of delay respective cycle.In above-mentioned three kinds of possible embodiment; Compare the data of the multiplexing handover module 103 of input; The data message that last multiplexing output or reduction obtain; The delay in corresponding several semiperiods or several cycles will occur, and the data of using rising edge or negative edge triggering to obtain specifically are that corresponding which passage also may be opposite.Therefore, need to carry out concrete analysis to the embodiment that provides different time delays.
In sum; The said binary channels navigation of the utility model radio-frequency transmitter can binary channels receive two GNSS radiofrequency signals, thereby improve the accuracy of location; And; Be provided with multiplexing handover module especially, the data of double-channel analog/digital conversion output are carried out conversion process, and the multiplexing output data that will obtain outwards exported.Because the said binary channels navigation of the utility model radio-frequency transmitter has and the on all four exterior I O output pin of single channel navigation radio-frequency transmitter, can save the Chip Packaging cost, again can be compatible with single-channel receiver, as its upgraded version.
Although the content of the utility model has been done detailed introduction through above-mentioned preferred embodiment, will be appreciated that above-mentioned description should not be considered to the restriction to the utility model.After those skilled in the art have read foregoing, for the multiple modification of the utility model with to substitute all will be conspicuous.Therefore, the protection domain of the utility model should be limited appended claim.
Claims (4)
1. the binary channels radio-frequency transmitter of a multiplexing analog to digital conversion output; It is characterized in that; Be provided with first, second passage and come the corresponding two-way radiofrequency signal (RF1, RF2) that receives; Convert radiofrequency signal to corresponding first, second intermediate frequency switching signal (CH1_IF, CH2_IF) separately afterwards, the subsequent conditioning circuit in said two passages sends respectively;
In first, second passage; Be provided with variable gain amplifier (71,72) and analog to digital converter (81,82) separately; In these two passages, respectively first, second intermediate frequency switching signal (CH1_IF, CH2_IF) after amplifying is carried out analog to digital conversion; Obtain the polar signal (SIGN1) and the range signal (MAG1) of first passage, and polar signal of second channel (SIGN2) and range signal (MAG2); Also be provided with variable gain amplifier control circuit (91,92) in first, second passage separately, range signal (MAG1, MAG2) wherein fed back to the variable gain amplifier (71,72) of correspondence;
Said two passages are an also shared multiplexing handover module (103); Come the analog-digital conversion data of first, second passage is carried out multiplexing process; Obtain the polarity composite signal (SIGN) that forms by said two polar signals (SIGN1, SIGN2) conversions, and the amplitude composite signal (MAG) that forms by said two range signals (MAG1, MAG2) conversion;
Said two analog to digital converters (81,82) use identical sampling clock (CLK) when carrying out analog to digital conversion; Said multiplexing handover module (103) also receives said sampling clock (CLK), and is translated into the sampling output clock (CLK_OUT) that is used for data sync;
Said multiplexing handover module (103) is provided with some IO output pins; Comprise respectively that the digital baseband outside sheet sends said polarity composite signal (SIGN), said amplitude composite signal (MAG), and one group of port of said sampling output clock (CLK_OUT).
2. the binary channels radio-frequency transmitter of multiplexing analog to digital conversion output as claimed in claim 1 is characterized in that,
Said two passages are shared RF front-end circuit carries out the down-converted first time to the said two-way radiofrequency signal (RF1, RF2) that receives; The required local frequency (LOI, LOQ) of down coversion is provided by two shared frequency synthesizer phaselocked loops of passage for the first time;
In the said RF front-end circuit, comprise the outer acoustic filter (2) of low noise amplifier (1), sheet, radio frequency prime amplifier (3) and the quadrature down converter (4,5) that connect successively;
In the said frequency synthesizer phaselocked loop, comprise the backfeed loop that connects and composes by phase frequency detector (12), charge pump (13), loop filter (14), voltage controlled oscillator (15), two-divider (16), pre-divider (17) and feedback divider (18).
3. the binary channels radio-frequency transmitter of multiplexing analog to digital conversion output as claimed in claim 2 is characterized in that,
In said first passage; Also be included in the intermediate-frequency filter (61) that said quadrature down converter (4,5) is provided with afterwards; It carries out Filtering Processing to down coversion first time intermediate-freuqncy signal afterwards, obtains and the corresponding first intermediate frequency switching signal (CH1_IF) of first via radiofrequency signal (RF1);
In said second channel; Also be included in double down converter (52) and intermediate-frequency filter (62) that said quadrature down converter (4,5) is provided with afterwards; To the intermediate-freuqncy signal after the first time down coversion carry out the second time down coversion and Filtering Processing after, obtain the second intermediate frequency switching signal (CH2_IF) corresponding with the second tunnel radiofrequency signal (RF2).
4. the binary channels radio-frequency transmitter of multiplexing analog to digital conversion output as claimed in claim 3 is characterized in that,
Said two passages are also shared connect successively with lower module:
A clock isolation amplifier (10), after its clock signal to the outside input was carried out shaping, (Ref CLK) was sent to said frequency synthesizer phaselocked loop with the reference clock that obtains;
A sampling clock module (11), it carries out the frequency division processing according to the said reference clock (Ref CLK) that receives to the local frequency (LOI, LOQ) that said frequency synthesizer phaselocked loop sends, and obtains SF;
A clock isolation amplifier (101), its with the SF shaping after, send identical sampling clock (CLK) and give said two analog to digital converters (81,82) and said multiplexing handover module (103).
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| CN2011204161199U CN202404236U (en) | 2011-10-27 | 2011-10-27 | Binary channel radio frequency receiver of multiplexing analog-to-digital conversion output |
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| CN2011204161199U CN202404236U (en) | 2011-10-27 | 2011-10-27 | Binary channel radio frequency receiver of multiplexing analog-to-digital conversion output |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102508262A (en) * | 2011-10-27 | 2012-06-20 | 上海迦美信芯通讯技术有限公司 | Double-channel radiofrequency receiver capable of realizing multiplex analog-to-digital conversion output and data processing method of double-channel radiofrequency receiver |
| CN111812686A (en) * | 2020-07-21 | 2020-10-23 | 山东大学 | Navigation signal receiver and clock distribution method thereof |
| CN112332892A (en) * | 2020-10-26 | 2021-02-05 | 北京邮电大学 | Transceiver, receiving method and transmitting method |
-
2011
- 2011-10-27 CN CN2011204161199U patent/CN202404236U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102508262A (en) * | 2011-10-27 | 2012-06-20 | 上海迦美信芯通讯技术有限公司 | Double-channel radiofrequency receiver capable of realizing multiplex analog-to-digital conversion output and data processing method of double-channel radiofrequency receiver |
| CN102508262B (en) * | 2011-10-27 | 2013-07-31 | 上海迦美信芯通讯技术有限公司 | Double-channel radiofrequency receiver capable of realizing multiplex analog-to-digital conversion output and data processing method of double-channel radiofrequency receiver |
| CN111812686A (en) * | 2020-07-21 | 2020-10-23 | 山东大学 | Navigation signal receiver and clock distribution method thereof |
| CN111812686B (en) * | 2020-07-21 | 2023-07-14 | 山东大学 | Navigation signal receiver and clock distribution method thereof |
| CN112332892A (en) * | 2020-10-26 | 2021-02-05 | 北京邮电大学 | Transceiver, receiving method and transmitting method |
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