CN202394543U - Clock-controlled asynchronous FIFO (first in-first out) memory - Google Patents

Abstract

The utility model relates to a memory, in particular to a clock-controlled asynchronous FIFO (first in-first out) memory, which is used for buffering data among different clock domains in an integrated circuit chip. The clock-controlled asynchronous FIFO memory comprises a dual-port SRAM (static random access memory), a writing line control unit of the SRAM, a reading line control unit of the SRAM and a mark unit, wherein the writing line control unit of the SRAM is divided into two channels, one channel of the writing line control unit is electrically connected with a writing line control end of the dual-port SRAM, the other channel of the writing line control unit is electrically connected with an input end of the mark unit, a Gray code reading conversion unit of the SRAM is divided into two channels, one channel of the Gray code reading conversion unit is electrically connected with a reading line control end of the dual-port SRAM, the other channel of the Gray code reading conversion unit is electrically connected with another input end of the mark unit, the mark unit is respectively connected with input ends of a full-generation logic unit, and another channel of the mark unit is electrically connected with an input end of an empty-generation logic unit.

Description

A kind of clock controlled asynchronous FIFO FIFO storer

Technical field

The utility model relates to a kind of storer, and particularly a kind of clock controlled asynchronous FIFO FIFO storer is used for the data buffering between the IC chip different clock-domains.

Background technology

In the modern IC chip,, often contain several clocks in the system along with the continuous expansion of design scale.The problem that multi-clock zone brings is exactly how to design the interface circuit between the asynchronous clock.Asynchronous FIFO is to address this problem a kind of simple, fast solution.Use asynchronous FIFO can be between two different clocks systems speed and convenience ground transmitting real-time data.At aspects such as network interface, Flame Image Process, asynchronous FIFO has obtained using widely.Async-generic FIFO has two and independently reads and writes clock; Its transmission data use a clock zone that data value is write the FIFO buffer memory in regular turn; Re-use another clock zone, according to order sense data value from FIFO of FIFO, these two clock zones are separate and inequality.

No matter be what type FIFO, its key point is to produce to read, write address and empty, full sign.Common good FIFO design, its basic demand is: write full without flowing overly to go out, can read sky and non-mutiread.Therefore, how empty, the full scale will of ways of producing correct FIFO is asynchronous FIFO design key of success.Design FIFO exists two big difficult points: the one, and synchronous asynchronous signal how, the elimination trigger produces metastable problem; The 2nd, how correct empty full the and near-space of design completely wait the generation circuit of signal.For fear of metastable state, adopt following method usually: 1. Gray code is adopted in write address/read address.Can know that by practice the probability that metastable probability is far longer than a synchronous asynchronous signal appears in synchronous a plurality of asynchronous input signals.The write address that the output of a plurality of triggers is formed/read the address can adopt Gray code.Because Gray code only changes one at every turn, adopt Gray code can reduce metastable generation effectively.2. adopt trigger to come the synchronous asynchronous input signal.The generation of empty full scale will is the core of FIFO.The logic of this part of correct design how directly has influence on the performance of FIFO.Common practices is to adopt read/write address to compare to produce empty full scale will.When the difference of read/write address equaled a preset value, empty/full signal was set.This implementation method logic is simple, but it is the bigger combinational logic that subtracter forms, thereby has limited the speed of FIFO.

The structure of typical asynchronous FIFO is as shown in Figure 1.Reading the address is to be produced by the address control module of reading of reading the clock triggering, and write address is to be produced by the write address control module of writing the clock triggering, produce the empty full scale will of FIFO, and the read/write address that is in different clock zones must compare.In order to reduce metastable risk, the binary code read/write address need convert Gray code to, and this process is accomplished by the Gray code conversion module.Read/write address Gray code after the conversion is synchronous through trigger in the full signal generator module of sky, and the read/write address Gray code after synchronously restores into binary code and compares, and produces empty full signal.

The asynchronous FIFO that adopts said method to realize has following shortcoming:

1. the mutual conversion of scale-of-two and Gray code has increased hardware complexity;

2. when read/write address is compared, often adopt subtraction, this has also increased hardware complexity, has increased the time-delay of circuit simultaneously.

Summary of the invention

The purpose of the utility model is to avoid the deficiency of above-mentioned technology, and a kind of clock controlled asynchronous FIFO memory is provided, and to reduce the complexity of circuit, avoids the use of the subtraction device, improves the speed of circuit.

For realizing above-mentioned purpose; The technical scheme of the utility model is: a kind of clock controlled asynchronous FIFO FIFO storer; Comprise: the write word line control module of double-port random static memory SRAM, SRAM, the readout word line control module of SRAM, tag unit; The write word line control module of SRAM divides two-way, one we be electrically connected with the line traffic control end that writes of double-port random static memory SRAM, another road is electrically connected with the tag unit input end; The Gray code conversion unit of reading of SRAM divides two-way, and one the tunnel is electrically connected with the readout word line control end of double-port random static memory SRAM, and another input end of another road and tag unit is electrically connected; Tag unit is electrically connected with the living logical block input end of producing at full capacity respectively, and another road is electrically connected with the empty logical block input end that produces.

Described write word line control module comprises the first chain of registers D1 and first group and a door A1; First chain of registers is joined end to end by the first register D10, the second register D11, the 3rd register D12 and the 3rd register D13 and constitutes, and first group constitutes with A13 with door A12 and the 4th with door A11, the 3rd with a door A10, second by first with door A1; The output of the first register D10 is connected to the data input pin of the second register D11; The output of the second register D11 is connected to the data input pin of the 3rd register D12; The output of the 3rd register D12 is connected to the data input pin of the 4th register D13, and the output of the 4th register D13 is connected to the data input pin of the first register D10; Outside input write clock signal wclk writes with outside input after through not gate I00 anti-phase and enables wen signal process and write door controling clock signal wclk_gated with door A00 with generation; Write the input end of clock that door controling clock signal wclk_gated is connected to the first register D10, the second register D11, the 3rd register D12 and the 4th register D13 respectively; Write the data input pin that door controling clock signal wclk_gated is connected to latch L10 after through not gate I01 anti-phase, write the Enable Pin that clock wclk signal is connected to latch L10; The output of latch L10 enables wen signal process and door A01 and generation write word line enable signal wwlen with writing; The output of the write word line enable signal wwlen and the first register D10 through first with door A10 with after output be connected to the write word line wwl0 of SRAM; The output of the write word line enable signal wwlen and the second register D11 through with door A11 with after output be connected to the write word line wwl1 of SRAM; The output of write word line enable signal wwlen and the 3rd register D12 through with door A12 with after output be connected to the write word line wwl2 of SRAM, the output of write word line enable signal wwlen and the 4th register D13 pass through with door A13 with after output be connected to the write word line wwl3 of SRAM.

Described readout word line control module comprises the second chain of registers D2 and second group and a door A2; Second chain of registers is joined end to end by the 5th register D20, the 6th register D21, the 7th register D22 and the 8th register D23 and constitutes, second group with the door A2 by the 5th with the door A20, the 6th with the door A21, the 7th with the door A22 and the 8th with the door A23 constitute; The output of the 5th register D20 is connected to the data input pin of the 6th register D21; The output of the 6th register D21 is connected to the data input pin of the 7th register D22; The output of the 7th register D22 is connected to the data input pin of the 8th register D23, and the output of the 8th register D23 is connected to the data input pin of the 5th register D20; Outside input is write clock rclk and is write with outside input after through not gate I02 anti-phase and enable ren signal process and read door controling clock signal rclk_gated with door A02 with generation.Read the input end of clock that door controling clock signal rclk_gated is connected to the 5th register D20, the 6th register D21, the 7th register D22 and the 8th register D23 respectively; The output of reading enable signal ren and the 5th register D20 through the 5th with door A20 with after output be connected to the readout word line rwl0 of SRAM; The output of reading enable signal ren and the 6th register D21 through the 6th with door A21 with after output be connected to the readout word line rwl1 of SRAM; The output of reading enable signal ren and the 7th register D22 through the 7th with door A22 with after output be connected to the readout word line rwl2 of SRAM, the output of reading enable signal ren and the 8th register D23 through the 8th with an A23 with after output be connected to the readout word line rwl3 of SRAM.

The readout word line control module also comprises one group of 32 register D0; The sense data line of SRAM is connected to this 32 register D0; Read the input end of clock that door controling clock signal rclk_gated is connected to these 32 register D0, the output of these 32 register D0 is outside output data_out.

Described zone bit unit comprises four zone bits, first zone bit, second zone bit, the 3rd zone bit and the 4th zone bit; Wherein:

First zone bit is made up of with door A40, the first nmos pass transistor N10, the 5th nmos pass transistor N20 and the 9th nmos pass transistor N30 with door A30, the 13 the first bistable circuit S0, the 9th; The drain terminal of the first nmos pass transistor N10 is connected with the antinodal points f10 of the first bistable circuit S0, and the grid end of the first nmos pass transistor N10 is connected with the output terminal of door A30 with the 9th, and the source end of the first nmos pass transistor N10 is connected with ground; The drain terminal of the 5th nmos pass transistor N20 is connected with the positive node f00 of the first bistable circuit S0, and the grid end of the 5th nmos pass transistor N20 is connected with the output terminal of door A40 with the 13, and the source end of the 5th nmos pass transistor N20 is connected with ground; The drain terminal of the 9th nmos pass transistor N30 is connected with the positive node f00 of the first bistable circuit S0, and the output of the grid end Sheffer stroke gate I03 of the 9th nmos pass transistor N30 connects, and the source end of the 9th nmos pass transistor N30 is connected with ground; The 9th with the door A30 an input end be connected with the antinodal points f10 of the first bistable circuit S0, another input end is connected with the output terminal r10 that is the 9th register D30; The 13 with the door A40 an input end be connected with the positive node f00 of the first bistable circuit S0, another input end is connected with the output terminal r20 of the 13 register D40;

Second zone bit is made up of with door A41, the second nmos pass transistor N11, the 6th nmos pass transistor N21 and the tenth nmos pass transistor N31 with door A31, the 14 the second bistable circuit S1, the tenth; The drain terminal of the second nmos pass transistor N11 is connected with the antinodal points f11 of the second bistable circuit S1, and the grid end of the second nmos pass transistor N11 is connected with the output terminal of door A31 with second, and the source end of the second nmos pass transistor N11 is connected with ground; The drain terminal of the 6th nmos pass transistor N21 is connected with the positive node f01 of the second bistable circuit S1, and the grid end of the 6th nmos pass transistor N21 is connected with the output terminal of door A41 with the 14, and the source end of the 6th nmos pass transistor N21 is connected with ground; The drain terminal of the tenth nmos pass transistor N31 is connected with the positive node f01 of the second bistable circuit S1, and the output of the grid end Sheffer stroke gate I03 of the tenth nmos pass transistor N31 connects, and the source end of the tenth nmos pass transistor N31 is connected with ground; The tenth with the door A31 an input end be connected with the antinodal points f11 of the second bistable circuit S1, another input end is connected with the output terminal r11 of the tenth register D31; The 14 with the door A41 an input be connected with the positive node f01 of the second bistable circuit S1, another input is connected with the output terminal r21 of the 14 register D41.

The 3rd zone bit is made up of with door A42, the 3rd nmos pass transistor N12, the 7th nmos pass transistor N22 and the 11 nmos pass transistor N32 with door A32, the 15 the 3rd bistable circuit S2, the 11; The drain terminal of the 3rd nmos pass transistor N12 is connected with the antinodal points f12 of the 3rd bistable circuit S2, and the grid end of the 3rd nmos pass transistor N12 is connected with the output terminal of door A32 with the 11, and the source end of the 3rd nmos pass transistor N12 is connected with ground; The drain terminal of the 7th nmos pass transistor N22 is connected with the positive node f02 of the 3rd bistable circuit S2, and the grid end of the 7th nmos pass transistor N22 is connected with the output terminal of door A42 with the 15, and the source end of the 7th nmos pass transistor N22 is connected with ground; The drain terminal of the 11 nmos pass transistor N32 is connected with the positive node f02 of the 3rd bistable circuit S2, and the output of the grid end Sheffer stroke gate I03 of the 11 nmos pass transistor N32 connects, and the source end of the 11 nmos pass transistor N32 is connected with ground; The 11 with the door A32 an input end be connected with the antinodal points f12 of the 3rd bistable circuit S2, another input end is connected with the output terminal r12 of the 11 register D32; The 15 with the door A42 an input end be connected with the positive node f02 of the 3rd bistable circuit S2, another input end is connected with the output terminal r22 of the 15 register D42;

The 4th zone bit is made up of with door A43, the 4th nmos pass transistor N13, the 8th nmos pass transistor N23 and the tenth bi-NMOS transistor N33 with door A33, the 16 the 4th bistable circuit S3, the 12; The drain terminal of the 4th nmos pass transistor N13 is connected with the antinodal points f13 of the 4th bistable circuit S3, and the grid end of the 4th nmos pass transistor N13 is connected with the output terminal of door A33 with the 12, and the source end of the 4th nmos pass transistor N13 is connected with ground; The drain terminal of the 8th nmos pass transistor N23 is connected with the positive node f03 of the 4th bistable circuit S3, and the grid end of the 8th nmos pass transistor N23 is connected with the output terminal of door A43 with the 16, and the source end of the 8th nmos pass transistor N23 is connected with ground; The drain terminal of the tenth bi-NMOS transistor N33 is connected with the positive node f03 of the 4th bistable circuit S3, and the output of the grid end Sheffer stroke gate I03 of the tenth bi-NMOS transistor N33 connects, and the source end of the tenth bi-NMOS transistor N33 is connected with ground; The 12 with the door A33 an input end be connected with the antinodal points f13 of the 4th bistable circuit S3, another input end is connected with the output terminal r13 of the 12 register D33; The 16 with the door A43 an input end be connected with the positive node f03 of the 4th bistable circuit S3, another input end is connected with the output terminal r23 of the 16 register D43.

The utlity model has following advantage:

1. the utility model is owing to adopt the clocked register chain to come the read-write word line of gating SRAM, simultaneously each data of SRAM whether effective marker directly sends the zone bit unit to, avoided complicated code conversion.

2. the utility model makes the value that changes bistable circuit only rely on three NMOS pull-down transistors because the value of zone bit is stored in the bistable circuit, does not have the problem of multi-clock zone, thus avoided the metastable state problem.

The utility model since the value of zone bit only need pass through combinational logic simple in structure just can produce empty, expire, in midair with half-full signal, do not need the subtract logic unit of complicacy, so reduced circuit complexity, improved circuit speed.

4. the utility model does not rely on the address signal of relatively reading and writing clock zone and just can produce the empty full half-full in midair signal that reaches of FIFO owing to adopt the form of zone bit, has avoided that address translation relatively waits a series of complicated problems after becoming Gray code again in the conventional art.

The structure of the utility model can combine accompanying drawing to do further detailed description.

Description of drawings

Fig. 1 is the structural drawing of traditional asynchronous FIFO;

Fig. 2 is the structured flowchart of 8 FIFO storer for the utility model degree of depth;

Fig. 3 is the circuit theory diagrams of 4 FIFO storer for the utility model degree of depth;

Fig. 4 is the timing waveform of writing of the utility model;

Fig. 5 is the timing waveform of reading of the utility model.

Embodiment

With reference to Fig. 2, the utility model mainly by dual-port static random access memory SRAM, write word line control module, readout word line control module, zone bit unit, full and half-full signal generator module, sky and in midair signal generator module form.Wherein:

Described write word line control module at three outside input write clock signal wclk, write under the effect of enable signal wen and reset signal rst_n, with polling mode, 8 of gating SRAM write word line wwl0 successively; Wwl1, wwl2, wwl3; Wwl4, wwl5, wwl6; One of wwl7, when a write word line during by gating, the data on the data of the external input port input data_in are written into this write word line corresponding memory space; The write word line module writes the zone bit unit with the effective marker of this storage space simultaneously; With the data of indicating this storage space is effectively, and the zone bit unit will keep this effective marker always, up to the readout word line control module invalid flag of this storage space is write the zone bit unit.

Described readout word line control module at three outside input read clock signal rclk, read under the effect of enable signal ren and reset signal rst_n, with polling mode, 8 of gating SRAM readout word line rwl0 successively; Rwl1, rwl2, rwl3; Rwl4, rwl5, rwl6; One of rwl7, when a readout word line during by gating, the data of this word line corresponding memory space are read out to the data output data_out of external output port; The readout word line module writes the zone bit unit with the invalid flag of this storage space simultaneously; With the data of indicating this storage space is invalid, and the zone bit unit will keep this invalid flag always, up to the write word line control module effective marker of this storage space is write the zone bit unit.

The zone bit unit is effectively exported to full signal and half-full signal generator module and spacing wave and signal generator module in midair respectively with invalid information with the data of SRAM storage space, and the output signals that produce outsides by these two modules completely signal full, half-full signal half_full, spacing wave empty and signal half_empty in midair.

With reference to Fig. 3, the utility model has provided one and has realized that the degree of depth is the circuit theory diagrams of 4 asynchronous FIFO, its 4 data of multipotency storage.The structure of each module is following:

Dual-port static random access memory SRAM, the storage kernel of employing 4 * 32bits;

The write word line control module comprises the first chain of registers D1 and first group and a door A1; First chain of registers is joined end to end by the first register D10, the second register D11, the 3rd register D12 and the 3rd register D13 and constitutes, and first group constitutes with A13 with door A12 and the 4th with door A11, the 3rd with a door A10, second by first with door A1.The output of the first register D10 is connected to the data input pin of the second register D11; The output of the second register D11 is connected to the data input pin of the 3rd register D12; The output of the 3rd register D12 is connected to the data input pin of the 4th register D13, and the output of the 4th register D13 is connected to the data input pin of the first register D10.In addition, outside input write clock signal wclk writes with outside input after through not gate I00 anti-phase and enables wen signal process and write door controling clock signal wclk_gated with door A00 with generation.Write the input end of clock that door controling clock signal wclk_gated is connected to the first register D10, the second register D11, the 3rd register D12 and the 4th register D13 respectively.Write the data input pin that door controling clock signal wclk_gated is connected to latch L10 after through not gate I01 anti-phase, write the Enable Pin that clock wclk signal is connected to latch L10.The output of latch L10 enables wen signal process and door A01 and generation write word line enable signal wwlen with writing.The output of the write word line enable signal wwlen and the first register D10 through first with door A10 with after output be connected to the write word line wwl0 of SRAM; The output of the write word line enable signal wwlen and the second register D11 through with door A11 with after output be connected to the write word line wwl1 of SRAM; The output of write word line enable signal wwlen and the 3rd register D12 through with door A12 with after output be connected to the write word line wwl2 of SRAM, the output of write word line enable signal wwlen and the 4th register D13 pass through with door A13 with after output be connected to the write word line wwl3 of SRAM.The principle of work of this write word line control module is: the write word line control module is controlled by the outside enable signal wen that writes, and produces 4 write word line signal and controls writing of SRAM.After resetting, the first register D10 is output as " 1 ", and the output of all the other registers all is " 0 ".But this moment, write word line enabled the wwlen signal for " 0 "; So 4 write word lines all are " 0 "; Enable the wen signal effectively and when keeping one to write the clock period when writing; The last clock period write word line of writing for half enables the wwlen signal and is " 1 ", and write word line wwl0 will be changed to high level, and all the other write word lines all are low level; Writing down the clock period write word line for half enables the wwlen signal and is " 0 "; All word lines all are low level, can produce a time clock with door A00 simultaneously, make the value displacement of the chain of registers D1 that wins; So the second register D11 is output as " 1 ", all the other registers all are " 0 ".Enable the effective of wen signal along with writing, 4 write word lines will be changed to high level successively, and circulation, accomplish the function that writes.The write word line control module is provided with two outside inputs, is respectively: write clock wclk and write enable signal wen.SRAM is provided with an external data input data_in.The sequential of these three outside inputs requires as shown in Figure 4, wherein requires the data on the data_in just necessary stable in preceding half clock period.Write door controling clock signal wclk_gated and write word line and enable the internal signal that wwlen is generation under the effect of three outside inputs, the timing waveform relation between its door also provides in Fig. 4.

The readout word line control module comprises the second chain of registers D2 and second group and a door A2.Second chain of registers is joined end to end by the 5th register D20, the 6th register D21, the 7th register D22 and the 8th register D23 and constitutes, second group with the door A2 by the 5th with the door A20, the 6th with the door A21, the 7th with the door A22 and the 8th with the door A23 constitute.The output of the 5th register D20 is connected to the data input pin of the 6th register D21; The output of the 6th register D21 is connected to the data input pin of the 7th register D22; The output of the 7th register D22 is connected to the data input pin of the 8th register D23, and the output of the 8th register D23 is connected to the data input pin of the 5th register D20.In addition, outside input is write clock rclk and is write with outside input after through not gate I02 anti-phase and enable ren signal process and read door controling clock signal rclk_gated with door A02 with generation.Read the input end of clock that door controling clock signal rclk_gated is connected to the 5th register D20, the 6th register D21, the 7th register D22 and the 8th register D23 respectively.The output of reading enable signal ren and the 5th register D20 through the 5th with door A20 with after output be connected to the readout word line rwl0 of SRAM; The output of reading enable signal ren and the 6th register D21 through the 6th with door A21 with after output be connected to the readout word line rwl1 of SRAM; The output of reading enable signal ren and the 7th register D22 through the 7th with door A22 with after output be connected to the readout word line rwl2 of SRAM, the output of reading enable signal ren and the 8th register D23 through the 8th with an A23 with after output be connected to the readout word line rwl3 of SRAM.In addition; The readout word line control module also comprises one group of 32 register D0; The sense data line of SRAM is connected to this 32 register D0, reads the input end of clock that door controling clock signal rclk_gated is connected to these 32 register D0, and the output of these 32 register D0 is outside output data_out.The principle of work of this readout word line control module is: the readout word line control module is controlled by the outside enable signal ren that reads, and produces 4 read word line signal and controls reading of SRAM.After resetting, the 5th register D20 is output as " 1 ", and all the other registers all are " 0 ".But read to enable the ren signal for " 0 " this moment, so 4 readout word lines all be " 0 ", the ren signal is effective and when keeping one to write the clock period when reading to enable, and upward reads clock period readout word line rwl0 half and will be changed to high level, and all the other readout word lines all are low level; Reading down the clock period for half can produce a time clock with a door A02, makes the data of reading in first cycle preserved by one group 32 register D0, and the output of this register D0 of 32 is outside output data_out; The time clock that produces with door A02 also makes the value of chain of registers be shifted; So the 6th register D21 is output as " 1 ", all the other registers all are " 0 ", when reading the clock period half down; Readout word line rwl1 can be changed to high level; All the other readout word lines are low level, but the value of data_out is by register holds, so can not change.Along with reading to enable the effective of ren signal, 4 readout word lines will be changed to high level successively, and circulation, accomplish the function of reading.The readout word line control module is provided with two outside inputs, is respectively: read clock rclk and read enable signal ren.The sequential of these two each and every one outside inputs requires as shown in Figure 5.Reading door controling clock signal rclk_gated is the internal signal that under the effect of two outside inputs, produces, and data_out is outside data-out port, and the timing waveform relation between its door also provides in Fig. 4.

The zone bit unit, comprise the 3rd group of register D3, the 4th group of register D4, the 3rd group and a door A3, the 4th group form with a door A4, first group of nmos pass transistor N1, second group of nmos pass transistor N2, the 3rd group of nmos pass transistor N3 and one group of bistable circuit S.The 3rd group of register D3 is made up of the 9th register D30, the tenth register D31, the 11 register D32 and the 12 register D33.The 4th group of register D4 is made up of the 13 register D40, the 14 register D41, the 15 register D42 and the 16 register D43.The 3rd group with the door A3 by the 9th with the door A30, the tenth with the door A31, the 11 with the door A32 and the 12 with the door A33 form.The 4th group with the door A4 by the 13 with the door A40, the 14 with the door A41, the 15 with the door A42 and the 16 with the door A43 form.First group of nmos pass transistor N1 is made up of the first transistor N10, transistor seconds N11, the 3rd transistor N12 and the 4th transistor N13.Second group of nmos pass transistor N2 is made up of the 5th transistor N20, the 6th transistor N21, the 7th transistor N22 and the 8th transistor N23.The 3rd group of nmos pass transistor N3 is made up of the 9th transistor N30, the tenth transistor N31, the 11 transistor N32 and the tenth two-transistor N33.Bistable circuit S is made up of the first bistable circuit S0, the second bistable circuit S1, the 3rd bistable circuit S2 and the 4th bistable circuit S3.

These circuit components of zone bit unit have been formed four zone bits altogether, are respectively: first zone bit, second zone bit, the 3rd zone bit and the 4th zone bit.Wherein:

First zone bit is made up of with door A40, the first nmos pass transistor N10, the 5th nmos pass transistor N20 and the 9th nmos pass transistor N30 with door A30, the 13 the first bistable circuit S0, the 9th.The drain terminal of the first nmos pass transistor N10 is connected with the antinodal points f10 of the first bistable circuit S0, and the grid end of the first nmos pass transistor N10 is connected with the output terminal of door A30 with the 9th, and the source end of the first nmos pass transistor N10 is connected with ground.The drain terminal of the 5th nmos pass transistor N20 is connected with the positive node f00 of the first bistable circuit S0, and the grid end of the 5th nmos pass transistor N20 is connected with the output terminal of door A40 with the 13, and the source end of the 5th nmos pass transistor N20 is connected with ground.The drain terminal of the 9th nmos pass transistor N30 is connected with the positive node f00 of the first bistable circuit S0, and the output of the grid end Sheffer stroke gate I03 of the 9th nmos pass transistor N30 connects, and the source end of the 9th nmos pass transistor N30 is connected with ground.The 9th with the door A30 an input end be connected with the antinodal points f10 of the first bistable circuit S0, another input end is connected with the output terminal r10 that is the 9th register D30.The 13 with the door A40 an input end be connected with the positive node f00 of the first bistable circuit S0, another input end is connected with the output terminal r20 of the 13 register D40.

Second zone bit is made up of with door A41, the second nmos pass transistor N11, the 6th nmos pass transistor N21 and the tenth nmos pass transistor N31 with door A31, the 14 the second bistable circuit S1, the tenth.The drain terminal of the second nmos pass transistor N11 is connected with the antinodal points f11 of the second bistable circuit S1, and the grid end of the second nmos pass transistor N11 is connected with the output terminal of door A31 with second, and the source end of the second nmos pass transistor N11 is connected with ground.The drain terminal of the 6th nmos pass transistor N21 is connected with the positive node f01 of the second bistable circuit S1, and the grid end of the 6th nmos pass transistor N21 is connected with the output terminal of door A41 with the 14, and the source end of the 6th nmos pass transistor N21 is connected with ground.The drain terminal of the tenth nmos pass transistor N31 is connected with the positive node f01 of the second bistable circuit S1, and the output of the grid end Sheffer stroke gate I03 of the tenth nmos pass transistor N31 connects, and the source end of the tenth nmos pass transistor N31 is connected with ground.The tenth with the door A31 an input end be connected with the antinodal points f11 of the second bistable circuit S1, another input end is connected with the output terminal r11 of the tenth register D31.The 14 with the door A41 an input be connected with the positive node f01 of the second bistable circuit S1, another input is connected with the output terminal r21 of the 14 register D41.

The 3rd zone bit is made up of with door A42, the 3rd nmos pass transistor N12, the 7th nmos pass transistor N22 and the 11 nmos pass transistor N32 with door A32, the 15 the 3rd bistable circuit S2, the 11.The drain terminal of the 3rd nmos pass transistor N12 is connected with the antinodal points f12 of the 3rd bistable circuit S2, and the grid end of the 3rd nmos pass transistor N12 is connected with the output terminal of door A32 with the 11, and the source end of the 3rd nmos pass transistor N12 is connected with ground.The drain terminal of the 7th nmos pass transistor N22 is connected with the positive node f02 of the 3rd bistable circuit S2, and the grid end of the 7th nmos pass transistor N22 is connected with the output terminal of door A42 with the 15, and the source end of the 7th nmos pass transistor N22 is connected with ground.The drain terminal of the 11 nmos pass transistor N32 is connected with the positive node f02 of the 3rd bistable circuit S2, and the output of the grid end Sheffer stroke gate I03 of the 11 nmos pass transistor N32 connects, and the source end of the 11 nmos pass transistor N32 is connected with ground.The 11 with the door A32 an input end be connected with the antinodal points f12 of the 3rd bistable circuit S2, another input end is connected with the output terminal r12 of the 11 register D32.The 15 with the door A42 an input end be connected with the positive node f02 of the 3rd bistable circuit S2, another input end is connected with the output terminal r22 of the 15 register D42.

The 4th zone bit is made up of with door A43, the 4th nmos pass transistor N13, the 8th nmos pass transistor N23 and the tenth bi-NMOS transistor N33 with door A33, the 16 the 4th bistable circuit S3, the 12.The drain terminal of the 4th nmos pass transistor N13 is connected with the antinodal points f13 of the 4th bistable circuit S3, and the grid end of the 4th nmos pass transistor N13 is connected with the output terminal of door A33 with the 12, and the source end of the 4th nmos pass transistor N13 is connected with ground.The drain terminal of the 8th nmos pass transistor N23 is connected with the positive node f03 of the 4th bistable circuit S3, and the grid end of the 8th nmos pass transistor N23 is connected with the output terminal of door A43 with the 16, and the source end of the 8th nmos pass transistor N23 is connected with ground.The drain terminal of the tenth bi-NMOS transistor N33 is connected with the positive node f03 of the 4th bistable circuit S3, and the output of the grid end Sheffer stroke gate I03 of the tenth bi-NMOS transistor N33 connects, and the source end of the tenth bi-NMOS transistor N33 is connected with ground.The 12 with the door A33 an input end be connected with the antinodal points f13 of the 4th bistable circuit S3, another input end is connected with the output terminal r13 of the 12 register D33.The 16 with the door A43 an input end be connected with the positive node f03 of the 4th bistable circuit S3, another input end is connected with the output terminal r23 of the 16 register D43.

The principle of work of zone bit unit is: the storage space of four zone bits in the zone bit unit and four 32bits of SRAM is corresponding one by one, and whether the value of first storage space of first zone bit indication SRAM is effective; Whether the value of second storage space of second zone bit indication SRAM is effective; Whether the value of first storage space of the 3rd zone bit indication SRAM is effective; Whether the value of the 4th storage space of the 4th zone bit indication SRAM is effective.The principle of work of these four zone bits is identical, and their principle of work is described with first zone bit below: when resetting, the 9th nmos pass transistor N30 manages conducting, and the value of the output node f00 of first zone bit is " 0 ".After resetting, the first nmos pass transistor N10, the 5th nmos pass transistor N20, the 9th nmos pass transistor N30 pipe is all closed, and the value of the output node f00 of first zone bit still is " 0 ".After first storage space to SRAM write data, the 9th register D30 was output as " 1 ", cause the 9th with the door A30 be output as " 1 "; So the first nmos pass transistor N10 manages conducting, make the value of the output node f00 of first zone bit be " 1 ", the value of the node f10 of first zone bit is " 0 " simultaneously; So the 9th with the output of door A30 be " 0 " at once, thereby closed the first nmos pass transistor N10, the first nmos pass transistor N10 at this moment; The 5th nmos pass transistor N20; The 9th nmos pass transistor N30 pipe is all closed, and the value of the output node f00 of first zone bit is " 1 " still, shows that the first storage space data of SRAM are effective.After the first storage space sense data to SRAM, the 13 register D40 is output as " 1 ", cause the 13 with the door A40 be output as " 1 "; So the 5th transistor N20 manages conducting, make the value of the output node f00 of first zone bit be " 0 ", the value of the node f10 of first zone bit is " 1 " simultaneously; So the 13 with the output of door A40 be " 0 " at once, thereby closed the 5th nmos pass transistor N20 pipe, the first nmos pass transistor N10 at this moment; The 5th nmos pass transistor N20; The 9th nmos pass transistor N30 pipe is all closed, and the value of the output node f00 of first zone bit is " 0 " still, shows that the first storage space data of SRAM are invalid.

Full, half-full signal generator module, comprise the 5th group with a door A5, the 6th group and door A6 and first group or door O1.The 5th group with the door A5 by the 17 with the door A50, the 18 with the door A51, the 19 with the door A52 and the 20 with the door A53 form.The 6th group with the door A6 by the 21 with the door A60 form.First or the door O1 by first or the door O10, second or the door O11 and the 3rd or the door O12 form.The 5th group is connected with f0j with the output f0i of zone bit respectively with two inputs of an A5i with the i of door in (A5), and when 0≤i≤n/2, j=i+n/2-1; When n/2＜i≤n-1, j=i-n/2-1; The number of the maximum storage data of n=SRAM, concrete annexation is: the 17 is connected with the output node f00 of first zone bit with the input end of an A50, and another input end is connected with the output node f01 of second zone bit; The 18 with the door A51 an input be connected with the output node f01 of second zone bit, another input end is connected with the output node f02 of the 3rd zone bit; The 19 with the door A52 an input end be connected with the output node f02 of the 3rd zone bit, another input end is connected with the output node f03 of the 4th zone bit; The 20 with the door A53 an input end be connected with the output node f03 of the 4th zone bit, another input end is connected with the output node f00 of first zone bit.The 21 is connected with the output terminal of an A50 with the 17 with input end of door A60, and another input end is connected with the output terminal of an A52 with the 19.First or input end of door O10 be connected with the output terminal of an A50 with the 17, another input end is connected with the output terminal of an A51 with the 18.Second or input end of door O11 be connected with the output terminal of an A52 with the 19, another input end is connected with the output of an A53 with the 20.The 3rd or input end of door O12 be connected with first or the output terminal of door O10, another input end is connected with second or the output terminal of an O11.The 21 with the output terminal of door A60 be exactly the full signal full of outside output, the 3rd or the output terminal of door O12 be exactly that half-full signal half_full is exported in the outside.

Empty, signal generator module in midair comprise second group or door O2, the 3rd group or door O3 and the 7th group and a door A7.Second group or Men Youdi four or door O20, the 5th or door O21, the 6th or door O22 and the 7th or door O23 form.The 3rd group or the door O3 by the 8th or the door O30 form.The 7th group with the door A7 by the 22 with the door A70, the 23 with the door A71 and the 24 with the door A72 form.Second group or the i of door (O2) or two inputs of door (O2i) are connected with f0j with the output f0i of zone bit respectively, and when 0≤i≤n/2, j=i+n/2-1; When n/2＜i≤n-1, j=i-n/2-1; The number of the maximum storage data of n=SRAM, concrete annexation is: the 4th or the input end of door O20 be connected with the output node f00 of first zone bit, another input end is connected with the output node f01 of second zone bit; The 5th or the door O21 an input end be connected with the output node f01 of second zone bit, another input end is connected with the output node f02 of the 3rd zone bit; The 6th or the door O22 an input end be connected with the output node f02 of the 3rd zone bit, another input end is connected with the output node f03 of the 4th zone bit; The 7th or the door O23 an input end be connected with the output node f03 of the 4th zone bit, another input end is connected with the output node f00 of first zone bit.The 8th or input end of door O30 be connected with first or the output terminal of door O20, another input end is connected with the 6th or the output terminal of an O22.The 22 is connected with the 4th or the output terminal of door O20 with input end of door A70, and another input end is connected with the 5th or the output terminal of an O21.The 23 is connected with the 6th or the output terminal of door O22 with input end of door A71, and another input end is connected with the 7th or the output terminal of an O23.The 24 is connected with the output terminal of an A70 with the 22 with input end of door A72, and another input end is connected with the output terminal of an A71 with the 23.The 24 is connected with the input end of output terminal Sheffer stroke gate I04 of door A72.The 8th or the output terminal of door O30 be exactly the outside spacing wave empty that exports, the output terminal of not gate I04 is exactly that signal half_empty is in midair exported in the outside.

Full, half-full signal generator module and sky, the principle of work of signal generator module is that value according to output f00, f01, f02 and the f03 of said four zone bits produces full signal full, half-full signal half_full, spacing wave empty and signal half_empty in midair in midair.Full signal full, half-full signal half_full, spacing wave empty and in midair signal half_empty to produce logical expression following.

full＝f00·f01·f02·f03

$\mathrm{empty}=\stackrel{\‾}{f00+f01+f02+f03}$

half_full＝(f00·f01)+(f01·f02)+(f02·f03)+(f03·f00)

$\mathrm{half}\_\mathrm{empty}=\stackrel{\‾}{(f00+f01)\·(f01+f02)\·(f02+f03)\·(f03+f00)}$

It is 4 clock controlled asynchronous FIFO memory that the embodiment of the utility model is not limited to the above-described degree of depth; Can make the FIFO storer of different depth according to actual needs; For example the degree of depth is that 8 or 16 circuit theory is identical with the described principle of Fig. 3; Only be the length that has increased by first chain of registers and second chain of registers, and the number that has increased zone bit in the zone bit unit.Obviously, anyone can do different circuits and change after the know-why of having understood the utility model, but these changes all belong within the protection domain of the utility model.

Claims (5)

1. clock controlled asynchronous FIFO FIFO storer; It is characterized in that: comprising: the write word line control module of double-port random static memory SRAM, SRAM, the readout word line control module of SRAM, tag unit; The write word line control module of SRAM divides two-way; One we be electrically connected with the line traffic control end that writes of double-port random static memory SRAM, another road is electrically connected with the tag unit input end; The Gray code conversion unit of reading of SRAM divides two-way, and one the tunnel is electrically connected with the readout word line control end of double-port random static memory SRAM, and another input end of another road and tag unit is electrically connected; Tag unit is electrically connected with the living logical block input end of producing at full capacity respectively, and another road is electrically connected with the empty logical block input end that produces.

2. a kind of clock controlled asynchronous FIFO FIFO storer according to claim 1 is characterized in that; Described write word line control module comprises the first chain of registers D1 and first group and a door A1; First chain of registers is joined end to end by the first register D10, the second register D11, the 3rd register D12 and the 3rd register D13 and constitutes, and first group constitutes with A13 with door A12 and the 4th with door A11, the 3rd with a door A10, second by first with door A1; The output of the first register D10 is connected to the data input pin of the second register D11; The output of the second register D11 is connected to the data input pin of the 3rd register D12; The output of the 3rd register D12 is connected to the data input pin of the 4th register D13, and the output of the 4th register D13 is connected to the data input pin of the first register D10; Outside input write clock signal wclk writes with outside input after through not gate I00 anti-phase and enables wen signal process and write door controling clock signal wclk_gated with door A00 with generation; Write the input end of clock that door controling clock signal wclk_gated is connected to the first register D10, the second register D11, the 3rd register D12 and the 4th register D13 respectively; Write the data input pin that door controling clock signal wclk_gated is connected to latch L10 after through not gate I01 anti-phase, write the Enable Pin that clock wclk signal is connected to latch L10; The output of latch L10 enables wen signal process and door A01 and generation write word line enable signal wwlen with writing; The output of the write word line enable signal wwlen and the first register D10 through first with door A10 with after output be connected to the write word line wwl0 of SRAM; The output of the write word line enable signal wwlen and the second register D11 through with door A11 with after output be connected to the write word line wwl1 of SRAM; The output of write word line enable signal wwlen and the 3rd register D12 through with door A12 with after output be connected to the write word line wwl2 of SRAM, the output of write word line enable signal wwlen and the 4th register D13 pass through with door A13 with after output be connected to the write word line wwl3 of SRAM.

3. a kind of clock controlled asynchronous FIFO FIFO storer according to claim 1 is characterized in that: described readout word line control module comprises the second chain of registers D2 and second group and a door A2; Second chain of registers is joined end to end by the 5th register D20, the 6th register D21, the 7th register D22 and the 8th register D23 and constitutes, second group with the door A2 by the 5th with the door A20, the 6th with the door A21, the 7th with the door A22 and the 8th with the door A23 constitute; The output of the 5th register D20 is connected to the data input pin of the 6th register D21; The output of the 6th register D21 is connected to the data input pin of the 7th register D22; The output of the 7th register D22 is connected to the data input pin of the 8th register D23, and the output of the 8th register D23 is connected to the data input pin of the 5th register D20; Outside input is write clock rclk and is write with outside input after through not gate I02 anti-phase and enable ren signal process and read door controling clock signal rclk_gated with door A02 with generation.Read the input end of clock that door controling clock signal rclk_gated is connected to the 5th register D20, the 6th register D21, the 7th register D22 and the 8th register D23 respectively; The output of reading enable signal ren and the 5th register D20 through the 5th with door A20 with after output be connected to the readout word line rwl0 of SRAM; The output of reading enable signal ren and the 6th register D21 through the 6th with door A21 with after output be connected to the readout word line rwl1 of SRAM; The output of reading enable signal ren and the 7th register D22 through the 7th with door A22 with after output be connected to the readout word line rwl2 of SRAM, the output of reading enable signal ren and the 8th register D23 through the 8th with an A23 with after output be connected to the readout word line rwl3 of SRAM.

4. a kind of clock controlled asynchronous FIFO FIFO storer according to claim 1; It is characterized in that: the readout word line control module also comprises one group of 32 register D0; The sense data line of SRAM is connected to this 32 register D0; Read the input end of clock that door controling clock signal rclk_gated is connected to these 32 register D0, the output of these 32 register D0 is outside output data_out.

5. a kind of clock controlled asynchronous FIFO FIFO storer according to claim 1, it is characterized in that: described zone bit unit comprises four zone bits, first zone bit, second zone bit, the 3rd zone bit and the 4th zone bit; Wherein:

First zone bit is made up of with door A40, the first nmos pass transistor N10, the 5th nmos pass transistor N20 and the 9th nmos pass transistor N30 with door A30, the 13 the first bistable circuit S0, the 9th; The drain terminal of the first nmos pass transistor N10 is connected with the antinodal points f10 of the first bistable circuit S0, and the grid end of the first nmos pass transistor N10 is connected with the output terminal of door A30 with the 9th, and the source end of the first nmos pass transistor N10 is connected with ground; The drain terminal of the 5th nmos pass transistor N20 is connected with the positive node f00 of the first bistable circuit S0, and the grid end of the 5th nmos pass transistor N20 is connected with the output terminal of door A40 with the 13, and the source end of the 5th nmos pass transistor N20 is connected with ground; The drain terminal of the 9th nmos pass transistor N30 is connected with the positive node f00 of the first bistable circuit S0, and the output of the grid end Sheffer stroke gate I03 of the 9th nmos pass transistor N30 connects, and the source end of the 9th nmos pass transistor N30 is connected with ground; The 9th with the door A30 an input end be connected with the antinodal points f10 of the first bistable circuit S0, another input end is connected with the output terminal r10 that is the 9th register D30; The 13 with the door A40 an input end be connected with the positive node f00 of the first bistable circuit S0, another input end is connected with the output terminal r20 of the 13 register D40;

Second zone bit is made up of with door A41, the second nmos pass transistor N11, the 6th nmos pass transistor N21 and the tenth nmos pass transistor N31 with door A31, the 14 the second bistable circuit S1, the tenth; The drain terminal of the second nmos pass transistor N11 is connected with the antinodal points f11 of the second bistable circuit S1, and the grid end of the second nmos pass transistor N11 is connected with the output terminal of door A31 with second, and the source end of the second nmos pass transistor N11 is connected with ground; The drain terminal of the 6th nmos pass transistor N21 is connected with the positive node f01 of the second bistable circuit S1, and the grid end of the 6th nmos pass transistor N21 is connected with the output terminal of door A41 with the 14, and the source end of the 6th nmos pass transistor N21 is connected with ground; The drain terminal of the tenth nmos pass transistor N31 is connected with the positive node f01 of the second bistable circuit S1, and the output of the grid end Sheffer stroke gate I03 of the tenth nmos pass transistor N31 connects, and the source end of the tenth nmos pass transistor N31 is connected with ground; The tenth with the door A31 an input end be connected with the antinodal points f11 of the second bistable circuit S1, another input end is connected with the output terminal r11 of the tenth register D31; The 14 with the door A41 an input be connected with the positive node f01 of the second bistable circuit S1, another input is connected with the output terminal r21 of the 14 register D41.

The 3rd zone bit is made up of with door A42, the 3rd nmos pass transistor N12, the 7th nmos pass transistor N22 and the 11 nmos pass transistor N32 with door A32, the 15 the 3rd bistable circuit S2, the 11; The drain terminal of the 3rd nmos pass transistor N12 is connected with the antinodal points f12 of the 3rd bistable circuit S2, and the grid end of the 3rd nmos pass transistor N12 is connected with the output terminal of door A32 with the 11, and the source end of the 3rd nmos pass transistor N12 is connected with ground; The drain terminal of the 7th nmos pass transistor N22 is connected with the positive node f02 of the 3rd bistable circuit S2, and the grid end of the 7th nmos pass transistor N22 is connected with the output terminal of door A42 with the 15, and the source end of the 7th nmos pass transistor N22 is connected with ground; The drain terminal of the 11 nmos pass transistor N32 is connected with the positive node f02 of the 3rd bistable circuit S2, and the output of the grid end Sheffer stroke gate I03 of the 11 nmos pass transistor N32 connects, and the source end of the 11 nmos pass transistor N32 is connected with ground; The 11 with the door A32 an input end be connected with the antinodal points f12 of the 3rd bistable circuit S2, another input end is connected with the output terminal r12 of the 11 register D32; The 15 with the door A42 an input end be connected with the positive node f02 of the 3rd bistable circuit S2, another input end is connected with the output terminal r22 of the 15 register D42;

The 4th zone bit is made up of with door A43, the 4th nmos pass transistor N13, the 8th nmos pass transistor N23 and the tenth bi-NMOS transistor N33 with door A33, the 16 the 4th bistable circuit S3, the 12; The drain terminal of the 4th nmos pass transistor N13 is connected with the antinodal points f13 of the 4th bistable circuit S3, and the grid end of the 4th nmos pass transistor N13 is connected with the output terminal of door A33 with the 12, and the source end of the 4th nmos pass transistor N13 is connected with ground; The drain terminal of the 8th nmos pass transistor N23 is connected with the positive node f03 of the 4th bistable circuit S3, and the grid end of the 8th nmos pass transistor N23 is connected with the output terminal of door A43 with the 16, and the source end of the 8th nmos pass transistor N23 is connected with ground; The drain terminal of the tenth bi-NMOS transistor N33 is connected with the positive node f03 of the 4th bistable circuit S3, and the output of the grid end Sheffer stroke gate I03 of the tenth bi-NMOS transistor N33 connects, and the source end of the tenth bi-NMOS transistor N33 is connected with ground; The 12 with the door A33 an input end be connected with the antinodal points f13 of the 4th bistable circuit S3, another input end is connected with the output terminal r13 of the 12 register D33; The 16 with the door A43 an input end be connected with the positive node f03 of the 4th bistable circuit S3, another input end is connected with the output terminal r23 of the 16 register D43.

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