CN202331840U - Learning machine circuit - Google Patents

Abstract

The utility model discloses a learning machine circuit, which comprises a main control circuit, a voltage stabilization starting circuit, a charging circuit, a storing circuit, an audio frequency circuit, a touch screen control screen, a display control circuit and a camera circuit, which are connected to the main control circuit. The learning machine circuit of the utility model has the advantages of effectively improving the information processing capability of the main control circuit of the learning machine, expanding the functions of a plurality of interfaces on a microprocessor, effectively solving the problem of weak data storage capability of the learning machine, improving the performance of the learning machine, enhancing the safety of the learning machine, and prolonging the service life thereof.

Description

A kind of learning machine circuit

Technical field

The utility model relates to the learning machine circuit field, is specially a kind of learning machine circuit.

Background technology

Learning machine is a kind of electronic instruction series products, is widely used in the student group at home.Learning machine is generally by governor circuit and other peripheral circuit, like formations such as display circuit, memory circuits.There is function singleness in the prior art learning machine, storage and data-handling capacity a little less than, can't carry out the problem that functional module is expanded.

The utility model content

The utility model purpose provides a kind of learning machine circuit, to solve prior art learning machine function singleness, storage and the more weak problem of data-handling capacity.

In order to achieve the above object, the technical scheme that the utility model adopted is:

A kind of learning machine circuit is characterized in that: include governor circuit, voltage stabilizing boot-strap circuit, charging circuit, memory circuit, voicefrequency circuit, touch screen control circuit, display control circuit, camera circuit;

Said governor circuit comprises that model is the microprocessor MPU of LQFP144; The PWMUSB_BOOT/GPIO4_WD pin of said microprocessor MPU connects power supply through resistance R 68, the pushbutton switch SW16 of mutual series connection; VCM pin, the BANDGAP pin of microprocessor MPU connect power supply ground through electric capacity parallel with one another respectively; The R100K_TS pin of microprocessor MPU connects power supply ground through the RC filtering circuit; Be connected with mutual resistance R of connecting 24 and capacitor C 36 between the RREF pin of microprocessor MPU and the VDD pin; Also lead to lead ground connection between resistance R 24, the capacitor C 36 between RREF pin and the VDD pin; The SPVDD2 pin of microprocessor MPU, VDD3/DC_V18_O pin are respectively through capacitor C parallel with one another 54, C60 ground connection; The DC_SW18 pin of microprocessor MPU inserts capacitor C 54 parallel with one another on the VDD3/DC_V18_O pin, the parallel connected end of C60 through diode in series D4, inductance L 1, is connected to the master routine crystal oscillating circuit between the XTAL12MO pin of microprocessor MPU, the XTAL12MI pin, is connected to the RTC crystal oscillating circuit between the XTAL32KO pin of microprocessor MPU, the XTAL32KI pin;

Said voltage stabilizing boot-strap circuit comprises boot-strap circuit, mu balanced circuit; Said boot-strap circuit comprises triode Q4, FET Q2, FET Q5, diode BAT54C; The grid of said FET Q5 connects power supply ground through resistance R 146; Drain electrode inserts said mu balanced circuit, also is connected to diode D6 between the grid of FET Q5, the drain electrode, and source electrode is through capacitor C 63 ground connection; The grid of said FET Q2 is connected with the collector of triode Q4; The source electrode of the drain electrode of FET Q2 and FET Q5 connects the SPVDD1 pin that microprocessor MPU is inserted in the back altogether; The source electrode of FET Q2 inserts the VBAT pin of microprocessor MPU, also is connected to resistance R 49 between the grid of FET Q2 and the source electrode; The grounded emitter of said triode Q4, base stage are divided into two-way after being connected to resistance R 57, are connected to the GPIO1_W pin that microprocessor MPU is inserted in resistance R 15 backs on the way, and another road is through resistance R 29 ground connection; Said diode BAT54C the 3rd pin inserts the resistance R 57 on the triode Q4 base stage; Diode BAT54C first pin inserts the VBAT pin of microprocessor MPU through pushbutton switch SW3; Be divided into two-way after also being connected to resistance R 56 on diode BAT54C first pin; One the road inserts the GPIO0_W pin of microprocessor MPU, and another road is divided into two-way through resistance R 52 ground connection after diode BAT54C second pin is connected to resistance R 53; One the road inserts the WAKEUP pin of microprocessor MPU, and another road is through capacitor C 25 ground connection; Said mu balanced circuit comprises two voltage stabilizing chip U3, U6; The VSS pin of voltage stabilizing chip U3 and U6 is ground connection respectively, and the VOUT pin of voltage stabilizing chip U3 is through capacitor C 78 ground connection, and the VOUT pin of voltage stabilizing chip U6 is through capacitor C 79 ground connection; The VOUT pin of voltage stabilizing chip U3 and U6 also inserts the SPVDD2 pin of microprocessor MPU respectively; The VIN pin of said voltage stabilizing chip U3 and U6 is divided into two-way respectively, and the VIN pin of voltage stabilizing chip U3 is leaded up to capacitor C 80 ground connection, and another road is connected with the drain electrode of FET Q5 in the boot-strap circuit; The VIN pin of voltage stabilizing chip U6 is leaded up to capacitor C 30 ground connection, and another road is connected with the drain electrode of FET Q5 in the boot-strap circuit;

Said charging circuit comprises electric power management circuit, usb circuit, Connection Block; Said electric power management circuit comprises that model is the charging chip U11 of LC4054; Be connected to resistance R 60 between the CHRG pin of charging chip U11 and the BAT pin, the GND pin ground connection of charging chip U11, the PROG pin is through resistance R 8 ground connection; Also have two on the BAT pin of charging chip U11 and draw lead; Draw the VBAT pin that lead connects microprocessor MPU for one on the BAT pin, another root is drawn lead through capacitor C 26 ground connection on the BAT pin, has two to draw lead on the VCC pin of said charging chip U11; On the VCC pin one draw lead through on the diode D2 that draws connect+the 5V power supply, another root is drawn lead through capacitor C 72 ground connection on the VCC pin; Said usb circuit comprises the USB interface chip; The NC1-NC4 pin of said USB interface chip connects back ground connection altogether; Be connected to four pass on the VBUS pin of USB interface chip and go out lead; A pass goes out lead through capacitor C parallel with one another 24, C29 ground connection on the VBUS pin, goes up another pass on the VBUS pin and goes out to be connected to diode D1 on the lead, and Third Road is drawn lead and connect+the 5V power supply on the VBUS pin; The 4th pass is divided into two-way after going out to be connected on the lead resistance R 11 again on the VBUS pin; The resistance R 36 of leading up on the resistance R 11 inserts the MPU_AD12/GPIO26_WU pin of microprocessor MPU, and another road is through resistance R 35 ground connection on the resistance R 11, and DP pin, the DM pin of the DP pin of said USB interface chip, DM pin and microprocessor MPU connect one to one; The ID pin of USB interface chip is vacant; GND pin ground connection also is connected to static impedance device ESD9 between the VBUS pin of said USB interface chip and the GND pin, also be connected to mutual static impedance device ESD7, the ESD8 that connects between DM pin and the DP pin; Said Connection Block comprises the web member CON2 of bipod; Socket power supply ground on the GND pin of said web member CON2; There is two-way to draw lead on the VBAT pin of web member CON2; A pass goes out the VBAT pin that lead connects microprocessor MPU on the VBAT pin, and another pass goes out lead and connects power supply ground through electric capacity TC3 on the VBAT pin;

Said memory circuit comprises main memory circuit, flash memory circuit, SD interface circuit; Said main memory circuit comprises that model is the memory chip U5 of K4S281632F; The A0-A12 pin of said memory chip U5 and the MADDR0-MADDR12 pin of microprocessor MPU connect one to one; MBA0, the MBA1 pin of BA0, BA1 pin and microprocessor MPU connect one to one; MCAS, the MRAS pin of CAS, RAS pin and microprocessor MPU connect one to one; The MDATA0-MDATA15 pin of the DQ0-DQ15 pin memory chip U5 of memory chip U5 connects one to one, and the CS pin of memory chip U5 is connected with the MCS pin of microprocessor MPU, and the WE pin is connected with the MWR pin of microprocessor MPU; MBE1 pin, the MBE0 pin of the UDQM of memory chip U5, LDQM pin and microprocessor MPU connect one to one; MCLK, the MCKE pin of CLK, CKE pin and microprocessor MPU connect one to one, and are connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively after the VDDQ1-VDDQ4 pin of memory chip U5 connects altogether again, and the VSSQ1-VSSQ4 pin connects back ground connection altogether; And be connected to capacitor C parallel with one another 38, C40 between the VDDQ1 pin of memory chip U5 and the VSSQ4 pin; Be connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively again after the VDD1-VDD3 pin of memory chip U5 connects altogether, connect power supply ground after the VSS1-VSS3 pin connects altogether, and be connected to capacitor C parallel with one another 9, C35 between the VSS1 pin of memory chip U5 and the VDD3 pin; Said flash memory circuit comprises flash chip U9; The RE pin of said flash chip U9 is connected with the MCMD pin of microprocessor MPU; The CE pin is connected with the NFC_CE0 pin of microprocessor MPU; The DNU pin is connected with the NFC_CE1 pin of microprocessor MPU; The CLE pin is connected with the NFC_CLE pin of microprocessor MPU; The ALE pin is connected with the NFC_ALE pin of microprocessor MPU, and the WE pin is connected with the NFC_WE pin of microprocessor MPU, and WP pin, VCC1 pin, VCC2 pin are connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively separately; The IO0-IO7 pin of flash chip U9 and the NFC_DATA0-NFC_DATA7 pin of microprocessor MPU connect one to one, and the NC5 pin of said memory chip U9 is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively through resistance R 17, R26 through resistance R 23, DNU pin through resistance R 12, CE pin through resistance R 13, R/NB pin; Said SD interface circuit comprises SD interface chip SD1; The VSS pin of said SD interface chip SD1, GROUND pin be ground connection respectively; The DAT0-DAT3 pin of SD interface chip SD1 and the NFC_DATA0-NFC_DATA3 pin of microprocessor MPU connect one to one; The CARD pin of SD interface chip SD1 is connected with the MPU_AD14 pin of microprocessor MPU; The CMD pin is connected with the MCMD pin of microprocessor MPU; The CLK pin is connected with the MCK pin of microprocessor MPU; The CARD pin of SD interface chip SD1 connects with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively through resistance R 55 through resistance R 3, DAT1 pin through resistance R 51, DAT0 pin through resistance R 50, CLK pin through resistance R 14, CMD pin through resistance R 48, DAT3 pin through resistance R 16, DAT2 pin, and the resistance R 55 of the resistance R 3 of the resistance R 51 of the resistance R 50 of the resistance R 14 of the resistance R 48 of the resistance R 16 of the CARD pin of SD interface chip SD1, DAT2 pin, DAT3 pin, CMD pin, CLK pin, DAT0 pin, DAT1 pin also inserts ground connection after the capacitor C 28 altogether;

Said voicefrequency circuit comprises recording circuit, power amplifier, head circuit; Said recording circuit comprises loudspeaker X1; First pin of said loudspeaker X1 connects the MIC_IN pin of microprocessor MPU through electric capacity TC7; The second pin ground connection of loudspeaker X1, said loudspeaker first pin are also inserted the VDD33 pin of microprocessor MPU through pull-up resistor R34, micropkonic second pin also inserts the VDD33 pin of microprocessor MPU through capacitor C 51; Said power amplifier comprises loudspeaker LS2; The terminals of said loudspeaker LS2 insert the SPKMINUS pin of microprocessor MPU; Another terminals insert the SPKPLUS pin of microprocessor MPU through electric capacity TC6; The terminals that said loudspeaker LS2 inserts the SPKMINUS pin of microprocessor MPU also pass through static impedance device ESD2 ground connection, and the terminals that loudspeaker LS2 inserts the SPKPLUS pin of microprocessor MPU also pass through static impedance device ESD1 ground connection; Said head circuit comprises that model is the earphone chip J2 of ST-017ASMT-040-100; Said earphone chip J2 has four pins; First pin ground connection of its headphone chip J2; Second pin of earphone chip J2 is through the inductance L 3 of series connection each other, the HPL pin that capacitor C 43 inserts microprocessor MPU; The 3rd pin of earphone chip J2 is divided into three the tunnel through the inductance L 2 of series connection each other, the HPR pin that capacitor C 42 inserts microprocessor MPU after the 4th pin of earphone chip J2 is connected to inductance FB1, and the resistance R 28 of leading up to inserts the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; Another road is through capacitor C 41 ground connection, and Third Road inserts the MPU_AD15 pin of microprocessor MPU through resistance R 27;

Said touch screen control circuit comprises touch control chip U8; Said touch control chip U8 model is ZT2083, and the SCL pin that touches control chip U8 inserts the GPIO10 pin of microprocessor MPU, and the SDA pin inserts the GPIO9 pin of microprocessor MPU; CAD1 pin, GND pin be ground connection respectively; The PENIRON pin inserts the SPI_CS pin of microprocessor MPU, has two-way to draw lead on the VCC pin of said touch control chip U8, and VCC pin one pass goes out lead through capacitor C 21 ground connection; Another pass of VCC pin goes out the VDDIO1-VDDIO3 pin that lead inserts microprocessor MPU respectively; The XP pin that touches control chip U8 passes through the AD0 pin that resistance R 65 inserts microprocessor MPUs, and the XP pin touches the AD2 pin of the YP pin of control chip U8 through resistance R 66 access microprocessor MPUs also through capacitor C 56 ground connection; And the YP pin is also through capacitor C 57 ground connection; The XN pin that touches control chip U8 passes through the AD1 pin that resistance R 63 inserts microprocessor MPUs, and the XN pin touches the AD3 pin of the YN pin of control chip U8 through resistance R 64 access microprocessor MPUs also through capacitor C 58 ground connection; And the YN pin also has the control output lead to draw respectively through electric capacity 59 ground connection on the XP pin of said touch control chip U8, YP pin, XN pin, the YN pin;

Said display control circuit comprises TFTLCD display control chip, the triode Q3 that is electrically connected with the TFTLCD display control chip; Said TFTLCD display control chip model is QD028007A0-37; The DB0-DB7 pin of TFTLCD display control chip, GND pin be ground connection respectively; The VCC1 pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; The CS pin of TFTLCD display control chip inserts the MPU_CS pin of microprocessor MPU; The RS pin inserts the MPU_A0 pin of microprocessor MPU, and the WR pin inserts the MPU_WR pin of microprocessor MPU, and the RD pin inserts the MPU_RD pin of microprocessor MPU; The X+ of TFTLCD display control chip, Y+, X-, Y-pin are corresponding to respectively static impedance device ESD3, ESD4, ESD5, ESD6 ground connection; Also be connected to the control signal incoming line on X+, Y+, X-, the Y-pin respectively, the LEDA pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively, and the LEDK1-LEDK4 pin of TFTLCD display control chip connects the collector that triode Q3 is inserted in the back altogether; The DB10-DB17 pin of TFTLCD display control chip connects one to one with the MPU_AD0-MPU_AD7 pin of microprocessor MPU respectively; Have two-way to draw lead on the RESET pin of TFTLCD display control chip, a pass goes out lead and is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively through resistance R 74 on the RESET pin, and another pass goes out lead and passes through capacitor C 7 ground connection on the RESET pin; After connecing altogether, the VCI pin of TFTLCD display control chip, VCC2 pin be divided into two line conductors; VCI pin, VCC2 pin connect back one line conductor altogether through capacitor C 39 ground connection, and VCI pin, VCC2 pin connect another line conductor of back altogether and be connected the grounded emitter of said triode Q3 with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; Base stage is connected with the USB_BOOT pin of microprocessor MPU through resistance R 72, also is connected to resistance R 73 between the base stage of triode Q3 and the emitter;

Said camera circuit comprises the camera chip J1 with 26 pins, the triode Q6 that is electrically connected with camera chip J1, and the model of said camera chip J1 is TGB130VS01, and camera chip J1 first pin is vacant; The second pin ground connection, the 3rd pin inserts the GPIO9 pin of microprocessor MPU, is divided into two-way after the 4th pin of camera chip J1 is connected to resistance R 25; Lead up to capacitor C 14 ground connection, the LDO_V33A_O pin of microprocessor MPU is inserted on another road, and the 5th pin of camera chip J1 inserts the GPIO10 pin of microprocessor MPU; The 6th pin, the 8th pin insert respectively in the camera, and the 7th pin of camera chip J1 is divided into two-way, and the 7th pin is leaded up to resistance R 43 and inserted triode Q6 collectors; Triode Q6 base stage is inserted through resistance R 44 in another road, and the 9th pin of camera chip J1 inserts the VIHREF pin of microprocessor MPU, and the tenth pin of camera chip J1 is divided into two-way; The tenth pin is leaded up to inductance L 5 and is connect+the 1.8V power supply; Another road is through capacitor C 20 ground connection, and the 11 pin of camera chip J1 is divided into two-way, and the inductance L 6 of leading up to is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; Another road is through capacitor C 22 ground connection; The 12 pin of camera chip J1 connects the GPIO16_WU pin of microprocessor MPU, and the 13 pin connects the GPIO23_WU pin of microprocessor MPU, and the 14 pin connects the GPIO3_WU pin of microprocessor MPU; The 15 pin ground connection of camera chip J1; The 16 pin connects the GPIO17_WU pin of microprocessor MPU, and the 18 pin connects the GPIO18_WD pin of microprocessor MPU, and the 19 pin connects the GPIO22_WD pin of microprocessor MPU; The 20 pin connects the GPIO19_WD pin of microprocessor MPU; The 21 pin connects the GPIO21_WD pin of microprocessor MPU, and the 22 pin connects the GPIO20_WD pin of microprocessor MPU, and the 23,24 pins of camera chip J1 are vacant; The 25,26 pins connect back ground connection altogether; The grounded emitter of said triode Q6, collector inserts the GPIO5_WU pin of microprocessor MPU, and the collector of triode Q6 also inserts the LD0_V33A_O pin of microprocessor MPU through resistance R 45.

The utility model can improve the information processing capability of learning machine governor circuit effectively; A plurality of interfaces on the microprocessor can be realized function expansion simultaneously; The utility model has solved the more weak problem of learning machine data storage capacities effectively simultaneously; Improve the performance of learning machine, also improved the security and the serviceable life of learning machine.

Description of drawings

Fig. 1 is the utility model governor circuit schematic diagram.

Fig. 2 is the utility model boot-strap circuit schematic diagram.

Fig. 3 is the utility model mu balanced circuit principle.

Fig. 4 is the utility model electric power management circuit schematic diagram.

Fig. 5 is the utility model usb circuit schematic diagram.

Fig. 6 is the utility model Connection Block circuit theory diagrams.

Fig. 7 is the utility model main memory circuit schematic diagram.

Fig. 8 is the utility model flash memory circuit schematic diagram.

Fig. 9 is the utility model SD interface circuit schematic diagram.

Figure 10 is the utility model recording circuit schematic diagram.

Figure 11 is the utility model power amplifier schematic diagram.

Figure 12 is the utility model head circuit schematic diagram.

Figure 13 is the utility model touch screen control circuit schematic diagram.

Figure 14 is the utility model display control circuit schematic diagram.

Figure 15 is the utility model camera circuit theory diagrams.。

Embodiment

A kind of learning machine circuit includes governor circuit, voltage stabilizing boot-strap circuit, charging circuit, memory circuit, voicefrequency circuit, touch screen control circuit, display control circuit, camera circuit;

As shown in Figure 1.Governor circuit comprises that model is the microprocessor MPU of LQFP144; The PWMUSB_BOOT/GPIO4_WD pin of microprocessor MPU connects power supply through resistance R 68, the pushbutton switch SW16 of mutual series connection; VCM pin, the BANDGAP pin of microprocessor MPU connect power supply ground through electric capacity parallel with one another respectively; The R100K_TS pin of microprocessor MPU connects power supply ground through the RC filtering circuit; Be connected with mutual resistance R of connecting 24 and capacitor C 36 between the RREF pin of microprocessor MPU and the VDD pin; Also lead to lead ground connection between resistance R 24, the capacitor C 36 between RREF pin and the VDD pin; The SPVDD2 pin of microprocessor MPU, VDD3/DC_V18_O pin are respectively through capacitor C parallel with one another 54, C60 ground connection; The DC_SW18 pin of microprocessor MPU inserts capacitor C 54 parallel with one another on the VDD3/DC_V18_O pin, the parallel connected end of C60 through diode in series D4, inductance L 1, is connected to the master routine crystal oscillating circuit between the XTAL12MO pin of microprocessor MPU, the XTAL12MI pin, is connected to the RTC crystal oscillating circuit between the XTAL32KO pin of microprocessor MPU, the XTAL32KI pin;

Like Fig. 2-shown in Figure 3.The voltage stabilizing boot-strap circuit comprises boot-strap circuit, mu balanced circuit; Boot-strap circuit comprises triode Q4, FET Q2, FET Q5, diode BAT54C; The grid of FET Q5 connects power supply ground through resistance R 146; Drain electrode inserts said mu balanced circuit, also is connected to diode D6 between the grid of FET Q5, the drain electrode, and source electrode is through capacitor C 63 ground connection; The grid of FET Q2 is connected with the collector of triode Q4; The source electrode of the drain electrode of FET Q2 and FET Q5 connects the SPVDD1 pin that microprocessor MPU is inserted in the back altogether; The source electrode of FET Q2 inserts the VBAT pin of microprocessor MPU, also is connected to resistance R 49 between the grid of FET Q2 and the source electrode; The grounded emitter of triode Q4, base stage are divided into two-way after being connected to resistance R 57, are connected to the GPIO1_W pin that microprocessor MPU is inserted in resistance R 15 backs on the way, and another road is through resistance R 29 ground connection; Diode BAT54C the 3rd pin inserts the resistance R 57 on the triode Q4 base stage; Diode BAT54C first pin inserts the VBAT pin of microprocessor MPU through pushbutton switch SW3; Be divided into two-way after also being connected to resistance R 56 on diode BAT54C first pin; One the road inserts the GPIO0_W pin of microprocessor MPU, and another road is divided into two-way through resistance R 52 ground connection after diode BAT54C second pin is connected to resistance R 53; One the road inserts the WAKEUP pin of microprocessor MPU, and another road is through capacitor C 25 ground connection; Mu balanced circuit comprises two voltage stabilizing chip U3, U6; The VSS pin of voltage stabilizing chip U3 and U6 is ground connection respectively, and the VOUT pin of voltage stabilizing chip U3 is through capacitor C 78 ground connection, and the VOUT pin of voltage stabilizing chip U6 is through capacitor C 79 ground connection; The VOUT pin of voltage stabilizing chip U3 and U6 also inserts the SPVDD2 pin of microprocessor MPU respectively; The VIN pin of voltage stabilizing chip U3 and U6 is divided into two-way respectively, and the VIN pin of voltage stabilizing chip U3 is leaded up to capacitor C 80 ground connection, and another road is connected with the drain electrode of FET Q5 in the boot-strap circuit; The VIN pin of voltage stabilizing chip U6 is leaded up to capacitor C 30 ground connection, and another road is connected with the drain electrode of FET Q5 in the boot-strap circuit;

Like Fig. 4-shown in Figure 6.Charging circuit comprises electric power management circuit, usb circuit, Connection Block; Electric power management circuit comprises that model is the charging chip U11 of LC4054; Be connected to resistance R 60 between the CHRG pin of charging chip U11 and the BAT pin, the GND pin ground connection of charging chip U11, the PROG pin is through resistance R 8 ground connection; Also have two on the BAT pin of charging chip U11 and draw lead; Draw the VBAT pin that lead connects microprocessor MPU for one on the BAT pin, another root is drawn lead through capacitor C 26 ground connection on the BAT pin, has two to draw lead on the VCC pin of charging chip U11; On the VCC pin one draw lead through on the diode D2 that draws connect+the 5V power supply, another root is drawn lead through capacitor C 72 ground connection on the VCC pin; Usb circuit comprises the USB interface chip; The NC1-NC4 pin of USB interface chip connects back ground connection altogether, is connected to four pass on the VBUS pin of USB interface chip and goes out lead, and a pass goes out lead through capacitor C parallel with one another 24, C29 ground connection on the VBUS pin; Going up another pass on the VBUS pin goes out to be connected to diode D1 on the lead; Third Road is drawn lead and is connect+the 5V power supply on the VBUS pin, and the 4th pass is divided into two-way after going out to be connected on the lead resistance R 11 again on the VBUS pin, and the resistance R 36 of leading up on the resistance R 11 inserts the MPU_AD12/GPIO26_WU pin of microprocessor MPUs; Another road is through resistance R 35 ground connection on the resistance R 11; DP pin, the DM pin of the DP pin of USB interface chip, DM pin and microprocessor MPU connect one to one, and the ID pin of USB interface chip is vacant, GND pin ground connection; Also be connected to static impedance device ESD9 between the VBUS pin of USB interface chip and the GND pin, also be connected to mutual static impedance device ESD7, the ESD8 that connects between DM pin and the DP pin; Connection Block comprises the web member CON2 of bipod; Socket power supply ground on the GND pin of web member CON2; There is two-way to draw lead on the VBAT pin of web member CON2; A pass goes out the VBAT pin that lead connects microprocessor MPU on the VBAT pin, and another pass goes out lead and connects power supply ground through electric capacity TC3 on the VBAT pin;

Like Fig. 7-shown in Figure 9.Memory circuit comprises main memory circuit, flash memory circuit, SD interface circuit; Main memory circuit comprises that model is the memory chip U5 of K4S281632F; The A0-A12 pin of memory chip U5 and the MADDR0-MADDR12 pin of microprocessor MPU connect one to one; MBA0, the MBA1 pin of BA0, BA1 pin and microprocessor MPU connect one to one; MCAS, the MRAS pin of CAS, RAS pin and microprocessor MPU connect one to one; The MDATA0-MDATA15 pin of the DQ0-DQ15 pin memory chip U5 of memory chip U5 connects one to one, and the CS pin of memory chip U5 is connected with the MCS pin of microprocessor MPU, and the WE pin is connected with the MWR pin of microprocessor MPU; MBE1 pin, the MBE0 pin of the UDQM of memory chip U5, LDQM pin and microprocessor MPU connect one to one; MCLK, the MCKE pin of CLK, CKE pin and microprocessor MPU connect one to one, and are connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively after the VDDQ1-VDDQ4 pin of memory chip U5 connects altogether again, and the VSSQ1-VSSQ4 pin connects back ground connection altogether; And be connected to capacitor C parallel with one another 38, C40 between the VDDQ1 pin of memory chip U5 and the VSSQ4 pin; Be connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively again after the VDD1-VDD3 pin of memory chip U5 connects altogether, connect power supply ground after the VSS1-VSS3 pin connects altogether, and be connected to capacitor C parallel with one another 9, C35 between the VSS1 pin of memory chip U5 and the VDD3 pin; Flash memory circuit comprises flash chip U9; The RE pin of flash chip U9 is connected with the MCMD pin of microprocessor MPU; The CE pin is connected with the NFC_CE0 pin of microprocessor MPU; The DNU pin is connected with the NFC_CE1 pin of microprocessor MPU; The CLE pin is connected with the NFC_CLE pin of microprocessor MPU; The ALE pin is connected with the NFC_ALE pin of microprocessor MPU, and the WE pin is connected with the NFC_WE pin of microprocessor MPU, and WP pin, VCC1 pin, VCC2 pin are connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively separately; The IO0-IO7 pin of flash chip U9 and the NFC_DATA0-NFC_DATA7 pin of microprocessor MPU connect one to one, and the NC5 pin of memory chip U9 is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively through resistance R 17, R26 through resistance R 23, DNU pin through resistance R 12, CE pin through resistance R 13, R/NB pin; The SD interface circuit comprises SD interface chip SD1; The VSS pin of SD interface chip SD1, GROUND pin be ground connection respectively; The DAT0-DAT3 pin of SD interface chip SD1 and the NFC_DATA0-NFC_DATA3 pin of microprocessor MPU connect one to one; The CARD pin of SD interface chip SD1 is connected with the MPU_AD14 pin of microprocessor MPU; The CMD pin is connected with the MCMD pin of microprocessor MPU; The CLK pin is connected with the MCK pin of microprocessor MPU; The CARD pin of SD interface chip SD1 connects with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively through resistance R 55 through resistance R 3, DAT1 pin through resistance R 51, DAT0 pin through resistance R 50, CLK pin through resistance R 14, CMD pin through resistance R 48, DAT3 pin through resistance R 16, DAT2 pin, and the resistance R 55 of the resistance R 3 of the resistance R 51 of the resistance R 50 of the resistance R 14 of the resistance R 48 of the resistance R 16 of the CARD pin of SD interface chip SD1, DAT2 pin, DAT3 pin, CMD pin, CLK pin, DAT0 pin, DAT1 pin also inserts ground connection after the capacitor C 28 altogether;

Like Figure 10-shown in Figure 12.Voicefrequency circuit comprises recording circuit, power amplifier, head circuit; Recording circuit comprises loudspeaker X1; First pin of loudspeaker X1 connects the MIC_IN pin of microprocessor MPU through electric capacity TC7; The second pin ground connection of loudspeaker X1, loudspeaker first pin are also inserted the VDD33 pin of microprocessor MPU through pull-up resistor R34, micropkonic second pin also inserts the VDD33 pin of microprocessor MPU through capacitor C 51; Power amplifier comprises loudspeaker LS2; The terminals of loudspeaker LS2 insert the SPKMINUS pin of microprocessor MPU; Another terminals insert the SPKPLUS pin of microprocessor MPU through electric capacity TC6; The terminals that loudspeaker LS2 inserts the SPKMINUS pin of microprocessor MPU also pass through static impedance device ESD2 ground connection, and the terminals that loudspeaker LS2 inserts the SPKPLUS pin of microprocessor MPU also pass through static impedance device ESD1 ground connection; Head circuit comprises that model is the earphone chip J2 of ST-017ASMT-040-100; Earphone chip J2 has four pins; First pin ground connection of its headphone chip J2; Second pin of earphone chip J2 is through the inductance L 3 of series connection each other, the HPL pin that capacitor C 43 inserts microprocessor MPU; The 3rd pin of earphone chip J2 is divided into three the tunnel through the inductance L 2 of series connection each other, the HPR pin that capacitor C 42 inserts microprocessor MPU after the 4th pin of earphone chip J2 is connected to inductance FB1, and the resistance R 28 of leading up to inserts the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; Another road is through capacitor C 41 ground connection, and Third Road inserts the MPU_AD15 pin of microprocessor MPU through resistance R 27;

Shown in figure 13.Touch screen control circuit comprises touch control chip U8; Touching control chip U8 model is ZT2083, and the SCL pin that touches control chip U8 inserts the GPIO10 pin of microprocessor MPU, and the SDA pin inserts the GPIO9 pin of microprocessor MPU; CAD1 pin, GND pin be ground connection respectively; The PENIRON pin inserts the SPI_CS pin of microprocessor MPU, has two-way to draw lead on the VCC pin of touch control chip U8, and VCC pin one pass goes out lead through capacitor C 21 ground connection; Another pass of VCC pin goes out the VDDIO1-VDDIO3 pin that lead inserts microprocessor MPU respectively; The XP pin that touches control chip U8 passes through the AD0 pin that resistance R 65 inserts microprocessor MPUs, and the XP pin touches the AD2 pin of the YP pin of control chip U8 through resistance R 66 access microprocessor MPUs also through capacitor C 56 ground connection; And the YP pin is also through capacitor C 57 ground connection; The XN pin that touches control chip U8 passes through the AD1 pin that resistance R 63 inserts microprocessor MPUs, and the XN pin touches the AD3 pin of the YN pin of control chip U8 through resistance R 64 access microprocessor MPUs also through capacitor C 58 ground connection; And the YN pin also has the control output lead to draw respectively through electric capacity 59 ground connection on the XP pin of said touch control chip U8, YP pin, XN pin, the YN pin;

Shown in figure 14.Display control circuit comprises TFTLCD display control chip, the triode Q3 that is electrically connected with the TFTLCD display control chip; TFTLCD display control chip model is QD028007A0-37; The DB0-DB7 pin of TFTLCD display control chip, GND pin be ground connection respectively; The VCC1 pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; The CS pin of TFTLCD display control chip inserts the MPU_CS pin of microprocessor MPU; The RS pin inserts the MPU_A0 pin of microprocessor MPU, and the WR pin inserts the MPU_WR pin of microprocessor MPU, and the RD pin inserts the MPU_RD pin of microprocessor MPU; The X+ of TFTLCD display control chip, Y+, X-, Y-pin are corresponding to respectively static impedance device ESD3, ESD4, ESD5, ESD6 ground connection; Also be connected to the control signal incoming line on X+, Y+, X-, the Y-pin respectively, the LEDA pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively, and the LEDK1-LEDK4 pin of TFTLCD display control chip connects the collector that triode Q3 is inserted in the back altogether; The DB10-DB17 pin of TFTLCD display control chip connects one to one with the MPU_AD0-MPU_AD7 pin of microprocessor MPU respectively; Have two-way to draw lead on the RESET pin of TFTLCD display control chip, a pass goes out lead and is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively through resistance R 74 on the RESET pin, and another pass goes out lead and passes through capacitor C 7 ground connection on the RESET pin; After connecing altogether, the VCI pin of TFTLCD display control chip, VCC2 pin be divided into two line conductors; VCI pin, VCC2 pin connect back one line conductor altogether through capacitor C 39 ground connection, and VCI pin, VCC2 pin connect another line conductor of back altogether and be connected the grounded emitter of said triode Q3 with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; Base stage is connected with the USB_BOOT pin of microprocessor MPU through resistance R 72, also is connected to resistance R 73 between the base stage of triode Q3 and the emitter;

Shown in figure 15.The camera circuit comprises the camera chip J1 with 26 pins, the triode Q6 that is electrically connected with camera chip J1, and the model of camera chip J1 is TGB130VS01, and camera chip J1 first pin is vacant; The second pin ground connection, the 3rd pin inserts the GPIO9 pin of microprocessor MPU, is divided into two-way after the 4th pin of camera chip J1 is connected to resistance R 25; Lead up to capacitor C 14 ground connection, the LDO_V33A_O pin of microprocessor MPU is inserted on another road, and the 5th pin of camera chip J1 inserts the GPIO10 pin of microprocessor MPU; The 6th pin, the 8th pin insert respectively in the camera, and the 7th pin of camera chip J1 is divided into two-way, and the 7th pin is leaded up to resistance R 43 and inserted triode Q6 collectors; Triode Q6 base stage is inserted through resistance R 44 in another road, and the 9th pin of camera chip J1 inserts the VIHREF pin of microprocessor MPU, and the tenth pin of camera chip J1 is divided into two-way; The tenth pin is leaded up to inductance L 5 and is connect+the 1.8V power supply; Another road is through capacitor C 20 ground connection, and the 11 pin of camera chip J1 is divided into two-way, and the inductance L 6 of leading up to is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; Another road is through capacitor C 22 ground connection; The 12 pin of camera chip J1 connects the GPIO16_WU pin of microprocessor MPU, and the 13 pin connects the GPIO23_WU pin of microprocessor MPU, and the 14 pin connects the GPIO3_WU pin of microprocessor MPU; The 15 pin ground connection of camera chip J1; The 16 pin connects the GPIO17_WU pin of microprocessor MPU, and the 18 pin connects the GPIO18_WD pin of microprocessor MPU, and the 19 pin connects the GPIO22_WD pin of microprocessor MPU; The 20 pin connects the GPIO19_WD pin of microprocessor MPU; The 21 pin connects the GPIO21_WD pin of microprocessor MPU, and the 22 pin connects the GPIO20_WD pin of microprocessor MPU, and the 23,24 pins of camera chip J1 are vacant; The 25,26 pins connect back ground connection altogether; The grounded emitter of triode Q6, collector inserts the GPIO5_WU pin of microprocessor MPU, and the collector of triode Q6 also inserts the LD0_V33A_O pin of microprocessor MPU through resistance R 45.

It is the microprocessor of LQFP144 that the utility model adopts the stronger model of arithmetic capability; The master routine crystal oscillating circuit provides clock signal for the master routine in the microprocessor; The RTC crystal oscillating circuit provides the elapsed time clock signal to microprocessor; Realize the filtering of signal through the RC filtering circuit that connects on the microprocessor, realize the electromagnetic oscillation of learning machine through the LC oscillatory circuit that constitutes by inductance and electric capacity parallel with one another that connects on the microprocessor.Mu balanced circuit is introduced external power source, can voltage stabilizing be provided to boot-strap circuit through the voltage stabilizing chip, can realize the learning machine safety opening terminal through boot-strap circuit again, has avoided because the infringement that instantaneous high pressure causes the learning machine circuit.Electric power management circuit is carrying out Charge Management in charging process; Realize the charging of usb data line through usb circuit; Electric capacity parallel with one another has improved the charge efficiency of learning machine effectively in the usb circuit, and the static impedance device that inserts in the usb circuit has simultaneously improved the ability of charging circuit inhibition static.SD interface, flash chip, memory interface can be realized multi-form data storage, and can improve the storage capacity of learning machine as required, have solved the weak problem of learning machine storage capacity.Loudspeaker X1 inserts in the microprocessor and realizes sound-recording function, and power amplifier is realized antistatic purpose through the static impedance device, has improved playback effect, and head circuit has been realized the function of learning machine earphone playback.Touch control chip display screen signal is carried out centralized control and processing, export control signal in the display screen of the control output lead access learning machine of touch control chip, increase signal output intensity through the electric capacity that touches on the control chip respective pins.The security that the electric capacity that each pin of TFTLCD display control chip inserts can improve circuit, triode cooperates with the TFTLCD display control chip simultaneously, has improved the circuit signal antijamming capability.Camera chip transfers to microprocessor after the picture signal of gathering is handled, and constitutes the LC oscillatory circuit through the inductance on the same pin of camera chip, electric capacity, and realizes the amplification transmission of signal through triode.

Claims (1)

1. a learning machine circuit is characterized in that: include governor circuit, voltage stabilizing boot-strap circuit, charging circuit, memory circuit, voicefrequency circuit, touch screen control circuit, display control circuit, camera circuit;

Said governor circuit comprises that model is the microprocessor MPU of LQFP144; The PWMUSB_BOOT/GPIO4_WD pin of said microprocessor MPU connects power supply through resistance R 68, the pushbutton switch SW16 of mutual series connection; VCM pin, the BANDGAP pin of microprocessor MPU connect power supply ground through electric capacity parallel with one another respectively; The R100K_TS pin of microprocessor MPU connects power supply ground through the RC filtering circuit; Be connected with mutual resistance R of connecting 24 and capacitor C 36 between the RREF pin of microprocessor MPU and the VDD pin; Also lead to lead ground connection between resistance R 24, the capacitor C 36 between RREF pin and the VDD pin; The SPVDD2 pin of microprocessor MPU, VDD3/DC_V18_O pin are respectively through capacitor C parallel with one another 54, C60 ground connection; The DC_SW18 pin of microprocessor MPU inserts capacitor C 54 parallel with one another on the VDD3/DC_V18_O pin, the parallel connected end of C60 through diode in series D4, inductance L 1, is connected to the master routine crystal oscillating circuit between the XTAL12MO pin of microprocessor MPU, the XTAL12MI pin, is connected to the RTC crystal oscillating circuit between the XTAL32KO pin of microprocessor MPU, the XTAL32KI pin;

Said voltage stabilizing boot-strap circuit comprises boot-strap circuit, mu balanced circuit; Said boot-strap circuit comprises triode Q4, FET Q2, FET Q5, diode BAT54C; The grid of said FET Q5 connects power supply ground through resistance R 146; Drain electrode inserts said mu balanced circuit, also is connected to diode D6 between the grid of FET Q5, the drain electrode, and source electrode is through capacitor C 63 ground connection; The grid of said FET Q2 is connected with the collector of triode Q4; The source electrode of the drain electrode of FET Q2 and FET Q5 connects the SPVDD1 pin that microprocessor MPU is inserted in the back altogether; The source electrode of FET Q2 inserts the VBAT pin of microprocessor MPU, also is connected to resistance R 49 between the grid of FET Q2 and the source electrode; The grounded emitter of said triode Q4, base stage are divided into two-way after being connected to resistance R 57, are connected to the GPIO1_W pin that microprocessor MPU is inserted in resistance R 15 backs on the way, and another road is through resistance R 29 ground connection; Said diode BAT54C the 3rd pin inserts the resistance R 57 on the triode Q4 base stage; Diode BAT54C first pin inserts the VBAT pin of microprocessor MPU through pushbutton switch SW3; Be divided into two-way after also being connected to resistance R 56 on diode BAT54C first pin; One the road inserts the GPIO0_W pin of microprocessor MPU, and another road is divided into two-way through resistance R 52 ground connection after diode BAT54C second pin is connected to resistance R 53; One the road inserts the WAKEUP pin of microprocessor MPU, and another road is through capacitor C 25 ground connection; Said mu balanced circuit comprises two voltage stabilizing chip U3, U6; The VSS pin of voltage stabilizing chip U3 and U6 is ground connection respectively, and the VOUT pin of voltage stabilizing chip U3 is through capacitor C 78 ground connection, and the VOUT pin of voltage stabilizing chip U6 is through capacitor C 79 ground connection; The VOUT pin of voltage stabilizing chip U3 and U6 also inserts the SPVDD2 pin of microprocessor MPU respectively; The VIN pin of said voltage stabilizing chip U3 and U6 is divided into two-way respectively, and the VIN pin of voltage stabilizing chip U3 is leaded up to capacitor C 80 ground connection, and another road is connected with the drain electrode of FET Q5 in the boot-strap circuit; The VIN pin of voltage stabilizing chip U6 is leaded up to capacitor C 30 ground connection, and another road is connected with the drain electrode of FET Q5 in the boot-strap circuit;

Said charging circuit comprises electric power management circuit, usb circuit, Connection Block; Said electric power management circuit comprises that model is the charging chip U11 of LC4054; Be connected to resistance R 60 between the CHRG pin of charging chip U11 and the BAT pin, the GND pin ground connection of charging chip U11, the PROG pin is through resistance R 8 ground connection; Also have two on the BAT pin of charging chip U11 and draw lead; Draw the VBAT pin that lead connects microprocessor MPU for one on the BAT pin, another root is drawn lead through capacitor C 26 ground connection on the BAT pin, has two to draw lead on the VCC pin of said charging chip U11; On the VCC pin one draw lead through on the diode D2 that draws connect+the 5V power supply, another root is drawn lead through capacitor C 72 ground connection on the VCC pin; Said usb circuit comprises the USB interface chip; The NC1-NC4 pin of said USB interface chip connects back ground connection altogether; Be connected to four pass on the VBUS pin of USB interface chip and go out lead; A pass goes out lead through capacitor C parallel with one another 24, C29 ground connection on the VBUS pin, goes up another pass on the VBUS pin and goes out to be connected to diode D1 on the lead, and Third Road is drawn lead and connect+the 5V power supply on the VBUS pin; The 4th pass is divided into two-way after going out to be connected on the lead resistance R 11 again on the VBUS pin; The resistance R 36 of leading up on the resistance R 11 inserts the MPU_AD12/GPIO26_WU pin of microprocessor MPU, and another road is through resistance R 35 ground connection on the resistance R 11, and DP pin, the DM pin of the DP pin of said USB interface chip, DM pin and microprocessor MPU connect one to one; The ID pin of USB interface chip is vacant; GND pin ground connection also is connected to static impedance device ESD9 between the VBUS pin of said USB interface chip and the GND pin, also be connected to mutual static impedance device ESD7, the ESD8 that connects between DM pin and the DP pin; Said Connection Block comprises the web member CON2 of bipod; Socket power supply ground on the GND pin of said web member CON2; There is two-way to draw lead on the VBAT pin of web member CON2; A pass goes out the VBAT pin that lead connects microprocessor MPU on the VBAT pin, and another pass goes out lead and connects power supply ground through electric capacity TC3 on the VBAT pin;

Said memory circuit comprises main memory circuit, flash memory circuit, SD interface circuit; Said main memory circuit comprises that model is the memory chip U5 of K4S281632F; The A0-A12 pin of said memory chip U5 and the MADDR0-MADDR12 pin of microprocessor MPU connect one to one; MBA0, the MBA1 pin of BA0, BA1 pin and microprocessor MPU connect one to one; MCAS, the MRAS pin of CAS, RAS pin and microprocessor MPU connect one to one; The MDATA0-MDATA15 pin of the DQ0-DQ15 pin memory chip U5 of memory chip U5 connects one to one, and the CS pin of memory chip U5 is connected with the MCS pin of microprocessor MPU, and the WE pin is connected with the MWR pin of microprocessor MPU; MBE1 pin, the MBE0 pin of the UDQM of memory chip U5, LDQM pin and microprocessor MPU connect one to one; MCLK, the MCKE pin of CLK, CKE pin and microprocessor MPU connect one to one, and are connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively after the VDDQ1-VDDQ4 pin of memory chip U5 connects altogether again, and the VSSQ1-VSSQ4 pin connects back ground connection altogether; And be connected to capacitor C parallel with one another 38, C40 between the VDDQ1 pin of memory chip U5 and the VSSQ4 pin; Be connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively again after the VDD1-VDD3 pin of memory chip U5 connects altogether, connect power supply ground after the VSS1-VSS3 pin connects altogether, and be connected to capacitor C parallel with one another 9, C35 between the VSS1 pin of memory chip U5 and the VDD3 pin; Said flash memory circuit comprises flash chip U9; The RE pin of said flash chip U9 is connected with the MCMD pin of microprocessor MPU; The CE pin is connected with the NFC_CE0 pin of microprocessor MPU; The DNU pin is connected with the NFC_CE1 pin of microprocessor MPU; The CLE pin is connected with the NFC_CLE pin of microprocessor MPU; The ALE pin is connected with the NFC_ALE pin of microprocessor MPU, and the WE pin is connected with the NFC_WE pin of microprocessor MPU, and WP pin, VCC1 pin, VCC2 pin are connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively separately; The IO0-IO7 pin of flash chip U9 and the NFC_DATA0-NFC_DATA7 pin of microprocessor MPU connect one to one, and the NC5 pin of said memory chip U9 is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively through resistance R 17, R26 through resistance R 23, DNU pin through resistance R 12, CE pin through resistance R 13, R/NB pin; Said SD interface circuit comprises SD interface chip SD1; The VSS pin of said SD interface chip SD1, GROUND pin be ground connection respectively; The DAT0-DAT3 pin of SD interface chip SD1 and the NFC_DATA0-NFC_DATA3 pin of microprocessor MPU connect one to one; The CARD pin of SD interface chip SD1 is connected with the MPU_AD14 pin of microprocessor MPU; The CMD pin is connected with the MCMD pin of microprocessor MPU; The CLK pin is connected with the MCK pin of microprocessor MPU; The CARD pin of SD interface chip SD1 connects with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively through resistance R 55 through resistance R 3, DAT1 pin through resistance R 51, DAT0 pin through resistance R 50, CLK pin through resistance R 14, CMD pin through resistance R 48, DAT3 pin through resistance R 16, DAT2 pin, and the resistance R 55 of the resistance R 3 of the resistance R 51 of the resistance R 50 of the resistance R 14 of the resistance R 48 of the resistance R 16 of the CARD pin of SD interface chip SD1, DAT2 pin, DAT3 pin, CMD pin, CLK pin, DAT0 pin, DAT1 pin also inserts ground connection after the capacitor C 28 altogether;

Said voicefrequency circuit comprises recording circuit, power amplifier, head circuit; Said recording circuit comprises loudspeaker X1; First pin of said loudspeaker X1 connects the MIC_IN pin of microprocessor MPU through electric capacity TC7; The second pin ground connection of loudspeaker X1, said loudspeaker first pin are also inserted the VDD33 pin of microprocessor MPU through pull-up resistor R34, micropkonic second pin also inserts the VDD33 pin of microprocessor MPU through capacitor C 51; Said power amplifier comprises loudspeaker LS2; The terminals of said loudspeaker LS2 insert the SPKMINUS pin of microprocessor MPU; Another terminals insert the SPKPLUS pin of microprocessor MPU through electric capacity TC6; The terminals that said loudspeaker LS2 inserts the SPKMINUS pin of microprocessor MPU also pass through static impedance device ESD2 ground connection, and the terminals that loudspeaker LS2 inserts the SPKPLUS pin of microprocessor MPU also pass through static impedance device ESD1 ground connection; Said head circuit comprises that model is the earphone chip J2 of ST-017ASMT-040-100; Said earphone chip J2 has four pins; First pin ground connection of its headphone chip J2; Second pin of earphone chip J2 is through the inductance L 3 of series connection each other, the HPL pin that capacitor C 43 inserts microprocessor MPU; The 3rd pin of earphone chip J2 is divided into three the tunnel through the inductance L 2 of series connection each other, the HPR pin that capacitor C 42 inserts microprocessor MPU after the 4th pin of earphone chip J2 is connected to inductance FB1, and the resistance R 28 of leading up to inserts the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; Another road is through capacitor C 41 ground connection, and Third Road inserts the MPU_AD15 pin of microprocessor MPU through resistance R 27;

Said touch screen control circuit comprises touch control chip U8; Said touch control chip U8 model is ZT2083, and the SCL pin that touches control chip U8 inserts the GPIO10 pin of microprocessor MPU, and the SDA pin inserts the GPIO9 pin of microprocessor MPU; CAD1 pin, GND pin be ground connection respectively; The PENIRON pin inserts the SPI_CS pin of microprocessor MPU, has two-way to draw lead on the VCC pin of said touch control chip U8, and VCC pin one pass goes out lead through capacitor C 21 ground connection; Another pass of VCC pin goes out the VDDIO1-VDDIO3 pin that lead inserts microprocessor MPU respectively; The XP pin that touches control chip U8 passes through the AD0 pin that resistance R 65 inserts microprocessor MPUs, and the XP pin touches the AD2 pin of the YP pin of control chip U8 through resistance R 66 access microprocessor MPUs also through capacitor C 56 ground connection; And the YP pin is also through capacitor C 57 ground connection; The XN pin that touches control chip U8 passes through the AD1 pin that resistance R 63 inserts microprocessor MPUs, and the XN pin touches the AD3 pin of the YN pin of control chip U8 through resistance R 64 access microprocessor MPUs also through capacitor C 58 ground connection; And the YN pin also has the control output lead to draw respectively through electric capacity 59 ground connection on the XP pin of said touch control chip U8, YP pin, XN pin, the YN pin;

Said display control circuit comprises TFTLCD display control chip, the triode Q3 that is electrically connected with the TFTLCD display control chip; Said TFTLCD display control chip model is QD028007A0-37; The DB0-DB7 pin of TFTLCD display control chip, GND pin be ground connection respectively; The VCC1 pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; The CS pin of TFTLCD display control chip inserts the MPU_CS pin of microprocessor MPU; The RS pin inserts the MPU_A0 pin of microprocessor MPU, and the WR pin inserts the MPU_WR pin of microprocessor MPU, and the RD pin inserts the MPU_RD pin of microprocessor MPU; The X+ of TFTLCD display control chip, Y+, X-, Y-pin are corresponding to respectively static impedance device ESD3, ESD4, ESD5, ESD6 ground connection; Also be connected to the control signal incoming line on X+, Y+, X-, the Y-pin respectively, the LEDA pin of TFTLCD display control chip is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively, and the LEDK1-LEDK4 pin of TFTLCD display control chip connects the collector that triode Q3 is inserted in the back altogether; The DB10-DB17 pin of TFTLCD display control chip connects one to one with the MPU_AD0-MPU_AD7 pin of microprocessor MPU respectively; Have two-way to draw lead on the RESET pin of TFTLCD display control chip, a pass goes out lead and is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively through resistance R 74 on the RESET pin, and another pass goes out lead and passes through capacitor C 7 ground connection on the RESET pin; After connecing altogether, the VCI pin of TFTLCD display control chip, VCC2 pin be divided into two line conductors; VCI pin, VCC2 pin connect back one line conductor altogether through capacitor C 39 ground connection, and VCI pin, VCC2 pin connect another line conductor of back altogether and be connected the grounded emitter of said triode Q3 with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; Base stage is connected with the USB_BOOT pin of microprocessor MPU through resistance R 72, also is connected to resistance R 73 between the base stage of triode Q3 and the emitter;

Said camera circuit comprises the camera chip J1 with 26 pins, the triode Q6 that is electrically connected with camera chip J1, and the model of said camera chip J1 is TGB130VS01, and camera chip J1 first pin is vacant; The second pin ground connection, the 3rd pin inserts the GPIO9 pin of microprocessor MPU, is divided into two-way after the 4th pin of camera chip J1 is connected to resistance R 25; Lead up to capacitor C 14 ground connection, the LDO_V33A_O pin of microprocessor MPU is inserted on another road, and the 5th pin of camera chip J1 inserts the GPIO10 pin of microprocessor MPU; The 6th pin, the 8th pin insert respectively in the camera, and the 7th pin of camera chip J1 is divided into two-way, and the 7th pin is leaded up to resistance R 43 and inserted triode Q6 collectors; Triode Q6 base stage is inserted through resistance R 44 in another road, and the 9th pin of camera chip J1 inserts the VIHREF pin of microprocessor MPU, and the tenth pin of camera chip J1 is divided into two-way; The tenth pin is leaded up to inductance L 5 and is connect+the 1.8V power supply; Another road is through capacitor C 20 ground connection, and the 11 pin of camera chip J1 is divided into two-way, and the inductance L 6 of leading up to is connected with the VDDIO1-VDDIO3 pin of microprocessor MPU respectively; Another road is through capacitor C 22 ground connection; The 12 pin of camera chip J1 connects the GPIO16_WU pin of microprocessor MPU, and the 13 pin connects the GPIO23_WU pin of microprocessor MPU, and the 14 pin connects the GPIO3_WU pin of microprocessor MPU; The 15 pin ground connection of camera chip J1; The 16 pin connects the GPIO17_WU pin of microprocessor MPU, and the 18 pin connects the GPIO18_WD pin of microprocessor MPU, and the 19 pin connects the GPIO22_WD pin of microprocessor MPU; The 20 pin connects the GPIO19_WD pin of microprocessor MPU; The 21 pin connects the GPIO21_WD pin of microprocessor MPU, and the 22 pin connects the GPIO20_WD pin of microprocessor MPU, and the 23,24 pins of camera chip J1 are vacant; The 25,26 pins connect back ground connection altogether; The grounded emitter of said triode Q6, collector inserts the GPIO5_WU pin of microprocessor MPU, and the collector of triode Q6 also inserts the LD0_V33A_O pin of microprocessor MPU through resistance R 45.

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