CN202305792U

CN202305792U - Three-channel digital tracking receiver

Info

Publication number: CN202305792U
Application number: CN2011204244204U
Authority: CN
Inventors: 房福松; 张向东; 帅国祥
Original assignee: NANJING XINXUAN ELECTRONIC SYSTEM ENGINEERING Co Ltd
Current assignee: NANJING XINXUAN ELECTRONIC SYSTEM ENGINEERING Co Ltd
Priority date: 2011-11-01
Filing date: 2011-11-01
Publication date: 2012-07-04
Anticipated expiration: 2021-11-01

Abstract

The utility model discloses a three-channel digital tracking receiver, which comprises a high-speed analog/digital (AD) sampling module and a signal processing module, wherein the signal processing module comprises a digital signal processor (DSP) chip, a field programmable gate array (FPGA), a control unit, a driving unit and the like. The three-channel digital tracking receiver can automatically detect a target and send measurement data of a distance angle error of the tracked and measured target to a data processing module; and due to high-speed AD sampling, the resolution of target distance detection can be improved. The receiver processes three paths of intermediate-frequency signals input by a radar so as to extract target distance information and angle errors.

Description

Triple channel numeral track receiver

Technical field

The utility model relates to three tunnel intermediate-freuqncy signals of getting off to the radar receiving system samples and handles, and is used in particular for the triple channel numeral track receiver in the monopulse system radar system.

Background technology

Along with the develop rapidly of electronic chip technology, at a high speed, volume is little and low in energy consumption be the main direction of its development.And the conventional analogue receiver can not satisfy modern Application in the radar system, so digital receiver has replaced its position, in whole radar, plays crucial effects.

Summary of the invention

In order to solve the problem that exists in the prior art; The utility model proposes a kind of triple channel numeral track receiver; Its high-speed AD sampling module can carry out high-speed sampling to target and improve target range resolution, target is asked processing such as mould, accumulation, MTD, CFAR can improve the ability of finding target.Concrete technical scheme is following:

A kind of triple channel numeral track receiver comprises high-speed AD sampling section, signal processing and data processor; The AD sampling section comprises AD sample circuit and I, Q demodulator circuit; Said AD sampling is sampled to three tunnel intermediate-freuqncy signals of radar input, and the output terminal of AD sample circuit connects the input end of I, Q demodulator circuit, and I, Q demodulator circuit are exported six road I, Q signal; Said signal processing comprises that signal processing module comprises dsp chip, fpga chip, control module and driver element;

For dsp chip: dsp chip is connected communication with fpga chip, dsp chip is communicated by letter with data processor through interface conversion circuit; Dsp chip is connected with storer;

For fpga chip: fpga chip connects the output terminal of I, Q demodulator circuit; Fpga chip connects control module through driver element; Fpga chip is communicated by letter with data processor through interface conversion circuit; Fpga chip is connected with storer.

The principle of work of AD sampling section is: the AD sampling section comprises high-speed AD sampling function and digital I, Q demodulation function; The AD sampling is carried out high-speed sampling to three tunnel intermediate-freuqncy signals of radar input; Digital signal after the sampling is moved digital medium-frequency signal to base band through Digital Down Convert and is done the IQ demodulation; This work and Digital Down Convert are accomplished simultaneously, by the numerical control local oscillator export respectively sine, cosine signal and digital medium-frequency signal respectively mixing obtain the IQ baseband signal; Last channel filtering produces 6 road I, Q signal respectively with other frequency filtering beyond the baseband signal.The function that the AD sampling section realizes all can be realized by ripe circuit in the prior art, is further limited at this.

Said data processor is PC, and PC processs and displays the information of signal processing output.The interface conversion circuit that is connected with dsp chip comprises RS232 conversion chip and RS422 conversion chip; The interface conversion circuit that is connected with fpga chip is the USB conversion chip.

Said sampling module comprises coupling buffer circuit, A/D transducer and clock circuit; The input end of said coupling buffer circuit is as the input end of this receiver, and the output terminal of coupling buffer circuit connects the input end of A/D transducer, and the output terminal of A/D transducer connects the input end of I, Q demodulator circuit; Clock circuit is that A/D transducer and digital signal processing circuit provide clock signal.

The input end of A/D transducer is connected with BPF..

Said fpga chip is loaded with differential conversion circuit, mod circuit, MTD, CFAR treatment circuit, target detection/decision circuit and angle error metering circuit; The input end of said differential conversion circuit connects the output terminal of I, Q demodulator circuit; The signal of the output of differential conversion circuit is passed to dsp chip after handling through mod circuit, coherent detection system MTD, CFAR treatment circuit and target detection/decision circuit successively.

Said target detection/decision circuit is sliding window detecting device.

This triple channel numeral track receiver has the real-time height, and structure is flexible, highly versatile, and modular design, the construction cycle is short, and system is easy to advantages such as maintenance and expansion.The utility model has adopted the digital signal Processing scheme of a kind of FPGA+DSP in the system design of single goal Radar Signal Processing, principle is following:

Very big data volume, processing speed is had relatively high expectations, but the relatively simple underlying algorithm of computing structure (as ask mould, CFAR, coherent accumulation, sliding window detect, from motion tracking etc.) be placed on and realize by hardware in the FPGA; And some data volumes are lower; Functions such as top layer algorithm that control structure is complicated (calculating like distance calculation, position angle calculating, the elevation angle) and assembly control, communication are flexible by addressing mode; The DSP of rich interface realizes, but so both requirement of real time has been taken into account dirigibility, the extensibility of system again; Reduce design difficulty, greatly reduced the volume and the power consumption of signal processing system.

FPGA adopts the StratixII of altera corp series high-performance digital logic device; Ask mould, video integration, CFAR, sliding window detection, target-recognition and angle calculation etc. all to accomplish with hardware in FPGA inside; Detect after the target, read in target correlation distance information and angle information by DSP and deliver to data processor and do further processing.The timing signal of radar need of work: repetitive frequency pulsed, main pulse, transponder pulse and blanking pulse produce by signal processing system.

Description of drawings

Fig. 1 triple channel numeral track receiver principle composition diagram,

Fig. 2 triple channel numeral track receiver CFAR schematic diagram,

The sliding window detector concept of Fig. 3 triple channel numeral track receiver figure,

Fig. 4 triple channel numeral track receiver signal processing flow figure.

Embodiment

Below in conjunction with accompanying drawing and embodiment the utility model is described further:

The input end of A/D transducer is connected with BPF..Said fpga chip is loaded with differential conversion circuit, mod circuit, MTD, CFAR treatment circuit, target detection/decision circuit and angle error metering circuit; The input end of said differential conversion circuit connects the output terminal of I, Q demodulator circuit; The signal of the output of differential conversion circuit is passed to dsp chip after handling through mod circuit, coherent detection system MTD, CFAR treatment circuit and target detection/decision circuit successively.Said target detection/decision circuit is sliding window detecting device.

1) carries out the high-speed AD sampling for three tunnel intermediate-freuqncy signals of radar input, then signal is carried out I, Q demodulation, finally export six road I, Q signal.

Big at a high speed dynamically A/D must accomplish low distortion, big dynamic, low-power consumption.The performance of if sampling is except outside the Pass the inherent characteristic with A/D itself has, and is also in close relations with peripheral circuit.The if sampling module is by coupling buffer circuit, A/D transducer, clock circuit, compositions such as digital signal processing circuit.The composing of these devices and printed circuit, other circuit all can influence the performance of A/D conversion, quadrature phase demodulation to its influence etc.Analog input before the A/D transducer adds a BPF., is used for signal and noise beyond the filtering sampling bandwidth, to prevent the back spectral aliasing of sampling.

2) in each pulse repetition time, to I _∑(i) and Q _∑(i) the two-way orthogonal signal obtain A after asking mould _∑(i); Other two-way obtains Δ a (i), Δ e (i).Whether after again the result being sent into CFAR treatment circuit, target detection, target decision device successively, judging has target to exist, and when detecting target measurement target distance and angle error again.

3) CFAR (CRAF) purpose provides the detection threshold that can avoid noise background clutter and disturbing effect comparatively speaking, has constant false-alarm probability when making target detection.Also be that radar keeps constant false-alarm probability in the complex background environment, realize the effective means that adaptive threshold detects, under ground unrest distributed known situation, native system adopted the method for Rayleigh distributed clutter thresholding CFAR to realize.

4) native system adopts sliding window detecting device to detect the judgement target, at first uses the first thresholding Go as target detection apart from one dimension CFAR, signal mode value A _∑(i) be quantified as " 0/1 " signal with Go after comparing, the number of echoes of receiving during like the inswept target of antenna beam is N, and then sliding accordingly window detecting device is made up of N-1 delay cell, and be T the time delay of each unit _rIf the secondary thresholding is K, if pulse sum >=K is scanned in N time of sliding window detecting device output, then thinking has echo signal.After detecting target, the extraction of target angle error voltage has adopted I, Q quadrature demodulation, digitizing normalizing method to accomplish.

5) DSP reads target range information and target direction angle error, angle of pitch control information are delivered to data processor.

6) data processing mainly carries out showing after the data processing to range information and angle error data that signal Processing is sent here.

The utility model under radar timing pip (PRF) effect, signal processing read at first that the intermediate frequency digital processing unit sends here with passage in the signal ∑ of each range unit _IAsk mould earlier, carry out the sliding window of CFAR and target and detect, obtain the target range data at last, deliver to other extension set after reading target range information by DSP.Detect after the target, under system software controls, azimuth angle error Δ A and angle of pitch error delta E that signal processing system reads corresponding target range door again carry out the angular error signal computing, thereby accomplish echo signal are carried out the tracking measurement processing.

Claims

1. a triple channel numeral track receiver is characterized in that comprising high-speed AD sampling section, signal processing and data processor;

The AD sampling section comprises AD sample circuit and I, Q demodulator circuit; Said AD sampling is sampled to three tunnel intermediate-freuqncy signals of radar input, and the output terminal of AD sample circuit connects the input end of I, Q demodulator circuit, and I, Q demodulator circuit are exported six road I, Q signal;

Said signal processing comprises that signal processing module comprises dsp chip, fpga chip, control module and driver element;

For dsp chip:

Dsp chip is connected communication with fpga chip, dsp chip is communicated by letter with data processor through interface conversion circuit; Dsp chip is connected with storer;

For fpga chip:

Fpga chip connects the output terminal of I, Q demodulator circuit; Fpga chip connects control module through driver element; Fpga chip is communicated by letter with data processor through interface conversion circuit; Fpga chip is connected with storer.

2. triple channel numeral track receiver according to claim 1 is characterized in that said data processor is PC, and PC processs and displays the information of signal processing output.

3. triple channel numeral track receiver according to claim 1 is characterized in that the interface conversion circuit that is connected with dsp chip comprises RS232 conversion chip and RS422 conversion chip; The interface conversion circuit that is connected with fpga chip is the USB conversion chip.

4. triple channel numeral track receiver according to claim 1 is characterized in that said sampling module comprises coupling buffer circuit, A/D transducer and clock circuit; The input end of said coupling buffer circuit is as the input end of this receiver, and the output terminal of coupling buffer circuit connects the input end of A/D transducer, and the output terminal of A/D transducer connects the input end of I, Q demodulator circuit; Clock circuit is that A/D transducer and digital signal processing circuit provide clock signal.

5. triple channel numeral track receiver according to claim 4 is characterized in that the input end of A/D transducer is connected with BPF..

6. triple channel numeral track receiver according to claim 1 is characterized in that said fpga chip is loaded with differential conversion circuit, mod circuit, MTD, CFAR treatment circuit, target detection/decision circuit and angle error metering circuit;

The input end of said differential conversion circuit connects the output terminal of I, Q demodulator circuit; The signal of the output of differential conversion circuit is passed to dsp chip after handling through mod circuit, coherent detection system MTD, CFAR treatment circuit and target detection/decision circuit successively.

7. triple channel numeral track receiver according to claim 6 is characterized in that said target detection/decision circuit is sliding window detecting device.