CN202260994U - PWM (Pulse-Width Modulation) control panel circuit - Google Patents
PWM (Pulse-Width Modulation) control panel circuit Download PDFInfo
- Publication number
- CN202260994U CN202260994U CN2011203774631U CN201120377463U CN202260994U CN 202260994 U CN202260994 U CN 202260994U CN 2011203774631 U CN2011203774631 U CN 2011203774631U CN 201120377463 U CN201120377463 U CN 201120377463U CN 202260994 U CN202260994 U CN 202260994U
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- CN
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- Prior art keywords
- control panel
- panel circuit
- fpga chip
- port ram
- dsp processor
- Prior art date
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- Expired - Fee Related
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- 230000009977 dual effect Effects 0.000 claims description 12
- 238000004891 communication Methods 0.000 abstract description 5
- 230000008901 benefit Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 4
- 239000013307 optical fiber Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000005693 optoelectronics Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000003550 marker Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Abstract
The utility model relates to a PWM control panel circuit, comprising a DSP (Digital Signal Processor) processor, a dual-port RAM (Random Access Memory), an FPGA (Field Programmable Gata Array) chip and a random access memory, wherein the DSP processor is a control core which is respectively communicated with the dual-port RAM and the FPGA chip through an address bus and a data bus; the DSP processor is further connected with the random access memory; the FPGA chip is for sending driving signals to a power unit or receiving state signals from the power unit. The PWM control panel circuit has advantages of fast communication speed, strong data processing ability and stable operation. The PWM control panel circuit can also control a plurality of power units of full-controlled converting devices.
Description
Technical field
The utility model relates to a kind of PWM control board circuit of power electronic equipment.
Background technology
The pwm pulse width modulated is a kind of analog control mode; Its variation according to respective loads comes the biasing of modulation crystal tube grid or base stage; Realize switching power supply output transistor or the change of transistor turns time; This mode can make the output voltage of power supply when operation conditions change, keep constant, is to utilize the numeral of microprocessor to export a kind of very effective technology that analog circuit is controlled.The PWM control technology is simple with its control, flexibly and the good advantage of dynamic response and the control mode of the extensive use of the power electronic technology that becomes also is the focus that people study.The processing speed of pwm circuit of the prior art and operational capability also have treatment to improve.
Summary of the invention
Be to solve prior art problems, the purpose of the utility model provides that a kind of communication speed is fast, data-handling capacity is strong, stable, the PWM control board circuit that can control a plurality of full-control type current device power cells.
For realizing above-mentioned purpose, the utility model is realized through following technical scheme:
A kind of PWM control board circuit; Comprise dsp processor, dual port RAM, fpga chip, random asccess memory; Described dsp processor is the control core, communicates through address bus and data/address bus and dual port RAM and fpga chip respectively, and described dsp processor also is connected with random asccess memory; Described fpga chip is used for power cell is sent the status signal of drive signal or received power unit.
Compared with prior art, the utility model has the advantages that:
1) use dual port RAM as communication interface, communication speed is fast, and minimum access time is 15ns.
2) this circuit all uses the technical grade chipset, and data processing speed is fast, and antijamming capability is strong.
3) the output signal can reach 18 tunnel transmitting-receivings, realizes the transmitting-receiving of multi-channel optical fibre signal.
Description of drawings
Fig. 1 is the structured flowchart of the utility model.
Embodiment
See Fig. 1; A kind of PWM control board circuit; Comprise dsp processor, dual port RAM, fpga chip, random asccess memory; Described dsp processor is the control core, communicates through address bus and data/address bus and dual port RAM and fpga chip respectively, and described dsp processor also is connected with random asccess memory; Described fpga chip is used for power cell is sent the status signal of drive signal or received power unit.
Communication part is used dual port RAM chip id T7026, and IDT7026 is the twoport static RAM (SRAM) of the high speed 16k * 16bits of American I DT company development.It is real dual port RAM, allows two (left and right) ports to read while write data, and each port has oneself independently control signal wire, address wire and data wire.But zero access data, minimum access time are 15ns, can be used with most of high-speed dsp processors, and need not to insert wait state.It has the Master/slave control pin, easily extension storage capacity and data bit width.IDT7026 also has the concentrator marker function except that having the dual-port access function, when data transmit, can constitute the multiple interfaces form.IDT7026 inwardly provides 16 bit data signals and 8 bit address signals.Dsp processor passes through control signal: BUSYRn, INTRn, CERn, SEMRn, XRWn, OERn again through these data and address signal dual port RAM chip id T7026 is write data and reading of data.Dsp processor reads the data that write IDT7026 through external interface D0-D15 on the control board and A0-A7.
Dsp processor is to use TMS320F28335, and address bus XA0-XA7 and the data/address bus XD0-XD15 of TMS320F28335 receive fpga chip and dual port RAM, through the enable signal control fpga chip and the dual port RAM work of address signal and each chip.Link to each other with a FM25CL64 (the Nonvolatile ferroelectric random asccess memory of 64K position) simultaneously and be used for preserving data after the power down.The command signal of dsp processor resolves into the drive signal of 18 road optoelectronic transceivers through fpga chip; Control 18 power cells and produce the PWM ripple; The state information of power cell sends fpga chip to through optoelectronic transceivers, after treatment, gives processor with information and handles.
Output is with fpga chip EP3C10E144I8 and 18 pairs of optical fiber input and output heads.EP3C10E144I8 receives data-signal and the conversion of address signal process that dsp processor is given, and drives every pair of optical fiber respectively and sends and the received power cell signal.
Claims (1)
1. PWM control board circuit; It is characterized in that; Comprise dsp processor, dual port RAM, fpga chip, random asccess memory; Described dsp processor is the control core, communicates through address bus and data/address bus and dual port RAM and fpga chip respectively, and described dsp processor also is connected with random asccess memory; Described fpga chip is used for power cell is sent the status signal of drive signal or received power unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203774631U CN202260994U (en) | 2011-09-28 | 2011-09-28 | PWM (Pulse-Width Modulation) control panel circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203774631U CN202260994U (en) | 2011-09-28 | 2011-09-28 | PWM (Pulse-Width Modulation) control panel circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202260994U true CN202260994U (en) | 2012-05-30 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203774631U Expired - Fee Related CN202260994U (en) | 2011-09-28 | 2011-09-28 | PWM (Pulse-Width Modulation) control panel circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202260994U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103176419A (en) * | 2013-03-14 | 2013-06-26 | 华北电力大学 | DSP (digital signal processing) control board compatible with TMS320F28x series |
-
2011
- 2011-09-28 CN CN2011203774631U patent/CN202260994U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103176419A (en) * | 2013-03-14 | 2013-06-26 | 华北电力大学 | DSP (digital signal processing) control board compatible with TMS320F28x series |
| CN103176419B (en) * | 2013-03-14 | 2015-10-21 | 华北电力大学 | The DSP control panel of compatible TMS320F28x series |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: RONGXIN POWER ELECTRONIC CO., LTD. STATE GRID CORP Free format text: FORMER OWNER: RONGXIN POWER ELECTRONIC CO., LTD. Effective date: 20121228 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20121228 Address after: 122000 Chaoyang City Chaoyang District, Twin Towers, Liaoning, No. three, No. 13 Patentee after: Chaoyang Power Supply Corp., Liaoning Power Co., Ltd. Patentee after: Rongxin Power Electronic Co., Ltd. Patentee after: State Grid Corporation of China Address before: 122000 Chaoyang City Chaoyang District, Twin Towers, Liaoning, No. three, No. 13 Patentee before: Chaoyang Power Supply Corp., Liaoning Power Co., Ltd. Patentee before: Rongxin Power Electronic Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120530 Termination date: 20140928 |
|
| EXPY | Termination of patent right or utility model |