CN202258252U

CN202258252U - Light-emitting diode (LED) serial row decoding circuit

Info

Publication number: CN202258252U
Application number: CN2011200020115U
Authority: CN
Inventors: 魏洵佳
Original assignee: Konka Group Co Ltd
Current assignee: Konka Group Co Ltd
Priority date: 2011-01-04
Filing date: 2011-01-04
Publication date: 2012-05-30
Anticipated expiration: 2021-01-04

Abstract

The embodiment of the utility model discloses a light-emitting diode (LED) serial row decoding circuit, which comprises an input socket, a bus buffering driver, a constant-current driving chip array, a row tube array, a serial shifting latch and an output socket, wherein the bus buffering driver is connected with the output end of the input socket; the constant-current driving chip array is connected with the output end of the bus buffering driver; the serial shifting latch is connected with the output end of the input socket and the output end of the bus buffering driver; the row tube array is connected with the output end of the serial shifting latch; and the output socket is respectively connected with the output end of the bus buffering driver, the output end of the serial shifting latch and the output end of the constant-current driving chip array. The LED serial row decoding circuit disclosed by the embodiment of the utility model is capable of simplifying an LED driving design and reducing the production cost and is beneficial to the extension of an LED module signal and the standardization of a signal interface.

Description

A kind of LED serial column decode circuitry

Technical field

The utility model relates to display screen actuation techniques field, relates in particular to a kind of LED serial column decode circuitry.

Background technology

At LED (Light Emitting Diode; Light emitting diode) during the control of display screen is used; The parallel-by-bit decoding of common dynamic LED drive plate all adopts 1-2 sheet row decoding chip 74HC138 to make up; Consider the versatility of 2-16 line scanning; Required capable input signal has taken 4 in 20 jack interface designs, sees the H [3..0] among Fig. 1, and all the other signals then comprise data R [2..0], G [2..0], B [2..0], shift clock SCLK, row latch signal/LATCH, open signal/OE and ground wire.

In dutycycle is that 1 static LED display screen and dutycycle are in 1/2,1/4,1/8,1/16 the dynamic LED display screen; The figure place of the line scan signals of launching is not quite similar; For example dutycycle is 1 not have line scan signals when promptly static, and H [3..0] need not be vacant, dutycycle be can use in 1/2 o'clock 1-2 position H [1..0] (2 time need not decoding), 1/4 o'clock with 2 H [1..0] or 4 H [3..0] that need not to decipher, 1/8 o'clock with 3 H [2..0], 1/16 o'clock with 4 H [3..0]; And in the design that need not row decoding; Then need increase bus buffer driver 74HC245, not calculate, so the general row decoding 74HC138 chip that adopts carries out the first-selection of row decoding as design.

Yet this traditional column decode circuitry has taken 4 in jack interface, therefore, makes the Interface design of LED drive plate have to be fixed on 20 pins, needs to adopt the flat cable of 20 lines, makes cost higher.

The utility model content

The utility model embodiment technical matters to be solved is; A kind of LED serial column decode circuitry is provided; Adopt a slice serial-shift latch to decipher to importing a bit string every trade signal; Available interface socket and signal wire with less signal substitutes traditional socket and signal wire realization LED driving, reduces production costs.

In order to solve the problems of the technologies described above; The utility model embodiment provides a kind of LED serial column decode circuitry; Comprise: input socket, bus buffer driver, constant-current driven chip array, serial-shift latch, administration-management array and accessory power outlet; Wherein, Said bus buffer driver is connected with the output terminal of said input socket, and said constant-current driven chip array is connected with said bus buffer output end of driver, and said serial-shift latch is connected with said bus buffer output end of driver with the output terminal of said input socket; Said administration-management array is connected with the output terminal of said serial-shift latch, and said accessory power outlet is connected with the output terminal of said bus buffer output end of driver, serial-shift latch and the output terminal of constant-current driven chip array respectively.

Preferably; Said input socket is 16 sockets; Wherein, Shift clock SCLK output terminal, row latch signal/LATCH output terminal and open signal/OE output terminal and be connected to said bus buffer driver, and comprise that a bit string every trade signal H_data output terminal is connected to said serial-shift latch.

Preferably, after the RGB three primary colors data buffering driving of said bus buffer driver with input, output to said constant-current driven chip array;

Said bus buffer driver with shift clock SCLK, row latch signal/LATCH, open and be divided into two-way after signal/OE buffering drives, the one tunnel outputs to said serial-shift latch and said constant-current driven chip array, the one tunnel outputs to said accessory power outlet.

Preferably; Said constant-current driven chip array the RGB three primary colors data of said bus buffer driver output with comprise shift clock SCLK, row latch signal/LATCH, open under the effect of control signal of signal/OE; It is luminous to drive corresponding LED; And export said RGB three primary colors data to said accessory power outlet, to output to the next stage led module.

Preferably; Said serial-shift latch is at shift clock SCLK, the row latch signal/LATCH of the output of said bus buffer driver and open under the effect of signal/OE; The serial row signal H_data of said input socket output is carried out the row decoding signal that serial-shift latchs the back generation; With the RGB three primary colors data sync of said constant-current driven chip array output, walking abreast outputs to said administration-management array;

The serial output terminal of said serial-shift latch links to each other with said accessory power outlet, and said serial row signal H_data is outputed to said accessory power outlet, so that said serial row signal H_data is outputed to the next stage led module.

Preferably, said administration-management array is under the effect of the parallel-by-bit decoded signal of said serial-shift latch output, and gating drives the LED of corresponding line.

Preferably, said serial-shift latch adopts 8 or 16 bit serial displacement latch, the decoding of going arbitrarily with the 2-16 of the odd-numbered line decoding that realizes durations such as comprising and embed new extendible other control signal.

Implement the utility model embodiment, have following beneficial effect:

LED serial column decode circuitry only needs a bit string every trade input signal just can realize the 2-16 decoding of row arbitrarily; The odd-numbered line decoding of duration such as comprise; Adopt 16 sockets just can satisfy the designing requirement of conventional LED drive plate; Thereby simplified system design, reduced production cost, and helped the expansion of led module signal and the standardization of signaling interface.

Description of drawings

Fig. 1 is existing 20 signal plug interface pin schematic layout patterns;

Fig. 2 is the LED serial column decode circuitry synoptic diagram of the utility model embodiment;

Fig. 3 is the interface pin schematic layout pattern of the input socket among Fig. 2;

Fig. 4 is the structural representation of serial row signal data.

Embodiment

To combine the accompanying drawing among the utility model embodiment below, the technical scheme among the utility model embodiment is carried out clear, intactly description, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the utility model protection.

Seeing also Fig. 2, is the LED serial column decode circuitry synoptic diagram of the utility model embodiment, and it comprises: input socket 11, bus buffer driver 12, constant-current driven chip array 13, serial-shift latch 14, administration-management array 15 and accessory power outlet 16, wherein:

Said input socket 11 is 16 signal plugs; Its output signal comprises: RGB three primary colors (red green blue tricolor) data, control signal and serial row signal; Wherein, shift clock SCLK (the Shift clock among the said control signal CTL (Control, control); Shift clock) output terminal, row latch signal/LATCH (latch; Latch) output terminal, open signal/OE (Output Enable, output allow) output terminal and be connected to said bus buffer driver 12, also have a H_data (serial row signal) output terminal to be connected to serial-shift latch 14;

Said bus buffer driver 12 is delivered to said constant-current driven chip array 13 after can adopting the RGB three primary colors data buffering driving of multi-disc 74HC245 with input; Shift clock SCLK, row latch signal/LATCH, open and be divided into two-way after signal/OE buffering drives; One the road delivers to said serial-shift latch 14 and said constant-current driven chip array 13 simultaneously; Another road outputs to said accessory power outlet 16, to pass to the next stage led module;

Said constant-current driven chip array 13 goes down to drive corresponding LED in the effect of control signal shift clock SCLK, row latch signal/LATCH; / OE cut-offs signal and is used for gray scale and shows, and with RGB three primary colors data through the accessory power outlet 16 continuous next stage led modules that pass to;

Said serial-shift latch 14 shift clock SCLK, the row latch signal/LATCH with open under the effect of signal/OE; The row decoding signal parallel that the serial row signal H_data serial-shift of importing is latched the back generation outputs to administration-management array 15; The wherein displacement of serial row signal H_data and latch with the displacement of 13 pairs of RGB three primary colors of said constant-current driven chip array data and latch synchronously is used to eliminate the capable shade that produces when row switches simultaneously and open signal/OE;

The serial output of said serial-shift latch 14 is connected with accessory power outlet 16, so that serial row signal H_data is outputed to the next stage led module;

Said administration-management array 15 drives the LED of corresponding line at the effect of the row decoding signal of said serial-shift latch 14 and the line output gating that goes down;

Said accessory power outlet 16 is 16 signal plugs; Signal allocation is identical with input socket 11; It will be from the RGB three primary colors data of said constant-current driven chip array 13; From the shift clock SCLK of said bus buffer driver 12, row latch signal/LATCH, open signal/OE and output to the next stage led module from the serial row signal H_data of said serial-shift latch 14;

Further, said serial-shift latch 14 can adopt 8 74 serial 595 chips or constant-current driven chips, also can adopt 16 constant-current driven chips, and can realize the arbitrarily decoding of row of 2-16, comprises and waits the odd-numbered line of duration to decipher.

Fig. 3 is the interface pin schematic layout pattern of the input socket among Fig. 2; Data input pin R [2..0] is distributed in that 1,5,9 pins, G [2..0] are distributed in 2,6,10 pins, B [2..0] is distributed in 3,7,11 pins among the figure; Row latch signal/LATCH is distributed in 13 pins, shift clock SCLK and is distributed in 14 pins, opens that signal/OE is distributed in 15 pins, serial row signal H_data is distributed in 16 pins, all the other 4,8,12 pin ground connection.

Fig. 4 is the structural representation of serial row signal data; Because row decoding has adopted the shift clock SCLK identical with RGB three primary colors data and row latch signal/LATCH; So the valid data of serial row signal be 16 at the end of each led module data in this data channel, this 16bit is respectively the capable control signal of the 0th to the 15th row from the low level to a high position, the row control signal be 1 o'clock open-minded; It is shutoff in 0 o'clock; It is capable of the capable serial row signal data of L7 to have provided 8 action attitudes when scanning L0 among the figure, and the eight action attitude sweep waveforms that its produces are with to adopt 3 inputs, one to open the waveform of 74HC138 code translator generation of input identical;

It is understandable that; Other data bit of serial row signal data; Can also expand and embed other new control signal; For example embed with open signal/OE signal different be exclusively used in the independent control signal that administration-management is turn-offed, the capable shadow problem that produces because of the administration-management turn-off delay that is prone to when being beneficial to more effective solution dynamic scan.

The generation that is to be noted that said serial row signal data H_data is that programming realizes among the FPGA (Field-Programmable Gate Array, field programmable gate array) in the PC control scanning board.

Description through the foregoing description can be known, the utlity model has following advantage:

LED serial column decode circuitry only needs a bit string every trade input signal just can realize the 2-16 decoding of row arbitrarily; The odd-numbered line decoding of duration such as comprise; Adopt 16 signal plugs just can satisfy the designing requirement of conventional LED drive plate; Thereby simplified system design, reduced production cost, and helped the expansion of led module signal and the standardization of signaling interface.

Above disclosedly be merely the utility model preferred embodiment, can not limit the interest field of the utility model certainly with this, the equivalent variations of therefore being done according to the utility model claim still belongs to the scope that the utility model is contained.

Claims

1. LED serial column decode circuitry; It is characterized in that; Comprise: input socket, bus buffer driver, constant-current driven chip array, serial-shift latch, administration-management array and accessory power outlet; Wherein, Said bus buffer driver is connected with the output terminal of said input socket, and said constant-current driven chip array is connected with said bus buffer output end of driver, and said serial-shift latch is connected with said bus buffer output end of driver with the output terminal of said input socket; Said administration-management array is connected with the output terminal of said serial-shift latch, and said accessory power outlet is connected with the output terminal of said bus buffer output end of driver, serial-shift latch and the output terminal of constant-current driven chip array respectively.

2. LED serial column decode circuitry as claimed in claim 1; It is characterized in that; Said input socket is 16 sockets; Wherein, shift clock SCLK output terminal, row latch signal/LATCH output terminal and open signal/OE output terminal and be connected to said bus buffer driver, and comprise that a bit string every trade signal H_data output terminal is connected to said serial-shift latch.

3. LED serial column decode circuitry as claimed in claim 2 is characterized in that, after the RGB three primary colors data buffering driving of said bus buffer driver with input, outputs to said constant-current driven chip array;

4. LED serial column decode circuitry as claimed in claim 3; It is characterized in that; Said constant-current driven chip array the RGB three primary colors data of said bus buffer driver output with comprise shift clock SCLK, row latch signal/LATCH, open under the effect of control signal of signal/OE; It is luminous to drive corresponding LED, and exports said RGB three primary colors data to said accessory power outlet, to output to the next stage led module.

5. LED serial column decode circuitry as claimed in claim 4; It is characterized in that; Said serial-shift latch is at shift clock SCLK, the row latch signal/LATCH of the output of said bus buffer driver and open under the effect of signal/OE; The serial row signal H_data of said input socket output is carried out the row decoding signal that serial-shift latchs the back generation, and with the RGB three primary colors data sync of said constant-current driven chip array output, walking abreast outputs to said administration-management array;

6. LED serial column decode circuitry as claimed in claim 5 is characterized in that, said administration-management array is under the effect of the parallel-by-bit decoded signal of said serial-shift latch output, and gating drives the LED of corresponding line.

7. LED serial column decode circuitry as claimed in claim 6 is characterized in that, said serial-shift latch adopts 8 or 16 bit serial displacement latch.