CN202231605U - Digital power supply regulation system of an ion radiotherapy accelerator - Google Patents

Abstract

The utility model relates to a digital power supply regulation system of an ion radiotherapy accelerator based on NiosII dual-core, which is applied to the high-precision digital power supply pulse and direct current operation ways of multiple topological types of the ion radiotherapy accelerator. The digital power supply regulation system of the ion radiotherapy accelerator comprises an FPGA chip, an Flash module, a memory unit synchronous dynamic random access memory, a synchronous static random access memory, a debugging JTAG interface of the system, an Ethernet chip, an optical fiber receiver, a general asynchronous receiver / transmitter serial communication device and a serial memory, an ADC analog-to-digital converter, a DAC digital-to-analog converter, a power supply failure protection signal input channel module and a pulse width modulation signal output channel module which are respectively connected with a pin of the FPGA chip and also comprises a system o the FPGA chip.

Description

Ion is controlled cancer accelerator digital power regulating system

Technical field

The utility model relates to a kind of ion based on the NiosII double-core and controls cancer accelerator digital power regulating system, goes for high accuracy number power pulse and DC operation mode that ion is controlled the multiple topological classification of cancer accelerator.

Background technology

Ion is controlled the cancer accelerator and is relied on magnet lens such as two utmost point iron, four utmost point iron to realize the control to line, and magnet is two kinds of pulse and direct currents to the operational mode of power supply.The pulsing operation of digital power requires power supply to export according to given waveform; And can between random waveform, switch; And given for waveform for less data output variable, generally is to the bigger at interval waveform of point of digital power control board transmission from remote computer; Therefore power supply need become the less at interval waveform of point with this waveform interpolation before output; In the pulse output procedure of digital power, need constantly to upgrade given current value to the digital power adjuster.Waveform transmission, waveform interpolation, above these operations of given renewal all need be monopolized the cpu time, and general digital power regulating system can't satisfy the requirement of digital power for pulsing operation.

Summary of the invention

The problem that the utility model exists to prior art; Provide a kind of with Altera Cyclone II EP2C70 FPGA (Field-Programmable Gate Array; Being field programmable gate array) digital circuit board is hardware platform; Under the universal asynchronous reception/dispensing device of Q (UART) us II IDE; Use SOPC builder instrument; Build the programmable system on chip that contains two Nios II cpu, realize that ion controls the ion of the control of cancer accelerator digital power under pulse and DC operation mode and control cancer accelerator digital power regulating system respectively two Nios II cpu being carried out software programming on this programmable system on chip.

To achieve these goals; The utility model patent adopts following technical scheme: a kind of ion is controlled cancer accelerator digital power regulating system; Comprise fpga chip, also comprise as non-volatile memory device deposit the upper layer software (applications) program Flash module of writing based on programmable system on chip, internal storage location synchronous DRAM, the debugging of static RAM, system synchronously during as the upper layer software (applications) program running connects jtag interface, in order to the Ethernet chip that realizes fpga chip and the network service of remote computer, in order to the fiber optic receiver that receives fiber-optic signal, in order to the universal asynchronous reception/dispensing device serial communication device and the serial memory of the serial communication that realizes fpga chip, with the output current of digital power or voltage transitions become digital quantity to send into the ADC analog to digital converter of fpga chip, the DAC digital to analog converter that converts the intermediate variable of digital power in the fpga chip to analog quantity output all links to each other with the pin of fpga chip; Comprise that also multiple power source error protection signal input channel module and pulse-width signal output channel module directly are connected to the general pin of fpga chip; Pulse width modulating signal output channel module is controlled turning on and off of insulated gate bipolar transistor through the pulse width modulating signal of exporting certain duty ratio, makes the given current value of power supply output.

Further, the model of described fpga chip is the Cyclone II EP2C70 of U.S. altera corp.

Further; Synchronous DRAM is following storage area according to the address static division, comprises Data Update sign, high accuracy number regulator parameter district, dc area, 256 impulse waveform districts, 2 interpolation given areas, 2 intermediate variable districts, current given waveform address, next given waveform address, current given waveform length, next given waveform length, receives buffer area.

Further, described fpga chip is attend system and is divided into communication domain and regulates the territory;

Described communication domain comprises a Nios II cpu, and ethernet controller, universal asynchronous reception/dispensing device nuclear are connected to a Nios II cpu through an Avalon bus; The one Nios II cpu controls Ethernet chip on the FPGA hardware platform through ethernet controller, examines universal asynchronous reception/dispensing device serial communication device of controlling on the FPGA hardware platform through universal asynchronous reception/dispensing device;

Described adjusting territory comprises the 2nd Nios II cpu; Second timer, second WatchDog Timer are connected to the 2nd Nios II cpu through the 2nd Avalon bus, and wherein the 2nd Nios II cpu is attached thereto the second timer that connects through the total line traffic control of the 2nd Avalon; Second WatchDog Timer, the operation of monitoring main program prevents program generation endless loop.

Further, described communication domain comprises that also first timer, first WatchDog Timer, clock phase-locked loop, boundary scan universal asynchronous receiving-transmitting transmitter are connected to a Nios II cpu through an Avalon bus; First timer is as the system clock of on programmable system on chip, transplanting embedded OS; The boundary scan universal asynchronous receiving-transmitting transmitter is the debugging interface of synchro system; The clock that the clock phase-locked loop branch occurs frequently offers a Nios II cpu and other assemblies through an Avalon bus; First WatchDog Timer, the operation of monitoring main program prevents program generation endless loop.

Further; Described fpga chip is attend system and is also included shared domain; Described shared domain comprises serial memory controller, Flash controller, controller of synchronous dynamic random storage, synchronous static RAM controller, general high accuracy number adjuster, and its connected mode is serial memory controller, Flash controller, controller of synchronous dynamic random storage, static RAM controller, general high accuracy number adjuster are connected to a Nios II cpu of communication domain and the 2nd Nios II cpu in adjusting territory respectively through an Avalon bus of communication domain and the 2nd Avalon bus in adjusting territory synchronously; Wherein, Described high accuracy number adjuster is to upgrade with given and intermediate variable when preserving its calculating by the interrupt service subroutine of second timer 152; Message communicating and exchanges data are carried out in the described communication domain memory block shared thus with regulating the territory, and the impulse waveform of completion regulating system is exported and switched.

Further; Described general high accuracy number adjuster is that the ion that the hardware language descriptive language is described is controlled cancer accelerator digital power IP kernel with synchronous optical fiber assembly module; Be embedded into fpga chip according to Avalon EBI standard and attend in the system, Nios II cpu reads and writes control through the Avalon data/address bus to the register of bottom.

Further; Described synchronous optical fiber assembly module comprises synchronous example table memory block, example decoding unit, and the signal of telecommunication that the example decoding unit will be sent into synchronous optical fiber assembly module is deciphered according to amplitude and frequency and decoding is sent to current example memory block and stores; Also include the example matching unit, the example matching unit matees current example memory block and synchronous example table memory block, and the example in the current example memory block is identical with arbitrary example in the synchronous example table, then sends synchronizing signal.

The beneficial effect of the utility model: this technical scheme is applicable to that ion controls the pulse and the direct current mode of cancer accelerator digital power; Can realize the waveform pulse of single trigger impulse, continuous trigger pulse, the same waveform pulse of continuous trigger or the continuous trigger variation of digital power, can be implemented in 256 zero-clearances between the impulse waveform and switch.

Description of drawings:

Fig. 1 is the utility model programmable system on chip structured flowchart;

Fig. 2 is the utility model hardware circuit diagram;

Fig. 3 is the static memory distribution diagram of the utility model synchronous DRAM (SDRAM);

Fig. 4 simplifies topology diagram for digital power.

Embodiment:

Below in conjunction with accompanying drawing the principle and the characteristic of the utility model are described, institute gives an actual example and only is used to explain the utility model, is not the scope that is used to limit the utility model.

Embodiment 1: see Fig. 1, shown in Figure 2; A kind of ion is controlled cancer accelerator digital power regulating system; Comprise fpga chip 1; Also comprise as non-volatile memory device deposit the upper layer software (applications) program Flash module 2 of writing based on programmable system on chip, internal storage location synchronous DRAM (SDRAM) 3, the debugging of static RAM (SSRAM) 4, system synchronously during as the upper layer software (applications) program running connects jtag interface 5, in order to the Ethernet chip 6 that realizes fpga chip 1 and the network service of remote computer, in order to the fiber optic receiver 7 that receives fiber-optic signal, in order to universal asynchronous reception/dispensing device (UART) serial communication device 8 and the serial memory (EPCS) 13 of the serial communication that realizes fpga chip 4, become digital quantity to send into the ADC analog to digital converter 9 of fpga chip 1, convert the intermediate variable of fpga chip 1 interior digital power to DAC digital to analog converter 10 that analog quantity is exported the output current of digital power or voltage transitions, all the pin with fpga chip 1 links to each other; Comprise that also multiple power source error protection signal input channel module 11 and pulse-width modulation (PWM) signal output channels module 12 all directly are connected to the general pin of fpga chip 1; Pulse-width modulation (PWM) signal output channels module 12 makes the given current value of power supply output through the turning on and off of pulse-width modulation (PWM) signal controlling insulated gate bipolar transistor (IGBT) of the certain duty ratio of output.The model of described fpga chip 1 is the Cyclone II EP2C70 of U.S. altera corp.

Synchronous DRAM 3 is following storage area according to the address static division, comprises Data Update sign 31, high accuracy number regulator parameter district 32,35,2 intermediate variable districts 36,34,2 interpolation given areas, 33,256 impulse waveform districts of dc area, current given waveform address 37, next given waveform address 38, current given waveform length 39, next given waveform length 40, receives buffer area 41.Synchronous DRAM 3 is the mode of static memory and ping-pong operation.

Described fpga chip 1 is attend system and is divided into communication domain 14 and regulates territory 15;

Described communication domain 14 comprises a Nios II cpu141, and ethernet controller 142, synchronously optical fiber assembly module 143, universal asynchronous reception/dispensing device (UART) nuclear 144 are connected to a Nios II cpu141 through Avalon bus 145; Nios II cpu141 controls Ethernet chip 6 on the FPGA hardware platform through ethernet controller 142, universal asynchronous reception/dispensing device (UART) serial communication device 8 of controlling on the FPGA hardware platform through universal asynchronous reception/dispensing device (UART) nuclear 144; The synchronous IP kernel described for the hardware description language of optical fiber assembly module 143, a Nios II cpu through it to the synchronizable optical optical fiber signaling of the fiber optic receiver reception row decoding of going forward side by side; Described communication domain comprises that also first timer 146, first WatchDog Timer (Watch Dog) 147, clock phase-locked loop (PLL) 148, boundary scan universal asynchronous receiving-transmitting transmitter (JTAG UART) 149 are connected to the Nios II cpu of communication domain through Avalon bus 145; First timer is as the system clock of on programmable system on chip, transplanting embedded OS; Boundary scan universal asynchronous receiving-transmitting transmitter (JTAG UART) 149 is the debugging interface of synchro system; The clock that clock phase-locked loop occured frequently in 148 minutes offers Nios II cpu141 and other assemblies through the Avalon bus; WatchDog Timer 147, the operation of monitoring main program prevents program generation endless loop.

Described adjusting territory 15 comprises the 2nd Nios II cpu151; Second timer 152, second WatchDog Timer (Watch Dog) 153 are connected to the 2nd Nios II cpu through the 2nd Avalon bus 154, and wherein the 2nd Nios II cpu151 is attached thereto the second timer 152 that connects through 154 controls of the 2nd Avalon bus; Second WatchDog Timer (Watch Dog) 151, the operation of monitoring main program prevents program generation endless loop.

Described fpga chip is attend system and is also included shared domain 16; Described shared domain comprises serial memory (EPCS) controller 161, Flash controller 162, synchronous DRAM (SDRAM) controller 163, synchronous static RAM (SSRAM) controller 164, general high accuracy number adjuster 165; Its connected mode is serial memory (EPCS) controller 151, Flash controller 152, synchronous DRAM (SDRAM) controller 153, static RAM (SSRAM) controller 154, general high accuracy number adjuster are connected to a Nios II cpu of communication domain and the 2nd Nios II cpu in adjusting territory respectively through the first and second Avalon buses synchronously; Wherein, described high accuracy number adjuster is to upgrade with given and intermediate variable when preserving its calculating by the interrupt service subroutine of second timer 152.Message communicating and exchanges data are carried out in the communication domain memory block shared thus with regulating the territory, and the impulse waveform of completion regulating system is exported and switched.

Described synchronous optical fiber assembly module comprises synchronous example table memory block, example decoding unit, and the signal of telecommunication that the example decoding unit will be sent into synchronous optical fiber assembly module is deciphered according to amplitude and frequency and decoding is sent to current example memory block and stores; Also include the example matching unit, the example matching unit matees current example memory block and synchronous example table memory block, and the example in the current example memory block is identical with arbitrary example in the synchronous example table, then sends synchronizing signal.

Described general high accuracy number adjuster 165 is that the ion that the hardware language descriptive language is described is controlled cancer accelerator digital power IP kernel with synchronous optical fiber assembly module 143; Be embedded into fpga chip according to Avalon EBI standard and attend in the system, Nios II cpu reads and writes control through the Avalon data/address bus to the register of bottom.

A kind of ion that uses this system to realize is controlled the control method of cancer accelerator digital power, and its job step is:

1) remote computer passes synchronous example table down to synchronous optical fiber assembly module from Ethernet chip, universal asynchronous reception/dispensing device serial communication device;

2) fiber optic receiver receives when preamble example signal, will work as the preamble example by synchronous optical fiber assembly module and mate with synchronous example table, sends synchronizing signal;

3) be the example of waveform interpolation if work as the preamble example in the step (2); This moment, communication domain can be carried out interpolation to original waveform; And write the interpolation given area of synchronous DRAM in the shared domain, upgrade next given waveform address simultaneously, when next given waveform length; In this process; Regulate the still general high accuracy number adjuster of may command of territory; Peek from the current waveform district of synchronous DRAM by certain time interval; Calculate the duty ratio and the phase place of pulse-width signal output, digital power is delivered to by the output of pulse-width signal output channel module in the back, and digital power is organized pulse-width modulation letter signal thus and exported corresponding current waveform;

If the synchronous example in the step (2) is for triggering the waveform example; Communication domain can be made amendment to the flag bit of synchronous DRAM in the shared domain; Notice is regulated the territory has new events; Current given waveform address is given with next given waveform address assignment of synchronous DRAM in the shared domain earlier in the adjusting territory, gives current given waveform length when next given waveform length assignment, and general high accuracy number adjuster is controlled in the back; Peek from the current waveform district of synchronous DRAM by certain time interval; Calculate the duty ratio and the phase place of pulse-width signal output, digital power is delivered to by the output of pulse-width signal output channel module in the back, and digital power is organized pulse-width signal thus and exported corresponding current waveform.

4) repeat the continuous output that above process then can realize impulse waveform;

5) interpolation waveform example in the described step (3) requires the waveform of interpolation and last time exported differently, realizes that then becoming impulse waveform exports.

The synchronous example data format that relates in the above-mentioned flow process is 32 bits, and example can be divided into interpolation waveform example and trigger the waveform example according to type.Comprise example and example time-delay synchronously in the example table, each example is 32 bits; When example time-delay clock number representes that synchro system receives this example; The clock number that should delay time and respond; Time-delay clock number data format is 32 no symbol shapings, and last 32 unit interval for time-delay of example table, the unit interval of time-delay multiply by the time-delay clock number of example; Then be the actual time delay time of this example, receive that promptly this example sends the delay time of synchronizing signal.

A kind of ion based on the NiosII double-core is controlled cancer accelerator digital power regulating system, is a kind of programmable system on chip based on the FPGA hardware platform on execution mode.Nios CPU on the programmable system on chip, various controller and customization assembly all are positioned on the FPGA.Controller on the programmable system on chip can the control hardware platform on corresponding with it device.Please refer to Fig. 1, control cancer accelerator digital power regulating system based on the ion of NiosII double-core and on system configuration, be divided into communication domain, shared domain, adjusting territory; Communication domain comprises Nios II cpu, ethernet controller, optical fiber assembly module, timer, Watch Dog, the universal asynchronous reception/dispensing device of JTAG (UART), PLL, universal asynchronous reception/dispensing device (UART) are examined synchronously, and its connected mode is an ethernet controller, optical fiber assembly module, timer, Watch Dog, the universal asynchronous reception/dispensing device of JTAG (UART), PLL, universal asynchronous reception/dispensing device (UART) are connected to communication domain Nios II cpu through the Avalon bus synchronously; Regulate the territory and comprise timer, Nios II cpu, Watch Dog, its connected mode is that timer, Watch Dog are connected to adjusting territory Nios II cpu through the Avalon bus; Shared domain comprises EPCS controller, Flash controller, sdram controller, SSRAM controller, general high accuracy number adjuster, and its connected mode is that EPCS controller, Flash controller, sdram controller, SSRAM controller, general high accuracy number adjuster are connected to communication domain Nios II cpu respectively and regulate territory Nios II cpu through the Avalon bus.

In building the process of above-mentioned programmable system, can correspondingly increase or reduce some controller according to the actual functional capability needs.

Nios II processor is configurable general 32 the RISC soft-core processors of the second generation user of Altera company; Be the distinctive soft CPU kernel based on general FPGA framework of Altera company, its characteristic and peripheral hardware can increase or cutting as required.Have custom instruction, the advantages such as automatic establishment of peripheral configuration and map addresses and system flexibly.The Avalon bus is the comparatively simple bus on chip of a kind of agreement, and Nios II cpu carries out exchanges data through the Avalon bus and the external world.The software that uses during regulating system in the design of graphics 1 is the universal asynchronous reception/dispensing device of Q (UART) us II IDE.To this communication domain with regulate two in territory independently the programmable system on chip software of writing use that carries out upper layer software (applications) be Nios II IDE.

Controlling the employed hardware platform of cancer accelerator digital power regulating system based on the ion of NiosII double-core is Altera Cyclone II EP2C70 FPGA digital circuit board; Adopt 8 layers of printed board structure; Altera Cyclone II EP2C70 is a core devices; Adopt the high-speed figure isolating device in the hardware circuit, had good antijamming capability.Please refer to Fig. 2, the FPGA digital circuit board comprises core devices Altera Cylone II EP2C70 FPGA and peripheral components too web-roll core sheet, fiber optic receiver, Flash, SDRAM, SSRAM, EPCS, universal asynchronous reception/dispensing device (UART) serial communication device, ADC module, DAC module, multiple power source error protection signal input channel module, pwm signal output channel module on hardware is formed.On connected mode, peripheral components all links to each other with core devices Altera Cylone II EP2C70 FPGA pin.

In the above-mentioned EP2C70 FPGA digital circuit board, Flash deposits the upper layer software (applications) program of writing based on programmable system on chip as non-volatile memory device; SDRAM, the SSRAM internal storage location during as the upper layer software (applications) program running; JTAG is the debugging interface of system; Ethernet chip is in order to realize the network service of EP2C70 FPGA and remote computer; Fiber optic receiver is in order to receiving fiber-optic signal, and accomplishes opto-electronic conversion by hardware, and the signal of telecommunication after the conversion is sent into EP2C70 FPGA pin; Universal asynchronous reception/dispensing device (UART) serial communication device is in order to realize the serial communication of EP2C70 FPGA; The ADC analog to digital converter becomes digital quantity to send into EP2C70 FPGA the output current or the voltage transitions of digital power; The DAC digital to analog converter converts the intermediate variable of digital power in the EP2C70 FPGA to analog quantity output; Multiple power source error protection signal input channel module and pwm signal output channel module directly are connected to the general pin of EP2C70 FPGA through level shifting circuit; Pwm signal output channel module is controlled turning on and off of IGBT through the pwm signal of exporting certain duty ratio, makes the given current value of power supply output.

Control the digital power that cancer accelerator digital power controlling object that regulating system is used is based on H bridge topological structure based on the ion of NiosII double-core.The H bridge direct current/pulse switch power supply topological structure of Fig. 4 for simplifying.In the real figure power supply, various topological structures can be arranged, for example many H bridge string and structure only are example with the simplified structure at this, explain the principle of regulating system control figure power supply output.Please refer to Fig. 4; V1, V2, V3, V4 are respectively the IGBT on 4 brachium pontis of H bridge; General high accuracy number adjuster in the last programmable system on chip of EP2C70 calculates the duty ratio and the phase place of each road pwm signal through given electric current, by FPGA pin output pwm signal, via the pwm signal output channel module on the FPGA digital circuit board isolate amplify after; Deliver to V1, V2, V3, the V4 of digital power, digital power is exported given electric current thus.

In communication domain; Nios II cpu controls Ethernet chip on the FPGA hardware platform through ethernet controller, controls universal asynchronous reception/dispensing device (UART) serial communication device on the FPGA hardware platform through universal asynchronous reception/dispensing device (UART) nuclear; Timer is as the system clock of on programmable system on chip, transplanting embedded OS; Universal asynchronous reception/the dispensing device of JTAG (UART) is the debugging interface of synchro system; PLL is a clock phase-locked loop, divides the clock that occurs frequently to offer Nios II cpu and other assemblies through the Avalon bus; Watch Dog is a WatchDog Timer, and the operation of monitoring main program prevents program generation endless loop; Synchronously the optical fiber assembly module is the IP kernel that the hardware description language is described, the synchronizable optical optical fiber signaling that Nios II cpu receives fiber optic receiver through it row decoding of going forward side by side.

In regulating the territory, Nios II cpu is attached thereto the timer that connects through the total line traffic control of Avalon, and the interrupt service subroutine of timer upgrades the given of general high accuracy number adjuster and preserve the high accuracy number adjuster intermediate variable when calculating; Watch Dog is a WatchDog Timer, and the operation of monitoring main program prevents program generation endless loop.

In shared domain; EPCS controller, Flash controller, sdram controller, SSRAM controller, general high accuracy number adjuster all can and be regulated territory Nios II cpu read-write control by communication domain Nios II cpu; EPCS controller control EP2C70 FPGA digital circuit board the EPCS chip deposit the hardware configuration information of EP2C70 FPGA; The Flash of Flash controller control deposits communication domain and the elf file of regulating after territory Nios II software program compiles, and the SSRAM of the SDRAM of sdram controller control and the control of SSRAM controller is the communication domain memory block shared with regulating the territory; The ion that general high accuracy number adjuster is described for the hardware description language is controlled cancer accelerator digital power IP kernel; It is the user's peripheral hardware that meets the Avalon bus specification; Major function is the computing of digital regulated ring and the generation of pwm signal; According to Avalon EBI standard; Be embedded in the SOPC system; Nios II cpu can read and write control to the register of bottom through the Avalon data/address bus, and such as the modification of given electric current, regulator parameter, general high accuracy number adjuster can be controlled ADC module, DAC module, multiple power source error protection signal input channel module and the pwm signal output channel module on the EP2C70 FPGA digital circuit board.

By above-mentioned programmable system on chip structure and FPGA digital circuit board platform; Realize aspect at software, communication domain Nios II cpu has transplanted uC/OS II operating system and has realized that network service, serial communication, data interpolating, synchronizable optical optical fiber signaling receive decoding function; Regulating territory Nios II cpu does not have the graft procedure system, the write-back of the given input when realizing the register read-write, power supply direct current/pulsing operation to the general high accuracy number adjuster of User Defined peripheral hardware and the intermediate variable of high accuracy number adjuster computational process.

Communication domain works alone and communicates by letter and exchanges data with two Nios II cpu in regulating the territory, realizes the output and the switching of digital power impulse waveform thus.And the mechanism that realizes this function static memory that to be the SDRAM of shared domain sdram controller control adopt and the mode of ping-pong operation.Use size to need correspondingly cutting amount of capacity perhaps to delete certain controller for the SSRAM on the shared domain, sdram controller according to reality, so this mode is equally applicable to SSRAM after SDRAM is by cutting.Only be example once more with SDRAM.

Like Fig. 3; SDRAM is following storage area according to the address static division, comprises Data Update sign, high accuracy number regulator parameter district, dc area, 256 impulse waveform districts, 2 interpolation given areas, 2 intermediate variable districts, current given waveform address, next given waveform address, current given waveform length, next given waveform length, receives buffer area.The storage area of the numeric representation generation Data Update of Data Update sign upgrades like 0 expression free of data, and the data in the 1 expression high accuracy number regulator parameter district are upgraded; What high accuracy number regulator parameter district stored is the parameter of the general high accuracy number adjuster final updating of User Defined peripheral hardware; Dc area is deposited the given current value of direct current; 256 original pulse waveforms are deposited in 256 impulse waveform districts, promptly do not pass through the bigger at interval given waveform of point of interpolation processing; Deposit through the less at interval given waveform of the point of interpolation processing 2 interpolation given areas; The intermediate variable of general high accuracy number adjuster computational process is deposited in 2 intermediate variable districts; Receive buffer area and deposit the reception data of Ethernet and universal asynchronous reception/dispensing device (UART) serial communication.Communication domain all can be carried out data to the SDRAM that shares with the adjusting domain system and write, and when a side carried out Data Update to SDRAM, an other square tube is crossed the value of data query updating mark can learn it is the Data Update of which memory block.

Under the pulsed mode of digital power; The communication domain system need upgrade the interpolation given area according to the next pulse waveform, and still to need to read from the interpolation given area electric current that current given waveform upgrades general high accuracy number adjuster at synchronization given and regulate domain system.Therefore in SDRAM, taked the mode of ping-pong operation, be about to 2 interpolation given areas, one of them is as area in preparation, i.e. writable area, and another one is as working as proparea, i.e. read-only region.Regulate territory Nios II cpu and read when the proparea data are given as general high accuracy number current regulator, communication domain Nios II cpu is interpolation next pulse waveform in area in preparation; After current impulse waveform output is accomplished; Area in preparation is the good next pulse waveform of interpolation, and area in preparation became and worked as the proparea this moment, supplies to regulate territory Nios II cpu and reads given waveform; When the proparea becomes area in preparation; Supply communication domain Nios II cpu to write the next pulse waveform, so alternately, realize the output and the switching of impulse waveform.According to this mechanism; This execution mode can realize that ion controls the waveform pulse that the single trigger impulse of cancer accelerator digital power, continuous trigger pulse, the same waveform pulse of continuous trigger or continuous trigger change, and can be implemented in to carry out zero-clearance between 256 impulse waveforms and switch.

This execution mode not only can be operated in the pulse mode that ion is controlled cancer accelerator digital power, but also can be operated in the direct current mode.Support for the DC operation mode; The processing of in execution mode, being done is with given one section rising edge of a pulse or the trailing edge of being interpolated to of direct current; Waveform after this interpolation is treated as common impulse waveform; Only do single and trigger, make general high accuracy number adjuster keep last given current value, that is to say the direct current set-point.

The mode of taking for 2 intermediate variable districts also is a ping-pong operation mode as above: 2 intermediate variable districts, and one of them is as area in preparation, i.e. writable area, another one is as working as proparea, i.e. read-only region; The intermediate variable that adjusting territory Nios II cpu reads general high accuracy number adjuster is written into area in preparation; Communication domain Nios II cpu can read the data of in the proparea, storing it is forwarded to remote terminal by Ethernet or universal asynchronous reception/dispensing device (UART) serial communication device; Area in preparation became and works as the proparea after communication domain Nios II cpu reading of data was accomplished; Supply communication domain Nios II cpu to read; When the proparea becomes area in preparation, supply to regulate territory Nios II cpu and write, so alternately.

The above is merely the preferred embodiment of the utility model, and is in order to restriction the utility model, not all within the spirit and principle of the utility model, any modification of being done, is equal to replacement, improvement etc., all should be included within the protection range of the utility model.

Claims (8)

1. an ion is controlled cancer accelerator digital power regulating system; Comprise fpga chip; It is characterized in that, also comprise as non-volatile memory device deposit the upper layer software (applications) program Flash module of writing based on programmable system on chip, internal storage location synchronous DRAM, the debugging of static RAM, system synchronously during as the upper layer software (applications) program running connects jtag interface, in order to the Ethernet chip that realizes fpga chip and the network service of remote computer, in order to the fiber optic receiver that receives fiber-optic signal, in order to the universal asynchronous reception/dispensing device serial communication device and the serial memory of the serial communication that realizes fpga chip, with the output current of digital power or voltage transitions become digital quantity to send into the ADC analog to digital converter of fpga chip, the DAC digital to analog converter that converts the intermediate variable of digital power in the fpga chip to analog quantity output all links to each other with the pin of fpga chip; Comprise that also multiple power source error protection signal input channel module and pulse-width signal output channel module directly are connected to the general pin of fpga chip; Pulse width modulating signal output channel module is controlled turning on and off of insulated gate bipolar transistor through the pulse width modulating signal of exporting certain duty ratio, makes the given current value of power supply output.

2. ion as claimed in claim 1 is controlled cancer accelerator digital power regulating system, it is characterized in that, the model of described fpga chip is the Cyclone II EP2C70 of U.S. altera corp.

3. ion as claimed in claim 1 is controlled cancer accelerator digital power regulating system; It is characterized in that; Synchronous DRAM is following storage area according to the address static division, comprises Data Update sign, high accuracy number regulator parameter district, dc area, 256 impulse waveform districts, 2 interpolation given areas, 2 intermediate variable districts, current given waveform address, next given waveform address, current given waveform length, next given waveform length, receives buffer area.

4. ion as claimed in claim 1 is controlled cancer accelerator digital power regulating system, it is characterized in that, described fpga chip is attend system and is divided into communication domain and regulates the territory;

Described communication domain comprises a Nios II cpu, and ethernet controller, universal asynchronous reception/dispensing device nuclear are connected to a Nios II cpu through an Avalon bus; The one Nios II cpu controls Ethernet chip on the FPGA hardware platform through ethernet controller, examines universal asynchronous reception/dispensing device serial communication device of controlling on the FPGA hardware platform through universal asynchronous reception/dispensing device;

Described adjusting territory comprises the 2nd Nios II cpu; Second timer, second WatchDog Timer are connected to the 2nd Nios II cpu through the 2nd Avalon bus, and wherein the 2nd Nios II cpu is attached thereto the second timer that connects through the total line traffic control of the 2nd Avalon; Second WatchDog Timer, the operation of monitoring main program prevents program generation endless loop.

5. ion as claimed in claim 4 is controlled cancer accelerator digital power regulating system; It is characterized in that described communication domain comprises that also first timer, first WatchDog Timer, clock phase-locked loop, boundary scan universal asynchronous receiving-transmitting transmitter are connected to a Nios II cpu through an Avalon bus; First timer is as the system clock of on programmable system on chip, transplanting embedded OS; The boundary scan universal asynchronous receiving-transmitting transmitter is the debugging interface of synchro system; The clock that the clock phase-locked loop branch occurs frequently offers a Nios II cpu and other assemblies through an Avalon bus; First WatchDog Timer, the operation of monitoring main program prevents program generation endless loop.

6. ion as claimed in claim 4 is controlled cancer accelerator digital power regulating system; It is characterized in that; Described fpga chip is attend system and is also included shared domain; Described shared domain comprises serial memory controller, Flash controller, controller of synchronous dynamic random storage, synchronous static RAM controller, general high accuracy number adjuster, and its connected mode is serial memory controller, Flash controller, controller of synchronous dynamic random storage, static RAM controller, general high accuracy number adjuster are connected to a Nios II cpu of communication domain and the 2nd Nios II cpu in adjusting territory respectively through an Avalon bus of communication domain and the 2nd Avalon bus in adjusting territory synchronously; Wherein, Described high accuracy number adjuster is to upgrade with given and intermediate variable when preserving its calculating by the interrupt service subroutine of second timer 152; Described communication domain is carried out message communicating and exchanges data with the adjusting territory by the memory block of sharing, and the impulse waveform of completion regulating system is exported and switched.

7. control cancer accelerator digital power regulating system like claim 4 or 6 described ions; It is characterized in that; Described general high accuracy number adjuster is that the ion that the hardware language descriptive language is described is controlled cancer accelerator digital power IP kernel with synchronous optical fiber assembly module; Be embedded into fpga chip according to Avalon EBI standard and attend in the system, Nios II cpu reads and writes control through the Avalon data/address bus to the register of bottom.

8. ion as claimed in claim 4 is controlled cancer accelerator digital power regulating system; It is characterized in that; Described synchronous optical fiber assembly module comprises synchronous example table memory block, example decoding unit, and the signal of telecommunication that the example decoding unit will be sent into synchronous optical fiber assembly module is deciphered according to amplitude and frequency and decoding is sent to current example memory block and stores; Also include the example matching unit, the example matching unit matees current example memory block and synchronous example table memory block, and the example in the current example memory block is identical with arbitrary example in the synchronous example table, then sends synchronizing signal.

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