CN202183093U - Configuration management unit for reconfigurable system - Google Patents
Configuration management unit for reconfigurable system Download PDFInfo
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- CN202183093U CN202183093U CN2011203373852U CN201120337385U CN202183093U CN 202183093 U CN202183093 U CN 202183093U CN 2011203373852 U CN2011203373852 U CN 2011203373852U CN 201120337385 U CN201120337385 U CN 201120337385U CN 202183093 U CN202183093 U CN 202183093U
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Abstract
The utility model discloses a configuration management unit for reconfigurable system. The configuration management unit comprises a micro-processing array module, an off-chip memory interface module and a configuration information cache module. An external signal is transmitted to the micro-processing array module through the off-chip memory interface module and then is transmitted to the configuration information cache module. In this way, the processing efficiency for configuration information is improved, and the configuration management mode in the traditional coarsness reconfigurable system is changed, therefore, the dynamic reconfiguration efficiency of a complex coarsness reconfigurable system is improved.
Description
Technical field
The utility model relates to the imbedded reconfigurable design field, particularly, relates to a kind of configuration management element that is used for reconfigurable system.
Background technology
Appearance along with FPGA restructural technology; Big about-face the method for traditional embedded design; Restructural calculates the computation schema as a kind of novel time-space domain, has application prospect widely in embedded and high performance computing field, has become the current embedded system Development Trend.The development of local dynamic reconfigurable technology; Represented a kind of new reconfigurable design thought, be made up of microprocessor and reconfigurable hardware mostly, reconfigurable hardware can adopt the fine granularity logical block of FPGA; It also can be the coarseness module of specific function; Make that the execution of hardware capability is more flexible, all the more not obvious of the wide gap between the software and hardware, hardware task can be according to demand as software task flexible invocation and configuration.But the energy utilization that how the local dynamic reconfigurable system utilizes the software and hardware coordinated operation to handle is improved system has become a factor of restriction restructural technical development.
At present; Traditional FPGA (Field Programmable Gate Array; Field programmable gate array) basic processing unit that is comprised in is that unit comes deal with data with bit (bit-level); Profuse ICR interconnect resource is provided between the arithmetic element, can realize complicated sequential and combinational logic circuit function easily, so flexibility ratio has been very high.But when execution is the computing of unit (word-level) with the byte, exist many shortcomings: interconnection cost expense is big, the chip area utilization factor is low, thereby causes the performance power consumption of system lower than very.
The data bit width of the basic processing unit that granularity is meant in the reconfigurable system to be comprised, it has determined the data-handling capacity of reconfigurable system.The granularity of reconfigurable system can be divided into fine granularity and coarseness.Generally granularity is no more than 4 the fine granularity that is called, greater than 4 the coarseness that is called.The versatility of fine granularity reconfigurable system is good, but configuration is very complicated usually, like FPGA.To certain applications field (like multimedia processing etc.) design, optimize, dispose also much relatively simple usually by arithmetic element and interconnection structure for the coarseness reconfigurable system.Different with the fine granularity reconfigurable system, as to be comprised in coarseness reconfigurable system basic processing units, being fit to very much carry out data bit width is the data operation of byte, can obtain better can loss-rate more than FPGA.Therefore the coarseness reconfigurable system has remedied the shortcoming that exists in the above-mentioned fine granularity reconfigurable system well; Being fit to very much be used for realizing comprising a large amount of is all kinds of practical applications of the computing of unit with the byte, mainly comprises: video image processing, digital signal processing, radio communication, data encryption etc.
And along with the continuous expansion of coarseness reconfigurable arrays scale; Need be also more and more in the array by the number of the computing unit of reconstruct; The required configuration information data volume of restructuring procedure further increases; The time of dynamic restructuring also increases thereupon, and in the design of coarseness reconfigurable system, the management method of configuration information has determined the efficient of dynamic restructuring.Traditional configuration information management mode to the coarseness reconfigurable system can not be in time, effectively configuration information is transferred to the coarseness reconfigurable arrays, thereby limited the lifting of coarseness reconfigurable system serviceability.
The utility model content
The purpose of the utility model is, to the problems referred to above, proposes a kind of configuration management element that is used for reconfigurable system, to realize improving the advantage of complicated coarseness reconfigurable system dynamic restructuring efficient.
For realizing above-mentioned purpose, the technical scheme that the utility model adopts is:
A kind of configuration management element that is used for reconfigurable system comprises little processing array module, sheet external memory interface module and configuration information cache module; External signal is transferred to little processing array module through sheet external memory interface module, is transferred to the configuration information cache module then.
Preferred embodiment according to the utility model; Said little processing array module; Comprise N microprocessing unit, a M location of instruction, mailbox array and control module, the said location of instruction, mailbox array and control module all are connected electrically on the microprocessing unit.
Preferred embodiment according to the utility model; Said microprocessing unit; Comprise microprocessor, instruction cache unit, local storage unit, status register file and control register file, said instruction cache unit, local storage unit, status register file and control register file all and microprocessor be electrically connected.
According to the preferred embodiment of the utility model, said configuration information cache module comprises configuration words buffer memory, configure packet buffer memory and configure packet interpreter.
Preferred embodiment according to the utility model; Said little processing array module: be used to resolve the instruction block of obtaining from external memory storage; Draw the subalgorithm that on reconfigurable processing unit, to carry out, and generate configuration words, and this configuration words is outputed to the configuration information cache module;
Said external memory interface module: be used to realize that microprocessing unit is communicated by letter with external memory storage foundation in above-mentioned little processing array module;
Said configuration information cache module: be used for configuration words that the above-mentioned little processing array of buffer memory generates, look ahead and configure packet that buffer memory is prefetched to from external memory storage; And this configure packet resolved into the configuration information kernel, send to corresponding reconfigurable processing unit.
According to the preferred embodiment of the utility model, said microprocessing unit: be used to resolve the instruction block of obtaining from external memory storage, and with this instruction block and generate configuration words;
The said location of instruction: the instruction code that is used to deposit above-mentioned microprocessing unit;
Said mailbox array: be used to realize between the above-mentioned microprocessing unit and microprocessing unit and main control processor between communicate by letter;
Said control module: be used to arbitrate and dispatch the externally control of output of an above-mentioned N microprocessing unit.
According to the preferred embodiment of the utility model, said microprocessor: be used to resolve and carry out corresponding instruction;
Said instruction cache unit: instruction with buffer memory microprocessor needs is used to look ahead;
Said local storage unit: be used for the intermediate data that storage microprocessor execution command process produces;
Said status register file: be used to explain the duty of microprocessor, comprised the interrupt status register that is used to explain the Interrupt Process state;
Said control register file: be used for the course of work of control microprocessor, comprised the Clock management register that is used to enable and close the microprocessor driven clock.
According to the preferred embodiment of the utility model, said configuration information cache module comprises:
Configuration words buffer memory: be used for the cached configuration word;
Configure packet buffer memory: be used for the cached configuration packets of information;
The configure packet interpreter, the configuration information kernel that is used for configure packet is comprised decomposes out.
And a kind of method of reconfigurable system configuration management, may further comprise the steps:
Generate configuration words: the instruction block that the little processing array in the said configuration management element is obtained according to external memory storage; Distribution and parsing at the enterprising line algorithm of reconfigurable processing unit; And the generation configuration words, this configuration words is outputed in the configuration words buffer memory in the configuration information cache module;
Looking ahead of configure packet: said configuration management element is through resolving the above-mentioned configuration words that is buffered in the configuration words buffer memory; Obtain configure packet; If required configuration information wraps in the configure packet buffer memory and exists; Then this configure packet is duplicated portion, add to again in the configure packet buffer memory; If do not exist, then from external memory storage, obtain required configure packet, and then add in the configure packet buffer memory;
The transmission of configuration information kernel: the configuration information kernel that said configuration management element will be included in the configure packet to be comprised sends to corresponding reconfigurable arrays, the corresponding reconfigurable arrays of reconstruct successively.
The technical scheme of the utility model makes the configuration information that is used for the reconstruct reconfigurable processing unit can output to corresponding reconfigurable processing unit accurately and efficiently through a kind of configuration management element is provided, and has improved the treatment effeciency of configuration information.And a kind of configuring management method of three grades of flowing water is provided, change the configuration management mode in traditional coarseness reconfigurable system, thereby improved the dynamic restructuring efficient of complicated coarseness reconfigurable system.
Further feature of the utility model and advantage will be set forth in instructions subsequently, and, partly from instructions, become obvious, perhaps understand through implementing the utility model.The purpose of the utility model can realize through the structure that in the instructions of being write, claims and accompanying drawing, is particularly pointed out and obtain with other advantages.
Through accompanying drawing and embodiment, the technical scheme of the utility model is done further detailed description below.
Description of drawings
Accompanying drawing is used to provide the further understanding to the utility model, and constitutes the part of instructions, is used to explain the utility model with the embodiment of the utility model, does not constitute the restriction to the utility model.In the accompanying drawings:
Fig. 1 is the described structural representation that is used for the configuration management element of reconfigurable system of the utility model embodiment;
Fig. 2 is the structural representation of the configuration management element microprocessing unit that is used for reconfigurable system shown in Figure 1;
Fig. 3 is used for the configuration management element of reconfigurable system and uses connection layout for the utility model embodiment is described;
Fig. 4 is the process flow diagram of the method for the described realization reconfigurable system of the utility model embodiment configuration management.
Embodiment
Describe below in conjunction with the preferred embodiment of accompanying drawing, should be appreciated that preferred embodiment described herein only is used for explanation and explains the utility model, and be not used in qualification the utility model the utility model.
As shown in Figure 1; The configuration management element that is used for reconfigurable system; Comprise little processing array module: be used to resolve the instruction block of obtaining from external memory storage; Draw the subalgorithm that on reconfigurable processing unit, to carry out, and generate configuration words, and this configuration words is outputed to the configuration information cache module; Sheet external memory interface module: be used to realize that microprocessing unit is communicated by letter with external memory storage foundation in little processing array module; Configuration information cache module: be used for configuration words that the little processing array of buffer memory generates, look ahead and configure packet that buffer memory is prefetched to from external memory storage, and this configure packet is resolved into the configuration information kernel, send to corresponding reconfigurable processing unit.Wherein little processing array module comprises N microprocessing unit, a M location of instruction, mailbox array and control module; Microprocessing unit: be used to resolve the instruction block of obtaining from external memory storage, and with this instruction block and generate configuration words; The location of instruction: the instruction code that is used to deposit microprocessing unit; The mailbox array: be used to realize between the microprocessing unit and microprocessing unit and main control processor between communicate by letter; Control module: be used to arbitrate and dispatch the externally control of output of N microprocessing unit.The configuration information cache module comprises: the configuration words buffer memory: be used for the cached configuration word; Configure packet buffer memory: be used for the cached configuration packets of information; The configure packet interpreter, the configuration information kernel that is used for configure packet is comprised decomposes out.
μ PA can comprise N μ PE, the total M piece (M is smaller or equal to N) of instruction RAM.From the consideration of power consumption and area overhead, adjacent a plurality of μ PE share a block instruction RAM.Be to be that 4 μ PE share an instruction RAM shown in Fig. 1, in practical application, can take all factors into consideration the influence of performance and power consumption, the concrete selection is that several μ PE share an instruction RAM.
Mailbox array submodule, be used between a plurality of μ PE and μ PE and main control processor between communicate by letter.N+1 mailbox (Mail Box) arranged in the mailbox array submodule 4, be numbered #0 ~ #N, respectively as the exclusive inbox of N+1 equipment.Mailbox #0 is the inbox of main control processor, and mailbox # 1 ~ mailbox #N is respectively the inbox of μ PE# 1 ~ μ PE#N.Comprise a FIFO in each mailbox, can preserve many envelope mails.
The mechanism of mail communication can be divided into: a) synchronous communication between the μ PE.For example, when μ PE# 1 complete operation, when needing notice μ PE#2 start-up operation, then μ PE# 1 sends an envelope mail for the inbox of μ PE#2.When the inbox of μ PE#2 is received this envelope mail, can send a FIQ to μ PE#2 and interrupt (if the current clock of μ PE#2 is to close, then open the clock of μ PE#2 simultaneously, wake μ PE#2 up), notice μ PE#2 receives mail.μ PE#2 is through reading and inquire about this envelope mail in the mailbox then, and discovery can start work, forwards executing state to.B) master cpu is to specifying μ PE to send control information.For example, when main control processor need dispose μ PE# 1, master cpu at first sent an envelope mail to mailbox #1.When mailbox # 1 receives this envelope mail, send FIQ to μ PE# 1 and interrupt (open the clock of μ PE# 1 simultaneously, wake μ PE# 1 up), notice μ PE# 1 reads this envelope mail.μ PE# 1 obtains the control information that master control ARM sends through reading and inquire about this envelope mail in the mailbox then.
The control module submodule is used for arbitrating and dispatching the control that the external configuration words of a plurality of μ PE of μ PA is exported.Have the output of a N position to allow register in the control module submodule, whether its 0th ~ (N-1) output that identifies μ PE# 1 ~ μ PE#N successively is allowed to.Because can only there be simultaneously a μ PE to be allowed to output, thus output allow to show with only thermal meter code, be carved with when any and have only 1 to be effectively (value is " 1 ").It is " 0x1 " that output allows the initial value of register, and expression μ PE# 1 is allowed to output.Export and allow register still to have only effective that μ PE of current output just can go to reset the value that output allows register simultaneously by N μ PE visit.When certain μ PE need be with the configuration words output that generates, at first inquiry output allowed whether the corresponding position of register is effectively, if invalid then continue poll, if effectively, explained that then this μ PE can be with the configuration words output of its generation.When μ PE accomplishes output; This μ PE will reset the value that output allows register: remove current significance bit; The Gao Yiwei of current significance bit is set to effectively (if current significance bit is the N-1 position simultaneously; Then be provided with the 0th for effective), thus the output of next μ PE is set to allow.
Configuration information cache module comprises: configuration words FIFO submodule, configure packet FIFO submodule, configure packet interpreter submodule.Wherein, configuration words FIFO is used for the configuration words that buffer memory μ PA generates; Configure packet FIFO is used for the configure packet that buffer memory obtains from external memory storage through the sheet external memory interface, if required configuration information wraps among the configure packet FIFO and exists, then it is duplicated portion, adds to again among the configure packet FIFO; The configuration information kernel that the configure packet interpreter is used for configure packet is comprised decomposes out, and sends to corresponding RPU.
As shown in Figure 2, in microprocessing unit, comprise microprocessor, instruction cache unit, local storage unit, status register file and control register file again.Said microprocessor: be used to resolve and carry out corresponding instruction; The instruction cache unit: instruction with buffer memory microprocessor needs is used to look ahead; Local storage unit: be used for the intermediate data that storage microprocessor execution command process produces; Status register file: be used to explain the duty of microprocessor, comprised the interrupt status register that is used to explain the Interrupt Process state; Control register file: be used for the course of work of control microprocessor, comprised the Clock management register that is used to enable and close the microprocessor driven clock.
Each μ PE comprises: μ P, command cache, local RAM and state and control register file.Wherein, μ P adopts a RSIC processor to realize; Command cache is used for the instruction that this μ P of buffer memory carries out, and is read-only for μ P; Local RAM is used for store data, writes for μ P is readable; Comprise Clock management register, interrupt status register in state and the control register file.
The Clock management register is a low power dissipation design.After the program of initialization μ PE, master control ARM can enable this register through sending mail, thereby starts μ P.μ P can close the clock of μ P through with this register zero setting, thereby makes μ P get into low power consumpting state; After μ P gets into low-power consumption mode, come from the look-at-me (when the mail that is not read is arranged in the mailbox, producing) of mailbox, the look-at-me of RPU all can be recovered this position, thereby wake μ P up.
Interrupt status register is used to receive the look-at-me from different interrupt sources, and determines the limit priority in all look-at-mes, and according to priority order sends to μ P.Comprised 2 groups * 4 registers in the interrupt status register, be respectively applied for and handle IRQ and FIQ interruption.The interrupt source of IRQ is outside RPU, and the interrupt source of FIQ is the corresponding mailbox of this μ PE.
As shown in Figure 4; The method of reconfigurable system configuration management; Comprise the generation configuration words: the instruction block that the little processing array in the configuration management element is obtained according to external memory storage; In the distribution and the parsing of the enterprising line algorithm of reconfigurable processing unit, and generate configuration words, this configuration words is outputed in the configuration words buffer memory in the configuration information cache module; Looking ahead of configure packet: configuration management element is buffered in the configuration words in the configuration words buffer memory through parsing; Obtain configure packet; If required configuration information wraps in the configure packet buffer memory and exists, then this configure packet is duplicated portion, add to again in the configure packet buffer memory; If do not exist, then from external memory storage, obtain required configure packet, and then add in the configure packet buffer memory; The transmission of configuration information kernel: the configuration information kernel that configuration management element will be included in the configure packet to be comprised sends to corresponding reconfigurable arrays, the corresponding reconfigurable arrays of reconstruct successively.
The drive manner of three phases is a pipeline system, thereby has made full use of the resource of configuration management element, has improved the efficient that configuration information is handled.
As shown in Figure 3; H.264 method and configuration management element towards the configuration management of extensive coarseness reconfigurable system that this paper proposed have been adopted in the high-definition digital video of agreement decoding (H.264 1080p30fps HiPLevel4), can realize the H.264 high definition video decoding requirement of 1080p30fps HiPLevel4.The structure of this system comprises: as ARM7TDMI processor, configuration management element CMU, reconfigurable processing unit RPU, ahb bus, the DDR SDRAM of main control processor.The ARM7TDMI processor of advantages such as that selection has is small-sized, quick, low energy consumption, compiler support are good is used for the scheduling of control system operation as main control processor; CMU is connected with external memory storage through the ahb bus of 32bit, and external memory storage is selected the most frequently used embedded external memory storage DDR SDRAM for use, has good cost performance and ability loss-rate; RPU always has two, comprises 4 RCA among each RPU, and each RCA all contains 8 * 8 PE.For this verification system, the size of each corresponding configuration information kernel is 2Kbit.The size of every block instruction RAM is 32KByte among the CMU, and bit wide is 256bit.The mail that every envelope is used to communicate by letter is 32bit; Mail head (the high 5bit of mail by a 5bit; Span 0 ~ 16 identifies master control ARM, μ PE# 1 ~ μ PE#16 successively) and the Mail Contents of a 27bit (the low 27bit of mail, concrete meaning is by software definition) form.In the interrupt status register, the interrupt source of IRQ is 2 outside RPU, and 4 relevant registers are 2bit; The interrupt source of FIQ is the corresponding mailbox of this μ PE, and 4 relevant registers are 1bit.
Wherein reconfigurable processing unit (Reconfigurable Processing Unit) abbreviates RPU as; Configuration management (Configuration Management Unit) abbreviates CMU as; Basic processing unit (Processing Element) is called for short PE; Reconfigurable arrays (ReConfigurable Array) is called for short RCA; Configure packet (context group); Little processing array (micro-Processing Array) is called for short μ PA; Microprocessing unit (micro-Processing Element) is called for short μ PE; Microprocessor (micro-Processor) is called for short μ P; Instruction cache (command cache); Local storage unit (local RAM); Configuration words buffer memory (configuration words FIFO); Configure packet buffer memory (configure packet FIFO); Mailbox (Mail Box).
What should explain at last is: the above is merely the preferred embodiment of the utility model; Be not limited to the utility model; Although the utility model has been carried out detailed explanation with reference to previous embodiment; For a person skilled in the art, it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement.All within the spirit and principle of the utility model, any modification of being done, be equal to replacement, improvement etc., all should be included within the protection domain of the utility model.
Claims (4)
1. a configuration management element that is used for reconfigurable system is characterized in that, comprises little processing array module, sheet external memory interface module and configuration information cache module; External signal is transferred to little processing array module through sheet external memory interface module, is transferred to the configuration information cache module then.
2. the configuration management element that is used for reconfigurable system according to claim 1; It is characterized in that; Said little processing array module; Comprise N microprocessing unit, a M location of instruction, mailbox array and control module, the said location of instruction, mailbox array and control module all are connected electrically on the microprocessing unit.
3. the configuration management element that is used for reconfigurable system according to claim 2; It is characterized in that; Said microprocessing unit; Comprise microprocessor, instruction cache unit, local storage unit, status register file and control register file, said instruction cache unit, local storage unit, status register file and control register file all and microprocessor be electrically connected.
4. the configuration management element that is used for reconfigurable system according to claim 1 is characterized in that, said configuration information cache module comprises configuration words buffer memory, configure packet buffer memory and configure packet interpreter.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279753A (en) * | 2011-09-08 | 2011-12-14 | 无锡东集电子有限责任公司 | Method for configuring and managing reconfigurable system and configuration management unit for reconfigurable system |
| CN102968390A (en) * | 2012-12-13 | 2013-03-13 | 东南大学 | Configuration information cache management method and system based on decoding analysis in advance |
| CN103914404A (en) * | 2014-04-29 | 2014-07-09 | 东南大学 | Configuration information cache device in coarseness reconfigurable system and compression method |
| CN104915213A (en) * | 2015-06-19 | 2015-09-16 | 东南大学 | Partial reconfiguration controller of reconfigurable system |
-
2011
- 2011-09-08 CN CN2011203373852U patent/CN202183093U/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102279753A (en) * | 2011-09-08 | 2011-12-14 | 无锡东集电子有限责任公司 | Method for configuring and managing reconfigurable system and configuration management unit for reconfigurable system |
| CN102279753B (en) * | 2011-09-08 | 2014-03-12 | 无锡东集电子有限责任公司 | Method for configuring and managing reconfigurable system and configuration management unit for reconfigurable system |
| CN102968390A (en) * | 2012-12-13 | 2013-03-13 | 东南大学 | Configuration information cache management method and system based on decoding analysis in advance |
| WO2014090067A1 (en) * | 2012-12-13 | 2014-06-19 | 东南大学 | Pre-decoding analysis-based configuration information cache management method and system |
| CN102968390B (en) * | 2012-12-13 | 2015-02-18 | 东南大学 | Configuration information cache management method and system based on decoding analysis in advance |
| US9632937B2 (en) | 2012-12-13 | 2017-04-25 | Southeast University | Pre-decoding analysis based configuration information cache management method and system |
| CN103914404A (en) * | 2014-04-29 | 2014-07-09 | 东南大学 | Configuration information cache device in coarseness reconfigurable system and compression method |
| CN103914404B (en) * | 2014-04-29 | 2017-05-17 | 东南大学 | Configuration information cache device in coarseness reconfigurable system and compression method |
| CN104915213A (en) * | 2015-06-19 | 2015-09-16 | 东南大学 | Partial reconfiguration controller of reconfigurable system |
| CN104915213B (en) * | 2015-06-19 | 2018-05-18 | 东南大学 | A kind of Partial Reconstruction controller of reconfigurable system |
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Effective date of registration: 20200511 Address after: No.15 Xinghuo Road, Jiangbei new district, Nanjing, Jiangsu Patentee after: JIANGSU SEUIC TECHNOLOGY Co.,Ltd. Address before: 214000 Wuxi national integrated circuit design garden, No. 21-1 Changjiang Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, Wuxi, 606-609 Patentee before: WUXI SEUIC SEMICONDUCTORS Co.,Ltd. |
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Granted publication date: 20120404 |