CN202178776U

CN202178776U - High speed communication system based on CAN bus

Info

Publication number: CN202178776U
Application number: CN2011203080160U
Authority: CN
Inventors: 沈波
Original assignee: Hangzhou Langjie Measuring And Control Technology Development Co Ltd
Current assignee: Hangzhou Langjie Measuring And Control Technology Development Co Ltd
Priority date: 2011-08-23
Filing date: 2011-08-23
Publication date: 2012-03-28
Anticipated expiration: 2021-08-23

Abstract

The utility model discloses a high speed communication system based on a CAN bus, comprising a CPU and a CAN chip, between which a buffer memory module is arranged to realize communication. The data received by the CAN chip is stored in the buffer memory module; the CPU timing polling reads the data in the read buffer memory module. The defect is overcome that in a communication process with the CPU, an existing CAN chip need frequently produce interruption to allow the CPU to read the data, which can reduce the burden of the CPU.

Description

A kind of high-speed communication system based on the CAN bus

Technical field

The utility model relates to a kind of high-speed communication system based on the CAN bus, belongs to the data message communication technique field.

Background technology

CAN (Controller Area Network) is a controller local area network, can belong to the category of industrial field bus, is commonly referred to CAN bus, i.e. CAN bus is one of most widely used open field bus in the world at present.

Compare with general communication bus, the data communication of CAN bus has outstanding reliability, real-time and flexibility, because the advantage of these of CAN is also used very extensive in the automatic measuring and controlling field.If but the CAN controller need be accepted multichannel data or mass data,, need frequent the generation to interrupt letting CPU come reading of data because that existing C AN chip is not with buffer memory or is carried buffer memory capacity is very little; In automation field, CPU is also often bearing other heavy calculation tasks, and so frequent interruption has increased the burden of CPU greatly, has influenced the efficient of TT&C system, and some cpu instruction conflicts with the CAN interrupt instruction each other simultaneously, has increased development difficulty; The CAN control chip takies the CPU hardware resource simultaneously, influences other function of CPU and realizes.

Summary of the invention

The utility model problem to be solved just provides a kind of high-speed communication system based on the CAN bus, and solution has the defective that needs frequent generation interruption let the CPU reading of data in CAN chip and the CPU communication process now, to reduce the burden of CPU.

For solving the problems of the technologies described above; The utility model adopts following technical scheme: a kind of high-speed communication system based on the CAN bus; Comprise CPU and CAN chip; It is characterized in that: realize communication through cache module is set between CPU and the CAN chip, the data that said CAN chip receives exist in the cache module, and said CPU automatic regular polling reads the data in the cache module.

Further, described CAN chip and cache module are integrated in the ARM chip.Simplied system structure, the ARM chip can be used as coprocessor simultaneously, and the data of encapsulation CAN chip further reduce the CPU burden.

The beneficial effect of the utility model: between CAN chip and CPU, increase a cache module; The data that the CAN chip receives pre-exist in the cache module; CPU can automatic regular polling mode read the data in the cache module, needn't frequently interrupt, bother other program running.

Description of drawings

Below in conjunction with accompanying drawing the utility model is done further explanation:

Fig. 1 is the structural representation of the utility model;

Fig. 2 is the preferred structure sketch map of the utility model.

Embodiment

With reference to Fig. 1; A kind of high-speed communication system based on the CAN bus; Comprise CPU1 and CAN chip 3; Realize communication through cache module 2 is set between CPU1 and the CAN chip 3, the data that said CAN chip 3 receives exist in the cache module 2, and said CPU1 automatic regular polling reads the data in the cache module 2.CAN chip 3 needn't frequently produce and interrupt letting the CPU1 reading of data.

With reference to Fig. 2, CAN chip 3 is integrated in the ARM chip 4 with cache module 2, not only can simplied system structure, and ARM chip 4 can be used as coprocessor simultaneously, and the data of encapsulation CAN chip 3 further reduce the CPU1 burden; Can also adjust the size of CAN chip 3 required spatial caches, be applied to the measuring and controlling node of on-the-spot varying number, enough big spatial cache is arranged, guarantee can not lose when mass data receives transmission.

Claims

1. high-speed communication system based on the CAN bus; Comprise CPU (1) and CAN chip (3); It is characterized in that: realize communication through cache module (2) is set between CPU (1) and the CAN chip (3); The data that said CAN chip (3) receives exist in the cache module (2), and said CPU (1) automatic regular polling reads the data in the cache module (2).

2. a kind of high-speed communication system based on the CAN bus according to claim 1 is characterized in that: described CAN chip (3) is integrated in the ARM chip (4) with cache module (2).