CN202094123U

CN202094123U - Array substrate and display equipment

Info

Publication number: CN202094123U
Application number: CN2011202081804U
Authority: CN
Inventors: 李春伟; 田震寰; 白国晓; 林子锦; 杨魏松
Original assignee: Beijing BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2011-06-20
Filing date: 2011-06-20
Publication date: 2011-12-28
Anticipated expiration: 2021-06-20

Abstract

The present utility model discloses an array substrate and a kind of display equipment. The array substrate comprises a common electrode line made with transparent conductive material, and one part of the common electrode line, which is intersected with other lines, has a line width larger than the line width of the other parts of the common electrode line. As in the array substrate, the common electrode line is made with transparent electrodes, the part of the common electrode line intersecting with the other lines is thinner than the other parts of the common electrode line, the parasitic capacitance generated by the common electrode line and the other lines is reduced, and the product performance is increased.

Description

A kind of array base palte and display device

Technical field

The utility model relates to lcd technology, relates in particular to a kind of array base palte and display device.

Background technology

At present, in LCD (Liquid Crystal Display, liquid crystal display) display, TN (Twist Nematic, twisted-nematic) type TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor-LCD) is a type of drive commonly used.Storage capacitors among the TFT-LCD mainly is to be used to carry out power storage, uses when making its charged voltage can remain to next time frame update.

In the manufacturing process of TFT-LCD, normally utilize show electrode and Gate (grid line) cabling or public Common line, form parallel plate capacitor, as the storage capacitors among the TFT-LCD.In order to keep the TFT-LCD pixel when the Gate signal at stop, the voltage of pixel electrode is steady, adopts the method for preparing Common line (public electrode wire) on array base palte usually.But the introducing of Common line must bring following problem:

1, reduced aperture ratio of pixels, because the Common line is light tight, so the Common line is thick more, aperture opening ratio descends many more;

2, in order to guarantee aperture opening ratio, so the general preparation of Common line is thinner, Common Open (public electrode open circuit) badness so just taking place easily, reduces the yield of product;

3, present, TFT-LCD has panel size to do bigger and bigger, the trend that resolution is done higher and higher, therefore the Common line also becomes more and more longer, this can cause the resistance of Common line to increase along with the increase of line length, the increase of electricresistance effect all can cause the decay of Common signal, is difficult to guarantee electric voltage equalization on the Common line.

For overcoming the above problems, π shape, Z-shaped Common line etc. have appearred, can increase Common line area to a certain extent like this, guarantee the voltage of storage capacitance, but the easier resistance of Common line that makes increases, and GCS (Gate Common Shot, grid line-public electrode wire short circuit) badness perhaps takes place easily, and because the Gate layer is to take a sample test after covering, bad reparation after the test leakage.

For addressing the above problem, there is scheme to adopt transparency electrode to make Common line (public electrode wire), that thereby the Common line can be made is very thick, be close to and cover whole pixel, can improve the storage capacitance performance like this, and the yield of aperture ratio of pixels and product is provided, but the present utility model people finds, because the Common line is thicker, the Common line is easy to and circuit such as Data (data) line produces parasitic capacitance, and then influences the performance of product.

The utility model content

The utility model embodiment provides a kind of array base palte and display device, reduces Common line parasitic capacitance with realization, and then enhances product performance.

A kind of array base palte that the utility model provides comprises the public electrode wire that uses transparent conductive material to make, described public electrode wire with the live width of the cross section of other circuit live width less than described public electrode wire remainder.

Described other circuit is specially data wire or grid line.

Described transparent conductive material is specially tin indium oxide.

Perhaps, described transparent conductive material is specially zinc oxide.

The live width of described public electrode wire remainder is greater than 80% of pixel wide.

Described public electrode wire with the live width of the cross section of other circuit less than 50% of the live width of described public electrode wire remainder.

Described public electrode wire is at least 2 sub-public electrode wires at the cross section with other circuit, and the live width of described sub-public electrode wire is less than 50% of the live width of described public electrode wire line remainder.

On the cross section of described public electrode wire and other circuit, be provided with metal level.

Described metallic pattern is specially, the grid metal level that keeps in etching process.

The utility model embodiment also provides a kind of display device, comprises the array base palte that the utility model embodiment provides.

The utility model embodiment provides a kind of array base palte and display device, in this array base palte, use transparency electrode to make the Common line, simultaneously, at Common line and other circuit cross section, the remainder that is narrower than the Common line that the Common line is made, and then reduced the parasitic capacitance of Common line and the generation of other circuit, improved properties of product.

Description of drawings

The array base-plate structure schematic diagram that Fig. 1 provides for the utility model embodiment;

One of preferable array base-plate structure schematic diagram that Fig. 2 provides for the utility model embodiment;

The method flow diagram of the making array base palte that Fig. 3 provides for the utility model embodiment;

Array base-plate structure schematic diagram in the flow process of the making array base palte that Fig. 4 provides for the utility model embodiment after the exposure;

Array base-plate structure schematic diagram in the flow process of the making array base palte that Fig. 5 provides for the utility model embodiment after the etching;

Two of the preferable array base-plate structure schematic diagram that Fig. 6 provides for the utility model embodiment.

Embodiment

The utility model embodiment provides a kind of array base palte and display device, in this array base palte, use transparency electrode to make the Common line, simultaneously, at Common line and other circuit cross section, the remainder that is narrower than the Common line that the Common line is made, and then reduce the parasitic capacitance of Common line and the generation of other circuit, and then enhance product performance.

The array base palte that the utility model embodiment provides comprises as shown in Figure 1:

Glass substrate 1, Gate layer 2 and the Common line 3 that uses transparent conductive material to make, wherein, this Common line 3 with the live width of the cross section of other circuit 4 live width less than Common line remainder.

Usually, Common line 3 is more with the situation that the Data line intersects, thus when intersecting with the Data line, with the live width of cross section make less, can effectively reduce the parasitic capacitance that produces between Common line 3 and the Data line, and then the performance of raising product.

When if other circuits such as Common line 3 and grid line intersect, equally can be with the live width making of cross section less, and then reduce the parasitic capacitance that produces between Common line 3 and the Gate line and then the performance of raising product.

In this use new embodiment, the material of making Common line 3 uses transparent conductive material to get final product, specifically can use materials such as tin indium oxide ITO, zinc oxide ZnO, also can use other material according to actual conditions, the transparency of employed material is high more good more, and its electric conductivity is strong more good more.

Because what Common line 3 adopted is transparent material, so can not influence aperture ratio of pixels, therefore for reducing the resistance of Common line 3, it is bigger that the live width of Common line 3 is all made usually, in the utility model embodiment, Common line 3 is in the part of not intersecting with other circuit 4, and its live width is usually greater than 80% of pixel wide, to reduce the resistance of Common line 3 as far as possible.

In order to reduce parasitic capacitance preferably, Common line 3 is set at less than 50% of the live width of Common line 3 remainders usually in the live width with the cross section of other circuit 4, it is more little that this a part of live width is made, help reducing parasitic capacitance more, so can guarantee to reduce the live width of this part under the situation that Common line 3 can not occur opening a way as far as possible.Certainly, those skilled in the art also can be provided with the live width width of this part flexibly according to actual conditions, thereby when reducing parasitic capacitance, improve the combination property of array base palte.

Further, in order to guarantee Common line 3 open circuits not occur, and when guaranteeing that Common line 3 resistance can be not excessive, reduce parasitic capacitance as much as possible, as shown in Figure 2, the cross section of Common line 3 and other circuit 4 can be made as at least 2 sub-public electrode wires 31, the live width of this sub-public electrode wire 31 is less than 50% of the live width of Common line 3 remainders.

The array base palte that the utility model embodiment provides can adopt following method to make, and as shown in Figure 3, this method comprises:

Step S301, on glass substrate, deposit ITO film (indium tin oxide films) layer and Gate layer metal film successively;

Resist coating on step S302, the Gate layer metal film; If adopt the grating exposure method, the thickness of this photoresist can be identical with the thickness of S/D layer photoetching glue;

Step S303, photoresist is exposed; Array base palte after the exposure in the zone of the exposed glass substrate of needs, exposes to photoresist 5 as shown in Figure 4 fully, in the zone of the exposed ITO film layer of needs, photoresist 5 is not exclusively exposed;

Step S304, use wet etching etch away Gate layer metal film and ITO film layer on the zone of the exposed glass substrate of needs;

Step S305, use dry etching etch away residue photoresist and Gate layer metal film on the zone of the exposed ITO film layer of needs, and the vertical view of the array base palte after the etching as shown in Figure 5.

If will with in the Common line 3 with the cross section of All other routes 4 make thinner, so in step S303, just need make in the Common line 3 and the cross section of All other routes 4 more exposed glass substrates how, like this, when carrying out the etching of step S304 and step S305, can produce the Common line 3 thinner with the cross section of All other routes 4.

Since in step S304 and step S305 respectively to as having carried out etching one time between the ITOfilm layer of Common line 3 and the Gate layer metal film, so experienced twice etching between Common line 3 and the Gate layer metal film, further reduced the possibility of GCS badness.

Flow process among Fig. 3 has realized the making of the array base-plate structure among Fig. 5 by mask, array base-plate structure among Fig. 5 also can be made by twice mask: at first deposit ITO film layer, make the Common line graph behind the mask by lithography, develop then, etch the Common line; Deposit the Gate metal level again, make the Gate line graph behind the mask by lithography, develop then, etch the Gate line.

Further, for fear of Common line 3 meticulous and cause open circuit with the cross section of other circuit 4, also reduce simultaneously the resistance of Common line 3, as shown in Figure 6, can be on the cross section of Common line 3 and other circuit, metal level is set,, has strengthened the conduction of Common line 3 because this metal level is arranged on the thinner part of Common line 3.

For the ease of making, this metal level can directly use the Gate metal level, as long as in the process of etching, the Gate metal level on the cross section of reservation Common line 3 and other circuit gets final product.

The utility model embodiment also provides a kind of display device, comprises the array base palte that the utility model embodiment provides in this display device.

The utility model embodiment provides a kind of array base palte and display device, in this array base palte, use transparency electrode to make the Common line, simultaneously, at Common line and other circuit cross section, the remainder that is narrower than the Common electrode that the Common line is made, and then reduced the parasitic capacitance of Common electrode and the generation of other circuit, improved properties of product.

Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these are revised and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these changes and modification interior.

Claims

1. array base palte comprises the public electrode wire that uses transparent conductive material to make, it is characterized in that, described public electrode wire with the live width of the cross section of other circuit live width less than described public electrode wire remainder.

2. array base palte as claimed in claim 1 is characterized in that, described other circuit is specially data wire or grid line.

3. array base palte as claimed in claim 1 is characterized in that described transparent conductive material is specially tin indium oxide.

4. array base palte as claimed in claim 1 is characterized in that described transparent conductive material is specially zinc oxide.

5. array base palte as claimed in claim 1 is characterized in that the live width of described public electrode wire remainder is greater than 80% of pixel wide.

6. array base palte as claimed in claim 1 is characterized in that, described public electrode wire with the live width of the cross section of other circuit less than 50% of the live width of described public electrode wire remainder.

7. array base palte as claimed in claim 6 is characterized in that, described public electrode wire is at least 2 sub-public electrode wires at the cross section with other circuit, and the live width of described sub-public electrode wire is less than 50% of the live width of described public electrode wire remainder.

8. as the arbitrary described array base palte of claim 1-7, it is characterized in that, on the cross section of described public electrode wire and other circuit, be provided with metal level.

9. array base palte as claimed in claim 8 is characterized in that described metal level is specially, the grid metal level that keeps in etching process.

10. a display device is characterized in that, comprises arbitrary described array base palte as claim 1-9.